Synchronous rectification Buck

MOSFET driver

HIP6601B , HIP6603B and HIP6604B are specially designed for

Synchronously drives two power N-channel mosfet rectifier buck converter topologies. Together these drivers with the HIP63xx or ISL65xx family of multiphase step-down PWM controllers and mosfets form a complete core voltage regulator solution for advanced microprocessors. The HIP6601B drives the lower gate rectified to 12V in a synchronous manner, and the upper gate can operate independently from 5V to 12V. The HIP6603B drive's upper and lower gate drive voltage flexibility in the 5V to 12V range provides an optimized advantage for applications involving switching loss trade-offs as well as conduction losses. HIP6604B can be configured as HIP6601B or HIP6603B. The HIP6601B, HIP6603B, and HIP6604B feature high-efficiency switching power MOSFETs capable of frequencies up to 2 MHz. Each driver is capable of driving a 3000pF load with a 30ns propagation delay and 50ns transition time. These products implement only one external capacitor required. This reduces the complexity of the implementation. and allows the use of higher performance, cost-effective, N-channel MOSFETs. Adaptive penetration protection is integrated to prevent conduction of two mosfets simultaneously

feature

Driving two N-channel mosfets

Adaptive penetration protection

internal boot device

Supports high switching frequencies

Fast output rise time

Propagation delay 30ns

Small 8 Ld SOIC and EPSOIC and 16 Ld QFN packages

Dual gate drive voltages for optimum efficiency

Tri-state input with output stage off

Provides undervoltage protection

QFN package

Compliant with JEDEC PUB95 MO-220 QFN Quad Flat No Potential Customer Product Outline. - Package size close to chip scale; improved PCB efficiency and thinner profile. Lead Free (RoHS Compliant)

application

Core Voltage Power Supply for Intel Pentium III, AMD

Athlon 8482 ; Microprocessor

High Frequency Low Profile DC/DC Converters

High current low voltage DC/DC converter

Technical brief TB363, how-to guide and

Processing Moisture Sensitive Surface Mount Devices (SMD)

notes:

1. These Intersil lead-free plastic packaged products feature a lead-free material set, molding compound/mold connection material, 100% matte tinplate plus annealing (e3 termination, RoHS compliant and operate with SnPb and lead-free soldering). Intersil lead-free products are MSL classifications that meet the lead-free peak reflow temperature or exceed the lead-free requirements of IPC/JEDEC J STD-020.

2. Regarding the humidity sensitivity level (MSL)

Typical Application: 3-Channel Converter Using HIP6301 and HIP6601B Gate Drivers

3. In free air, measure JA with components mounted on a high-efficiency thermal conductivity test board. See Technical Bulletin TB379 for details.

4. θJA is measured in free air with components mounted on a highly efficient thermally conductive test board with "direct connect" capability. See Technical Bulletin TB379.

5. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Operating conditions recommended by electrical codes unless otherwise stated. Blackbody limits apply to operating temperature range, 0°C to +85°C

Operating conditions recommended by electrical codes unless otherwise stated. Blackbody limits apply to operating temperature range, 0°C to +85°C

Note:

6. Unless otherwise specified, parameters with minimum and/or maximum limits are 100% tested at +25°C. Temperature limits determined by characterization and not production tested

function pin

wear (pin 1), (pin 16 QFN) on gate drive output. Connect to a high-voltage gate N-channel MOSFET. Floating Boot Supply Pin for Gate Driver on Sheath (Pin 2), (Pin 2 QFN). on this pin and the phase pin. The bootstrap capacitor turns on the upper MOSFET. A resistor in series with the boat requires a capacitor to reduce losses in some applications

on the start pin. Used as a guide to select proper capacitor and resistor values. PWM (Pin 3), (Pin 3 QFN) The PWM signal is the control input for the driver. Pulse Width Modulation During operation, the signal can enter three different states, see "Tri-state PWM Input" on page 8 for more details. Connect this pin to the PWM output of the controller. Ground (Pin 4), (Pin 4 QFN) Bias and Ground Reference. All signals refer to this node. PGND (5-pin QFN package only) This pin is the power ground return for the lower gate driver. LGATE (Pin 5), (Pin 7 QFN) Lower Gate Drive Output. Connect to low-voltage gate power N-channel MOSFET. VCC (Pin 6), (Pin 9 QFN) Connect this pin to the +12V bias supply. High quality bypass capacitors from this pin to ground. LVCC (pin 10 QFN package only) reduces the gate driver supply voltage.

PVCC (Pin 7), (Pin 11 QFN) For the HIP6601B and HIP6604B, this pin provides the upper gate drive bias. Connect this pin from +12V to +5V. For the HIP6603B, this pin provides both upper and lower gate drive bias. Connect this pin to +12V or +5V. Phase (Pin 8), (Pin 14 QFN) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. Phase voltage is monitored for adaptive penetration protection. This pin also provides a return path for the upper gate driver.

illustrate

Operation Designed for versatility and speed, the HIP6601B, HIP6603B, and HIP6604B dual MOSFET drivers control high-side and externally supplied low-side N-channel FET PWM signals. The upper and lower gates remain low until the driver has initialized. Once the VCC voltage exceeds the VCC rise threshold (see "Electrical Specifications" on page 5) a pulse width modulated signal controls the gate transition. The rising edge turns on the PWM to turn off the lower MOSFET. After a short propagation delay [tPDLLGATE], the down gate begins to drop. The time [tFLGATE] is provided in the "Electrical Specification" for a typical drop. The adaptive shoot-through circuit monitors the LGATE voltage and determines how quickly the upper gate delay time [tPDHUGATE] drops below 2.2V based on the LGATE voltage. This prevents the upper and lower mosfets from not conducting or penetrating at the same time. Once the delay period is over, the upper gate driver starts to ramp up [tRUGATE] and the upper MOSFET turns on.

A falling transition on the PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. Short hair starts to drop [wear] at the upper gate. Likewise, adaptive through-the-wall circuits determine lower gate delay times, tPDHLGATE. The phase voltage is monitored. When the phase falls below 0.5V, the gate is allowed to rise under the lower gate and then rise [tRLGATE], turning on the lower gate MOSFET. A unique feature of the three-state PWM input HIP660X driver is to close the window to the PWM input. If the PWM signal enters and remains within a collective off-window delay time, the output driver is disabled and the MOSFET gate is pulled low and held low. Shutdown state when the PWM signal is moved to the close window. Otherwise, the thresholds outlined in the PWM rise and fall electrical specifications determine when the upper and lower gates are enabled. Adaptive penetration protection Both drivers use adaptive penetration protection to prevent the upper and lower mosfet conduction from short-circuiting the input power supply at the same time. This is done by ensuring that the falling gate turns off one MOSFET before the other is allowed to rise. When turning off the lower MOSFET, the LGATE voltage is monitored until the 2.2V threshold is reached, at which point the UGATE is released. An adaptive shoot-through circuit monitors the phase voltages during the grinding off period. Once the primary phase has dropped below the 0.5V threshold, LGATE is allowed to rise. Rise time at lower gate. If the phase does not drop to 0.5V within 250ns, LGATE is taken high to keep the bootstrap capacitor charged. If the phase voltage exceeds 0.5V during this period, the threshold remains high for more than 2µs, and LGATE goes low. The upper and lower gates are held in the lower position until the pulse width modulated signal.

The Power-On Reset (POR) function monitors the rising VCC voltage during initial startup and the gate driver remains low until the typical VCC rising threshold of 9.95 volts is reached. Once the VCC threshold rises above this value, the PWM input signal controls the gate drive. If VCC falls below the typical VCC falling threshold of 7.6V during operation, then hold both gate drivers low again. This condition continues until the VCC voltage exceeds the VCC rising threshold. Internal Boot Device The HIP6601B, HIP6603B, and HIP6604B drivers all have internal boot devices. Just add external capacitors through the boot and phase pins to complete the bootstrap circuit. The bootstrap capacitor must have a maximum voltage. The rating is higher than VCC+5V. The bootstrap capacitor can be selected from the following equations: Among them, QGATE is all to charge the gate of the upper MOSFET. The VBOOT term is defined as the allowable sag of the upper drive rail. For example, suppose a HUF76139 is chosen as the upper MOSFET. The gate charge, QGATE, is 65nC according to the data for gate drive on 10V. We assume that the drive voltage drops by 200mV during the PWM period. We found that a bootstrap capacitor of at least 0.325°F was required. The next larger standard value capacitor is 0.33µF. When needed from +12V or higher, the PVCC is connected to the +12V supply, and a resistor in series with the boot capacitor is required for startup. The increased power density of these designs can result in parasitic elements due to fast switching of large currents in a given circuit. Increasing the start-up resistor allows for tuning the circuit until the peak ringing at start-up is below 29V from start-up to ground and 17V from start-up to VCC. A start-up resistor value of 5 usually meets this criterion. In some applications, a well-tuned startup resistor can reduce startup pin ringing, but the phase ringing with the GND peak exceeds 17 volts. A gate resistor placed on the molar trace between the upper controller and the gate of the upper MOSFET is recommended to reduce ringing on the phase node and slow the turn-on of the upper MOSFET. A gate resistor value between 2 and 10 will typically reduce the phase to ground peaks below 17 volts. Gate Drive Voltage Versatility The HIP6601B and HIP6603B provide the user with total flexibility to select the gate drive voltage. The HIP6601B lower gate driver is fixed at VCC[+12V], but the upper gate driver rail ranges from 12V to 5V depending on the voltage applied to the PVCC. HIP6603B tie together to lower the drive rail. Simply going from 5V to 12V on PVCC will set the two drive rail voltages.

Power consumption

Package power dissipation is primarily a Mossfett of the selected switching frequency and total gate charge. Calculating power consumption ideal applications in drivers is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended ±125°C. The maximum operating junction temperature of the SO8 package allows the IC power dissipation to be approximately 800 mW. When designing the driver as an application, the following calculations are recommended to ensure that the frequency of the chosen mosfet is safe to operate at the desired location. The power dissipated by the driver is approximated as:

where fsw is the switching frequency of the PWM signal. Deja Vu VL stands for the upper and lower gate rail voltages. Curve QL is determined by MOSFET selection and any additions to the gate pegs. IDDQ VCC products are quiescent power supplies typically 30 mW. Power consumption is approximately the result of power. Enter and exit through the upper and lower gates. But the internal boot also dissipates energy on the chip during refresh cycles. Expressing this force above the MOSFET total gate charge is explained below. When the lower MOSFET or its body diode conducts and pulls the phase node towards ground. When the bootstrap device boots, the current path is to bring the bootstrap capacitor back to its fresh shape. Since the upper gate of a MOSFET is driven, the charge from the bootstrap capacitor is equivalent to the total gate charge of the MOSFET. Therefore, the required refresh power bootstrap capacitor is equivalent to charging the gate capacitance of the MOSFET 2020-01-07.

where QLOSS is the total charge capacitor removed from the boot and supplied to the upper gate load. The 1.05 factor is from after the description. Characterization of the basic circuit with different loading profiles and frequency drivers is provided. CU and CL are upper and lower gate load capacitors. Add decoupling capacitors [0.15µF] to the PVCC and VCC pins. The bootstrap capacitor value is 0.01µF. In Figure 1, the CU and CL values are the same, and the same frequency varies from 50 kHz to 2 MHz. PVCC and VCC are in parallel to provide +12V power supply. The curve does cut off above 800 MW, but continuous operation above this point is not recommended. Figure 2 shows the losses in the driver at both gates and on each gate when loaded with 3nF. Note the higher gate power consumption caused by the bootstrap on the upper refresh cycle. Again, PVCC and VCC are tied together for a +12V power supply

The effect of load on power consumption is shown in Figure 3. When the gate capacitor varies from 1nF to 5nF. VCC and PVCC are connected together and the +12V power supply. Figures 4, 5, and 6 show the same results for the HIP6603B characteristics of a +5V supply on PVCC with VCC connected to a +12V supply. Since both the upper and lower gate capacitances can vary, Figure 8 shows the dissipation curve relative to the lower gate on which the gate capacitance remains constant at 3 different values of capacitance. These curves apply only to the expired HIP6601B power configuration.