6N137 , HCPL-26xx/06xx/ 4661 , HCNW137/26x1 are light-coupled gate diodes combined with GaAsP luminescence and integrated high-gain photodetectors. Enable. The input allows the detector to be strobed. The output detector IC is an open collector Schottky clamp transistor. Inner shield provides guaranteed common mode; transient immunity specification up to 15000 V/s at Vcm 100 volts. This unique design provides maximum AC and DC circuit isolation while achieving TTL compatibility. optocoupler. AC and DC operating parameters allow for problem-free system performance.

feature

15 kV/μs minimum Common Mode Rejection (CMR) for HCNW2611, HCPL-2611, HCPL-4661, VCM=1 kV, HCPL-0611, HCPL-0661 High Speed: 10 MBd typical with LSTTL/TTL compatible low input current capability : 5mA Guaranteed Over-Temp AC/DC Performance: -40°C to +85°C Available in 8-Pin Dip, SOIC-8, Wide Body Package Strobe Output (Single Channel Products Only) Safety Approved - UL Recognized - 1 Minute 3750 Vrms and 5000 Vrms per UL1577 CSA certified (5000 Vrms/1) for 1 minute min Rated for HCNW137/26X1 and Option 020 [6N137, HCPL-2601/11/30/31, HCPL-4661] Products only ) - approved IEC/EN/DIN EN 60747-5-5

VIORM=567 V peak for 06xx option 060

VIORM=630 V peak for 6N137/26xx option 060 For HCNW137/26x1, VIORM=1414 V peak

MIL-PRF-38534 sealed versions available (HCPL-56xx/66xx)

application

Isolated Line Receiver

computer peripheral interface

Microprocessor System Interface

Digital isolation for A/D, D/A conversion

switching power supply

Instrument input/output isolation

Ground loop elimination

Replace the pulse transformer

Power Transistor Isolation in Motor Drives

Isolation of high-speed logic systems

The 6N137, HCPL-26xx, HCPL-06xx, HCPL-4661, HCNW137 and HCNW26x1 are suitable for high-speed logic interfaces, input/output buffering, as line receivers in environments where traditional line receivers cannot tolerate, recommended for extremely high ground or Use in inductive noise environments.

a. Technical data is available in a separate Avago publication.

b. Using Avago application circuit, 15kV/µs can be achieved, VCM=1kV.

c. Enable is only available for single channel products, except HCPL-193x devices.

Electrical Specifications

Unless otherwise specified, exceed recommended temperature (TA=-40°C to +85°C). All typical values at VCC=5 V, TA=25°C. All enable test conditions apply to single channel products only. See notes.

Note: The power lines need to be bypassed with a 0.1µF ceramic disc capacitor near each optocoupler as shown. The total lead length between the ends of the capacitor and the isolation pins should not exceed 20mm.

a. JEDEC registered the data for 6N137. JEDEC registration specifies 0°C to +70°C. Avago specifies -40°C to +85°C.

b. Each channel.

The JEDEC registration of c.6J137 specifies a maximum IOH of 250µA. Avago, with a guaranteed maximum IOH of 100µA.

d. A high logic state on the enable input does not require an external pull-up. If the VE pin is not used, connecting VE to VCC will improve CMR performance. For single channel products only.

The E.JEDEC registered 6N137 specifies a maximum ICCH of 15 mA. AVAGO guarantees a maximum ICCH of 10mA.

f. JEDEC registered 6N137 specifies a maximum ICCL of 18 mA. AVAGO guarantees a maximum ICCL of 13mA. The JEDEC registration for the 6N137 specifies a maximum IEL of 2 mA. Avago guarantees a maximum IEL of 1.6mA.

Switch Specifications (AC)

Above recommended temperature (TA=-40°C to +85°C), VCC=5V, IF=7.5mA, unless otherwise specified. All typical values at TA=25°C, VCC=5 V.

a. Ratings apply to all devices unless otherwise stated in the box.

b. JEDEC registered the data of 6N137.

c. Each channel.

d. Measure the tPLH propagation delay from the 3.75 mA point on the falling edge of the input pulse to the 1.5 volt point on the rising edge of the output pulse.

e. Measure the tPHL propagation delay from the 3.75 mA point on the rising edge of the input pulse to the 1.5 volt point on the falling edge of the output pulse.

f. A high logic state on the enable input does not require an external pull-up. If the VE pin is not used, connecting VE to VCC will improve CMR performance. For single channel products only.

g. See the application section titled "Propagation Delay, Pulse Width Distortion, and Propagation Delay Distortion" for details.

h. tPSK equals the worst-case difference in tPHL and/or tPLH that occurs between units at any given temperature and specified test conditions.

i. The tELH enable propagation delay is from the 1.5 V point on the falling edge of the enable input pulse to the output pulse.

j. The tEHL enable propagation delay is measured from the 1.5v point on the rising edge of the enable input pulse to the output pulse.

Propagation Delay, Pulse Width Distortion and Propagation Delay Deviation Propagation delay describes how quickly a logic signal propagates through a system. This low-to-high propagation delay (tPLH) is the amount of time it takes for the input signal to propagate to the output for the output to go from low to high. Likewise the propagation delay from high to low (tPHL) is the amount of time it takes for the input signal to propagate to the output to make the output go from high to low (see figure). Pulse Width Distortion (PWD) results for different tPLH and tPHL values. PWD is defined as tPLH and TPHL often determine the maximum data rate capability of the transmission system. PWD can be expressed as a percentage by dividing the PWD (unit: ns) by the minimum pulse width (unit: ns) being transmitted. Generally, a PWD of about the minimum pulse width is acceptable; the exact number depends on the specific application (RS232, RS422, Tl, etc.).

Propagation delay skew (tPSK) is considered a problem for signals on parallel data lines in parallel data applications. If parallel data is sent through a set of optocouplers, the propagation delay will cause the data to arrive at the optocouplers output at different times. If this differential propagation delay is large enough, it will determine the maximum rate at which parallel data can be sent through the optocoupler. Propagation delay deviation is defined as the minimum and maximum propagation delay, TPLH or tPHL, for any set of operating optocouplers under the same conditions (ie, the same drive current, supply voltage, output load, and operating temperature). As shown, if the inputs of a set of optocouplers are turned on or off at the same time, tPSK is the difference between the shortest propagation delay (tPLH), or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, TPSK can determine maximum parallelism. data transfer rate. The picture is with a clock and a data line sent through an optocoupler. The figure shows the input and output data and clock signal optocouplers. For maximum data transfer rates, both edges of the clock signal are used to clock the data; if only one edge is used, the clock signal will need to be twice as fast.

Propagation delay deviation indicates that the edge may be sent through the optocoupler. The graph shows the uncertainty in both the data and the clock line. It is important that these two aspects of uncertainty do not overlap, otherwise the clock signal may arrive before all data outputs have finished, or some data outputs may start changing before the clock signal arrives. From these considerations, the absolute minimum pulse width that can be sent through an optocoupler in parallel applications is twice tPSK. A prudent design should use a slightly longer pulse width to ensure that the rest of the circuit does not cause a malfunction. Optocouplers specified by tPSK offer guaranteed propagation delay specifications, pulse width distortion and propagation delay over recommended values for temperature, input current and power supply range.