illustrate

The HCPL-3120 contains a gaasp led while the HCPL- J312 and HCNW3120 contain an Algaas LED. The LEDs are optically coupled to an integrated circuit of a power output stage. These optocouplers are ideal for driving power IGBTS and mosfets for motor control inverter applications. The high operating voltage range of the tea output stage provides the required voltage for the gate controller drive voltage. The current provided by these optocouplers makes them ideal for directly driving ILP 1200 V//100 A. For Igbts with higher ratings, the HCPL-3120 series is available Discrete power stage IGBT GateHCNW3120 for driver driver driver is high isolation Viorm voltage=1414vpeak in the IEC//en//din en 60747-5-5.HCPL-J312 has VIORM isolation voltage=1230VPEAKand the viorm=630vpeak is also available with the HCPL-3120 (Option 060) margin recommendations for normal static protection handling and assembly to prevent damage and/or possible degradation by ESD

feature

2.5 Maximum peak output current

2.0 A minimum peak output current

25 kV/µs VCM Min Common Mode Rejection (CMR) = 1 500 Volts 0.5 V Max Low Level Output Voltage (VOL) Eliminates Negative Gate Drive Required

CC=5mA maximum supply current

Undervoltage Lockout Protection (UVLO) with Hysteresis

Wide operating voltage control range: 15 to 30 volts

500 ns maximum switching speed

Industrial temperature range: –40°C to 100°C

Safety Approved: UL Recognized for HCPL-3120/J312 at 3750 Vrms for 1 minute For HCNW3120, 5000 Vrms for 1 minute CSA Approved IEC/EN/DIN EN 60747-5-5: VIORM=630 V peak for HCPL-3120 (Option 060) VIORM = 1230 V peak for HCPL-J312 VIORM = 1414 V peak for HCNW3120

application

IGBT/MOSFET gate drive

AC/BLDC Motor Drive

Industrial inverter

switching power supply

A 0.1µF bypass capacitor must be connected between pin 5 and pin 8

notes:

Time from 25°C to max temp = max 8 minutes. Maximum temperature=200°C, Minimum temperature=150°C

NOTE: Non-halide fluxes should be used. Recommended peak temperature for wide body 400 mils package is 245°C

All Avago technical data sheets report leakage and clearance inherent in the optocoupler assembly itself. These dimensions are the starting point that equipment designers need when determining circuit insulation requirements. However, once installed on a printed circuit board, the minimum creepage and clearance requirements specified by individual equipment standards must be met. For leakage current, the solder fillets of the input and output leads must be considered along the surface of the printed circuit board. There are recommended techniques such as grooves and ribs that can be used on printed circuit boards to achieve the required creepage and clearance. Creepage and clearance distances will also vary based on factors such as pollution level and insulation class.

IEC/EN/DIN EN 60747-5-5 Insulation related characteristics

These optocouplers are "only within safe limits data" for safe electrical isolation. Maintenance of safety data shall be guaranteed by protective circuits. Surface mount classification is Class 1 With CECC 00802.

Absolute Maximum Ratings

a. Linearly reduce the free air temperature above 70°C at a rate of 0.3 mA/°C.

b.0a. See the Applications section for more details on limiting IOH peaks.

c. Linearly reduce the free air temperature above 70°C at a rate of 4.8 mW/°C.

d. The maximum LED junction temperature should not exceed 125°C at a free air temperature above 70°C, with a linear drop at a rate of 5.4 mW/c.

Electrical Specifications (DC)

exceeds recommended operating conditions (TA=-40 to 100°C, for HCPL-3120, HCPL-J312 IF(ON) = 7 to 16 mA, for HCNW3120 IF(ON) = 10 to 16 mA, VF(OFF) ) = -3.6 to 0.8 volts, VCC = 15 to 30 volts, VEE = ground) unless otherwise specified.

a. All typical values at TA=25°C and VCC–VEE=30 V unless otherwise noted.

b. 0 A VO = (VCC – 15 V) 17 c Maximum pulse width = 10 μs, maximum duty cycle = 0.2%.

c.0a. See the Applications section for more details on limiting IOH peaks.

d. In this test, VOH is measured with DC load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero amps.

e. Maximum pulse width = 1 ms, maximum duty cycle = 20%.

application information

Elimination of negative IGBT gate drive (discussion applies to HCPL-3120, HCPL-J312 and HCNW3120) To keep the IGBT stable, the HCPL-3120 has a very low maximum VoL specification of 0.5V. The HCPL-3120 achieves this very low. VOL by using a DMOS transistor with 1 (typ) resistor in its pull-down circuit. When the HCPL-3120 is in the low state, the IGBT gate is shorted to the emitter via Rg+1. Minimizing Rg and lead inductance from the HCPL-3120 to the IGBT gate emitter (possibly by mounting the HCPL-3120 on a small PC board directly above the IGBT) can eliminate the need for a negative IGBT gate drive in many applications such as shown in Figure 25. The design of this PC board should take care to avoid IGBT collector or emitter tracking close to the HCPL-3120 input, as this may cause unwanted transients to couple into the HCPL-3120 and degrade performance. (If the IGBT drain must be routed near the input of the HCPL-3120, the LED should be reverse biased when off to prevent transient signals coupled from the IGBT drain from turning on the HCPL-3120.)

The gate resistance (Rg) is chosen to minimize IGBT switching losses. (Discussion applies to HCPL-3120, HCPL-J312 and HCNW3120)

Step 1: Calculate the Rg minimum according to the IOL peak specification. The IGBT and Rg in the picture can be analyzed as a simple RC circuit with voltage supplied by the HCPL-3120.

Rg≥(VCC–VEE–VOL)/IOLPEAK

=(VCC–V–2V)/Ipeak

=(15V+5V–2V)/2.5A

=7.2≈8 The volume value of 2V in the above formula is the conservative VOL value when the peak current is 2.5A (see figure). At lower Rg values the HCPL-3120 provides less than ideal voltage steps. This results in lower peak currents (more headroom) than predicted by this analysis. When negative gate drive is not used in the previous equation V is equal to zero volts.

Step 2: Check the power consumption of the HCPL-3120 and increase if necessary. HCPL-3120 Total Power Consumption (PT) is equal to the sum of Emitter Power (PE) and Output

Power (PO):

PT=PE+PO-PE=IF×VF×duty ratio

PO=PO (bias) + PO (switch)

=ICC×(VCC–VEE)+ESW(RG,QG)×f For the circuit in the figure, IF (worst case)=16mA, Rg=8, maximum duty cycle=80%, Qg=500 nC, f = 20 kHz and TA max = 85°C: PE = 16mA x 1.8V x 0.8 = 23mw PO = 4.25ma x 20v + 5.2µJ x 20khz = 85mw + 104mw = 189mw >178 MW (max) (at 85°C) = 250 MW -15°C * 4.8 MW/°C) The 4.25ma value of ICC in the above formula is obtained by reducing the ICC max by 5mA (occurs at –40 °C) to ICC maximum at 85°C (see figure). Since PO in this case is greater than PO(MAX), Rg must be increased to reduce the power consumption of the HCPL-3120. PO(Switching Max) = PO(Maximum) – PO(Deviation) = 178 MW - 85 MW = 93 MW ESW(MAX) = (PO(SWITCHINGMAX))/f

=93mW/20kHz=4.65μJ for Qg=500 nC, from the figure, the value of ESW=4.65μJ gives Rg=10.3.

Thermal Model (discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) The steady-state thermal model of the HCPL-3120 is shown in the figure. The thermal resistance values given in the model can be used to calculate the given operating conditions. As the model shows, all heat-generated flows pass through the CA corresponding to the temperature TC that causes this condition. The value of θCA depends on the board design conditions and is therefore up to the designer. The value for θCA = 83°C/W comes from thermal measurements using a 2.5 x 2.5 inch PC board with small traces (no ground plane), a single HCPL-3120 soldered to the center of the board and still air. The absolute maximum power dissipation derating specification assumes a theta temperature of 83°C/W. According to the thermal pattern in the diagram, the LED and detector IC

The junction temperature can be expressed as: TJE=PE≈(θLC | |(θLD+θDC)+θCA)+PD×((θLC×θDC)/(θLC+θDC+θLD))+θCA)+TA TJD=PE(θLC ×θDC)/(θLC+θDC+θLD))+θCA+PD×(θDC||(θLD+θLC+θCA)+TA

Inserting the values of θLC and θDC shown in the figure can be obtained: TJE=PE×(256°C/W+θCA)+PD•(57°C/W+θCA)+TA TJD=PE×(57°C/W +θCA)+PD×(111°C/W+θCA)+TA For example, given PE=45 mW, PO=250 mW, TA=70°C, and θCA=83°C/W: TJE=PE× 339°C/W+PD×140°C/W+TA=45MW×339°C/W+250MW×140°C/W+70°C=120°CTJD=PE×140°C/W +PD×194°C/W+TA=45mW×140°C/W+250mW×194°C/W+70°C=125°CTJE and TJD should be limited to 125°C specific according to the board Layout and Component Placement (θCA) for applications.

LED driver circuit considerations for ultra-high CMR performance (discussion applies to HCPL-3120, HCPL-J312 and HCNW3120) In the absence of detector shielding, the main cause of optocoupler CMR failure is the capacitively coupled optocoupler at the input, passing through the package , to the detector IC, as shown. The HCPL-3120 diverts the capacitively coupled current from the sensitive integrated circuit by using a detector integrated circuit with an optically transparent Faraday shield. However, this shielding will not remove the capacitive coupling between the LED and optocoupler pins 5–8, as shown in the diagram. This capacitive coupling causes perturbation of the LED current during common-mode transients and is the main reason for the failure of the shielded optocoupler CMR. The main design goal of a high CMR LED driver circuit is to keep the LED in the correct state (on or off) during common mode transients. For example, the recommended application circuit (figure) can achieve 25kV/μs CMR while minimizing component complexity. In the next two parts, we'll discuss techniques for keeping LEDs in the correct state.

CMR with LEDs (CMRH) High CMR LED driver circuits must be in common mode transients. This is done by overdriving the LED current beyond the input threshold, so it won't be pulled below the threshold momentarily. A minimum LED current of 10 mA provides sufficient headroom over the maximum. 5 mA FLH to achieve 25 kV/µs CMR. CMR (CMRL) High CMR when LED is off Also flows through the RSAT and VSAT of the logic gate. As long as the low voltage developed on the logic gate is less than VF (off), the LED will remain off and no common mode will fail. As shown, the open collector drive circuit cannot operate at + Keep the LED off during dVcm/dt transients because the current flowing through CLEDN must be supplied by the LED and is not recommended for applications requiring ultra-high CMRL performance. The diagram is an alternative drive circuit same as the recommended application circuit (diagram), with or without shunting the LED Achieving ultra-high CMR performance is off.

Undervoltage Lockout Feature (discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) The HCPL-3120 includes an Undervoltage Lockout (UVLO) feature to protect against IGBT fault conditions that cause the HCPL-3120 supply voltage (equivalent to a fully charged IGBT gate voltage) drops below the level necessary to keep the IGBT in a low resistance state. Supply voltage below HCPL-3120 VUVLO – threshold (9.5

Specification

(Discussion applies to the HCPL-3120, HCPL-J312, and HCNW3120) The HCPL-3120 includes a Propagation Delay Difference (PDD) specification designed to help designers minimize "dead time" in their inverter power supply designs. Dead time is the period of time during which the high-side and low-side power transistors (Q2 in the Q1 diagram) are turned off. Any overlapping conduction in Q1 and Q2 will result in high current flow through the power unit between the high and low voltage motor rails

To minimize dead time in a given design, turning on LED2 should be delayed (relative to turning off LED1) so that in the worst case, transistor Q1 just turns off when transistor Q2 turns on, as shown. The amount of delay required to achieve this condition is equal to the maximum specification for the difference in propagation delay, PDDMAX, specified for an operating temperature range of -40°C to 100°C. Delaying the LED signal differential with the maximum propagation delay ensures that the minimum dead time is zero, but does not tell the designer what the maximum dead time is. The maximum dead time corresponds to the difference. The relationship between the maximum and minimum time lag for different specifications is shown in the figure. The maximum dead time of the HCPL-3120 is 700ns (=350ns – (–350ns)) over the operating temperature range of -40°C to 100°C. Note that the dead time is taken for the calculation of the PDD and at the same temperature and test conditions because the optocouplers under consideration are usually IGBTs that are mounted close to each other and are switching in the same position.