Summary

16-bit fixed-point digital signal processor; on-chip memory; enhanced Harvard triple-bus architecture; performance: instruction bus and dual data bus; independent computational units: ALU, multiplier/accumulator, and shifter; single-cycle instruction execution and multiple Function.

illustrate

On-chip Program Memory & Data Memory RAM; Integrated I/O Peripherals: Serial Port, Timer, Host Interface Port ( ADSP-2111 only).

feature

25 MIPS, 40 ns maximum instruction rate; separate on-chip buses for program and data memory; program memory stores both instructions and data (triple bus performance); dual data address generator with modulo sum; bit-reversed addressing; zero Efficient program sequencing for overhead; loops: single-loop loop setup; automatic bootstrap of on-chip program memory; byte-range external memory (such as EPROM); double-buffered serial port with compression hardware, automatic data buffering and multi-channel operation; ADSP -2111 host interface port provides simple interface to 68000 , 80C51 , ADSP-21xx, etc. Autoboot of ADSP-2111 program memory; via host interface port; three edge or level sensitive interrupts; low power idle instructions; PGA, PLCC, PQFP and TQFP packages; MIL-STD-883B versions available.

General Instructions

The ADSP-2100 series processors are microcontrollers optimized for digital signal processing (DSP) and other high-speed digital processing applications. ADSP-21xx processors are all built on a common core. Each processor combines a core DSP-architecture computational unit, data address generator and program sequencer with different functions such as on-chip program and data memory RAM, programmable timers, one or two serial ports, and in Host interface port on the ADSP-2111.

This data sheet describes the following ADSP-2100 series processors:

ADSP-2101;

ADSP-2103: 3.3V version of ADSP-2101;

ADSP-2105: low-cost digital signal processor;

ADSP-2111: DSP with host interface;

ADSP-2115;

ADSP-2161/62/63/64: DSP for custom ROM programming.

The following ADSP-2100 series processors are not included in this data sheet:

ADSP-2100A: DSP microprocessor;

ADSP-2165/66: ROM programming ADSP-216x processors with power off and larger chip memory ( 12K program memory ROM, 1K program memory RAM, 4K data memory RAM);

ADSP-21msp5x: Mixed-signal DSP processor with integrated on-chip A/D and D/A plus power down;

ADSP-2171: Speed and feature-enhanced ADSP-2100 family of processors with host interface ports, shutdown and instruction set extensions for bit manipulation, multiplication, bias rounding, and global interrupt masking;

ADSP-2181: The ADSP-21xx processor features the ADSP-2171 plus 80K bytes of on-chip RAM configured as 16K words of program memory and 16K words of data memory.

See each processor's individual data sheet for more information.

The highest-performance ADSP-21xx processors are fabricated in a high-speed, sub-micron, double-layer metal CMOS process, operating at 25mhz and operating at 40ns instruction cycle time. Each instruction can be executed in one cycle. Fabrication in CMOS results in low power consumption.

The ADSP-2100 family's flexible architecture and comprehensive instruction set support a high degree of parallelism. In one cycle, the ADSP-21xx can do all of the following:

(1), generate the next program address

(2), get the next instruction

(3), perform one or two data movements

(4), update one or two data address pointers

(5), perform calculation

(6) Receive and transmit data through one or two serial ports

(7) Receive and/or transmit data through the host interface port (ADSP-2111 only)

The ADSP-2101, ADSP-2105, and ADSP-2115 include the family's basic processor set. Each of these three devices contains program and data memory RAM, an interval timer and one or two serial ports. The ADSP-2103 is a 3.3-volt power supply version of the ADSP-2101; it is identical to the ADSP-2101 in all other features. Table 1 shows the characteristics of each ADSP-21xx processor.

The ADSP-2111 adds a 16-bit Host Interface Port (HIP) to the basic set of ADSP-21xx integrated functions. The host port provides a simple interface to a host microprocessor or microcontroller such as the 8031, 68000 or ISA bus.

The ADSP-216x family is a memory variant of the ADSP-2101 and ADSP-2103 that contains factory programmed on-chip ROM program memory. These devices provide varying amounts of on-chip memory for program and data storage. Table 2 shows the available features of the ADSP-216x family of custom ROM encoded processors.

ADSP-216x products eliminate the need for an external boot EPROM in the system and can also eliminate the need for any external program memory by installing the entire application in on-chip ROM. Therefore, these devices provide an excellent choice for a large number of applications where board space and system cost constraints are key issues.

development tools

ADSP-21xx processors are supported by a complete set of tools for system development. The ADSP-2100 family of development software includes C and assembly language tools that allow programmers to write code for any ADSP-21xx processor. The ANSI C compiler generates ADSP-21xx assembly source code, while the runtime C library provides ANSI standard and custom DSP library routines. The ADSP21xx assembler generates object code modules that the linker assembles into executable files. The processor simulator provides an interactive instruction-level simulation with a reconfigurable, windowed user interface. The PROM splitter utility generates PROM programmer-compatible files.

The EZ-ICE® in-circuit emulator enables debugging of ADSP-21xx systems by providing a range of emulation functions such as modifying memory and register values and executing breakpoints. The EZ-LAB® demo board is a complete DSP system that executes EPROM-based programs.

The EZ Kit Lite is a very low cost evaluation/development platform that contains the hardware and software required to evaluate the ADSP-21xx architecture.

More details and ordering information are available in the ADSP-2100 Series Software and Hardware Development Tools Data Sheet (ADDS-21xx-Tools). This data sheet is available from any analog sales office or dealer.

Additional Information

This data sheet provides an overview of the capabilities of the ADSP-21xx processors. For detailed design information on the architecture and instruction set, please refer to the ADSP-2100 series user manual provided with the analog device.

Architecture Overview

Figure 1 shows a block diagram of the ADSP-21xx architecture.

The processor contains three independent computational units: ALU, multiplier/accumulator (MAC), and shifter. The calculation unit directly handles 16-bit data and has provisions to support multi-precision calculations. The ALU performs a standard set of arithmetic and logical operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations. Shifters perform logical and arithmetic shifts, normalization, denormalization, and derived exponentiation operations. The shifter can efficiently implement digital format control including multi-word floating point representations.

The internal result (R) bus connects the computational units directly so that the output of any unit can be used as the input of any unit in the next cycle.

A powerful program sequencer and two dedicated data address generators ensure efficient use of these computational units. The sequencer supports conditional jumps, subroutine calls, and single-cycle returns. Using an internal loop counter and loop stack, the ADSP-21xx executes loop code with zero overhead and does not require explicit jump instructions to maintain loops.

Two data address generators (DAGs) provide addresses for fetching dual operands from data memory and program memory simultaneously. Each DAG maintains and updates four address pointers. Whenever data is accessed using a pointer (indirect addressing), it is post-modified by the value of one of the four modifying registers. A length value can be associated with each pointer to enable automatic modulo addressing for circular buffers. Serial ports also use circular buffering to automatically transfer data to (or from) onchip memory.

Efficient data transfer is achieved through the use of five internal buses:

(1), program memory address (PMA) bus;

(2) Program memory data (PMD) bus;

(3), data memory address (DMA) bus;

(4), data storage data (DMD) bus;

(5), the result (R) bus.

Two address buses (PMA, DMA) share an external address bus, allowing memory expansion from off-chip, and EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.

Two data buses (PMD, DMD) share an external data bus.

The BMS, DMS and PMS signals indicate which memory space is using the external bus.

Program memory can store both instructions and data, allowing the ADSP-21xx to fetch two operands in one cycle, one from program memory and one from data memory. The processor can fetch an operand from on-chip program memory and fetch the next instruction in the same cycle.

The memory interface supports slow memory and memory-mapped peripherals with programmable wait state generation. External devices can request/authorize the use of signals (BR, BG) via the bus.

A bus-granted execute mode (GO mode) allows the ADSP21xx to continue operating from memory. The second execution mode requires the processor to be stopped when the bus is granted.

Each ADSP-21xx processor can respond to several different interrupts. There can be up to three external interrupts, configured as edge or level sensitive. Internal interrupts can be generated by timers, the serial port, and on the ADSP-2111, the host interface port. There is also a master reset signal.

The boot circuit provides automatic loading of on-chip program memory from byte-wide external memory. After reset, three wait states are automatically generated. For example, this allows the 60 ns ADSP-2101 to use the 200 ns EPROM as external boot memory. Multiple programs can be selected and loaded from the EPROM without additional hardware.

The data receive and transmit pins on SPORT1 (Serial Port 1) can be configured as general purpose input flags and output flags. You can use these pins to signal events to and from external devices. The ADSP-2111 has three additional flag outputs whose states are controlled by software.

A programmable interval timer can generate periodic interrupts. The 16-bit count register (TCOUNT) is decremented every n cycles, where n–1 is the scaled value stored in the 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from the 16-bit period register (TPERIOD).

serial port

The ADSP-21xx processors include two synchronous serial ports ("SPORTs") for serial and multiprocessor communications. All ADSP-21xx processors have two serial ports (SPORT0, SPORT1), but the ADSP-2105 has only SPORT1.

The serial port provides a complete synchronous serial interface with optional companding in hardware. A wide variety of framed or unframed data transmission and reception modes of operation are available. Each movement can generate an internal programmable serial clock or accept an external serial clock.

The ADSP-21xx serial ports provide the following features:

Bidirectional - Each sport has a separate, double-buffered send and receive function.

Flexible Clocking - Each sport can use an external serial clock or generate its own clock internally.

Flexible Frame - A frame with independent transmit and receive functions for the sports field; each function can operate in frameless mode, or generate a frame sync signal internally or externally; the frame sync signal can be high or reverse active, with both pulse width and timing.

Different Word Lengths - Each motion supports serial data word lengths from 3 to 16 bits.

Hardware Companding - According to CCITT Recommendation G.711, optional A-method and μ-method companding is available for each sport.

Flexible Interrupt Scheme - The receive and transmit functions can generate unique interrupts upon completion of a data word transfer.

Single-Cycle Autofill - Each motion can automatically receive or send the contents of an entire circular data buffer with only one overhead cycle per data word; generates an interrupt after the transfer of the entire buffer is complete.

Multi-channel function (SPORT0 only) - SPORT0

Provides a multi-channel interface for selectively receiving or transmitting 24-word or 32-word time-division multiplexed serial bit streams; this feature is especially useful for T1 or CEPT interfaces or network communication scenarios with multiple processors. (Note that the ADSP-2105 only includes SPORT1, not SPORT0, so multi-channel operation is not available.)

Alternate configuration - SPORT1 can be optional

Configured as two external interrupt inputs (IRQ0, IRQ1) and flag input and flag output signals (FI, FO).

Host Interface Port (ADSP-2111)

The ADSP-2111 includes a Host Interface Port (HIP), a parallel I/O port that allows easy connection to a host processor.

Through HIP, the host can access the ADSP-2111

A processor as a memory-mapped peripheral. The host interface port can be viewed as an area of dual-port memory or mailbox registers that allows communication between the ADSP-2111's computing core and the host. Host interface ports are fully asynchronous. When the ADSP-2111 is running at full speed, the main processor can write data to the HIP.

Three pins configure the HIP for different types of host processors. The HSIZE pin configures the HIP for 8-bit or 16-bit communication with the host processor. HMD0 configures the bus strobe, selects a separate read and write strobe or a single read/write strobe and host data strobe. HMD1 selects separate address (3-bit) and data (16-bit) buses, or multiple 16-bit address/data buses with address latch enable. Connecting these pins to the appropriate values configures the ADSP2111 for a straight line interface to a variety of industry standard microprocessors and microcomputers.

The HIP contains six data registers (HDR5-0) and two status registers (HSR7-6) with an associated HMASK register for masking interrupts from each HIP data register. The HIP data registers are mapped into the internal data memory of the ADSP-2111. Two status registers provide status information to the ADSP-2111 and the host processor. The HSR7 contains a software reset bit that can be set by the ADSP-2111 and the host.

HIP transfers can be managed using interrupts or polling. HIP generates an interrupt whenever the HDR register receives data written from the host processor. It also generates an interrupt when the host processor successfully reads any HDR. The read/write status of the hdr is also stored in the HSR register.

The HMASK register bits can be used to mask read or write interrupts from a single HDR register. Bits in the IMASK register enable and disable all HIP read interrupts or all HIP write interrupts. So, for example, a write to HDR4 will only cause an interrupt if the HDR4 write bit in HMASK and the HIP write interrupt enable bit in IMASK are both set.

The HIP provides a second method of booting the ADSP-2111, where the host processor loads the instructions into the HIP. The ADSP-2111 automatically transfers data (in this case opcodes) to internal program memory. The BMODE pin determines whether the ADSP-2111 boots from the host processor via the HIP or from an external EPROM via the data bus.

interrupt

The ADSP-21xx's interrupt controller allows the processor to respond to interrupts with minimal overhead. Up to three external interrupt input pins IRQ0, IRQ1 and IRQ2 are provided. IRQ2 is always available as a dedicated pin; IRQ1 and IRQ0 can be alternately configured as part of Serial Port 1. The ADSP-21xx also supports internal interrupts for timers, serial ports, and host interface ports (on the ADSP-2111). Interrupts are prioritized internally and are individually maskable (except for resets that are not maskable). This IRQx input pin is programmable for horizontal or edge sensitivity. The interrupt priorities for each ADSP-21xx processor are shown in Table III.

The ADSP-21xx uses a vectored interrupt scheme: when an interrupt is acknowledged, the processor transfers program control to the interrupt vector address corresponding to the received interrupt. Interrupts can be selectively nested so that higher priority interrupts can preempt the currently executing interrupt service routine. Each interrupt vector location is four instructions long, so simple service routines can be encoded entirely in this space. Longer service routines require additional jump or call instructions.

A single interrupt request is logically ANDed with the bits in the IMASK register; the highest priority unmasked interrupt is then selected.

The interrupt control register, ICNTL, allows setting external interrupts to be edge-sensitive or level-sensitive. Depending on bit 4 in ICNTL, interrupt service routines can be nested (higher priority interrupts take precedence) or sequential (only one interrupt service is active at a time).

The Interrupt Force and Clear Register IFC is a write-only register that contains the force and clear bits for each interrupt (except for level-sensitive interrupts and ADSP-2111 HIP interrupts, which cannot be forced or cleared in software).

When responding to an interrupt, the ASTAT, MSTAT and IMASK status registers are pushed onto the status stack and the PC counter is loaded with the appropriate vector address. The state stack is seven levels deep (nine levels on the ADSP-2111), allowing interrupt nesting. When the interrupt instruction returns, the stack is automatically popped.

Pin Definition

Table 4 on the next page shows the pin assignments for the ADSP21xx processors. Any unused inputs must be tied to VDD.

system interface

Figure 3 shows a typical system for the ADSP-2101, ADSP-2115, or ADSP-2103, with two serial I/O devices, a boot EPROM, and optional external program and data memory. ADSP-2101 and ADSP-2103 can address a total of 15K words of data memory and 16K words of program memory. ADSP-2115 can address a total of 14.5K words of data memory and 15K words of program memory.

Figure 4 shows the system diagram of the ADSP-2105, including a serial I/O device, a boot EPROM, and optional external program and data memory. The ADSP-2105 can address a total of 14.5K words of data memory and 15K words of program memory.

Figure 5 shows a system diagram of the ADSP-2111, which includes two serial I/O devices, a host processor, a boot EPROM, and optional external program and data memory. A total of 15K words of data memory and 16K words of program memory are addressable.

Programmable wait state generation allows the processor to easily interface to slow external memory.

The ADSP-2101, ADSP-2103, ADSP-2115, and ADSP-2111 processors also provide one external interrupt (IRQ2) and two serial port (SPORT0, SPORT1) or three external port interrupts (IRQ2, IRQ1, IRQ0) and One serial port (SPORT0).

The ADSP-2105 provides one external interrupt (IRQ2) and one serial port (SPORT1) or three external interrupts (IRQ2, IRQ1, IRQ0) without a serial port.

clock signal

The CLKIN input of the ADSP-21xx processors can be driven by a crystal or TTL compatible external clock signal. During operation, the CLKIN input cannot be stopped or changed in frequency, nor can it operate below the specified low frequency limit.

If an external clock is used, it should be a TTL compatible signal running at the command rate. The signal should be connected to the CLKIN input of the processor; in this case the XTAL input must be left unconnected.

Since the ADSP-21xx processors include an on-chip oscillator circuit, an external crystal can also be used. The crystal should be connected through the CLKIN and XTAL pins, with the two capacitors connected as shown in Figure 2. A parallel resonant, fundamental frequency, microprocessor grade crystal should be used.

The clock output signal (CLKOUT) is generated by the processor and is synchronized with the internal cycle of the processor.

reset

The reset signal initiates a full reset of the ADSP-21xx. The reset signal must be asserted when the chip is powered up to ensure proper initialization. If the reset signal is applied during initial power-up, it must be held long enough for the processor's internal clock to stabilize. If a reset is initiated at any time after power-up and the input clock frequency does not change, the processor's internal clock continues and this stabilization time is not required.

The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and the total time required for the internal Phase Locked Loop (PLL) to lock to a specific crystal frequency. At least 2000 tCK cycles will ensure that the PLL is locked (however, this does not include the crystal oscillator start-up time). During this power-up sequence, the reset signal should be held low. On any subsequent resets, the reset signal must meet the minimum pulse width specification tRSP. To generate the reset signal, use an RC circuit with an external Schmitt trigger or a commercial reset IC. (Don't just use RC circuits.)

The reset input resets all internal stack pointers to an empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, the boot load sequence is executed (provided there are no pending bus requests and the chip is configured to boot with MMAP=0). The first instruction is then fetched from internal program memory location 0x0000.

program memory interface

The on-chip program memory address bus (PMA) and the on-chip program memory data bus (PMD) are multiplexed with the on-chip data memory bus (DMA, DMD) to form a single external data bus and a single external address bus. The external data bus is bidirectional, 24 bits wide, allowing instructions to be fetched from external program memory. Program memory can contain code and data.

The external address bus is 14 bits wide. For the ADSP-2101, ADSP-2103, and ADSP-2111, these lines can directly address 16K words, 2K of which are on-chip. For the ADSP-2105 and ADSP-2115, the address lines can directly address up to 15K words, of which 1K is on-chip.

The data line is bidirectional. The Program Memory Select (PMS) signal indicates access to program memory and can be used as a chip select signal. The write (WR) signal indicates a write operation and acts as a write strobe. The read (RD) signal indicates a read operation and serves as a read strobe or output enable signal.

ADSP-21xx processors use PX registers to write data from 16-bit registers to 24-bit program memory to provide the lower 8 bits. When the processor reads 16 bits of data from the 24-bit program memory into the 16-bit data register, the lower 8 bits are placed into the PX register.

The program memory interface can generate 0 to 7 wait states for external memory devices; the default is 7 wait states reset.

program memory map

Program memory can be mapped in two ways, depending on the state of the MMAP pins. Figure 6 shows the two program memory maps for the ADSP-2101, ADSP-2103, and ADSP-2111. Figure 8 shows the program memory map for the ADSP-2105 and ADSP-2115. Figures 7 and 9 show the program memory map for the ADSP-2161/62 and ADSP-2163/64 respectively.

ADSP-2101/ADSP-2103/ADSP-2111

When MMAP=0, the on-chip program memory RAM occupies 2K words starting at address 0x0000. Off-chip program memory uses the remaining 14K words starting at address 0x0800. In this configuration, when MMAP=0, the bootload sequence (described below in "Boot Memory Interfaces - Side") starts automatically when reset is released.

When MMAP=1, the 14K words of off-chip program memory start at address 0x0000, and the on-chip program memory RAM is located in the upper 2K words, starting at address 0x3800. In this configuration, program memory does not start, although it can be written to and read from under program control.

ADSP-2105/ADSP-2115

When MMAP=0, the on-chip program memory RAM occupies 1K words starting at address 0x0000. Off-chip program memory uses the remaining 14K words starting at address 0x0800. In this configuration, when MMAP=0, the bootload sequence (described below in "Boot Memory Interfaces - Side") starts automatically when reset is released.

When MMAP=1, 14K words of off-chip program memory start at address 0x0000, and on-chip program memory RAM is located in 1K words between addresses 0x3800-0x3BFF. In this configuration, program memory does not start, although it can be written to and read from under program control.

data storage interface

The data memory address bus (DMA) is 14 bits wide. The bidirectional external data bus is 24 bits wide, with the upper 16 bits used for data memory data (DMD) transfers.

The Data Memory Select (DMS) signal indicates access memory for data and can be used as a chip select signal. The write (WR) signal indicates a write operation and can be used as a write strobe. The read (RD) signal indicates a read operation and can be used as a read strobe or output enable signal.

ADSP-21xx processors support memory-mapped I/O, and peripheral memory is mapped into the data memory address space and accessed by the processor in the same manner as data memory.

data store map

ADSP-2101/ADSP-2103/ADSP-2111

For the ADSP-2101, ADSP-2103, and ADSP-2111, the on-chip data memory RAM is located in 1K words starting at address 0x3800, as shown in Figure 10. Data memory locations at the end of data memory from 0x3C00 to 0x3FFF are reserved. The system's control and status registers, timers, wait state configuration, and serial port operations are located in this area of memory.

ADSP-2105/ADSP-2115

For the ADSP-2105 and ADSP-2115, the on-chip data memory RAM resides in 512 words starting at address 0x3800, as shown in Figure 10. The data memory location at 0x3A00 is reserved at the end of data memory at 0x3FFF. The system's control and status registers, timers, wait state configuration, and serial port operations are located in this area of memory.

all processors

The remaining 14K of data memory is located off-chip. This external data memory is divided into five regions, each associated with its own wait state generator. This allows slower peripherals to be mapped into data memory that specifies wait states. By mapping peripherals to different regions you can accommodate peripherals with different wait state requirements - yes. After reset, all zones default to seven wait states.

enable memory interface

On the ADSP-2101, ADSP-2103, and ADSP-2111, the boot memory is an external 64K x 8 space divided into 8 separate 8K x 8 pages. On the ADSP-2105 and ADSP-2115, the boot memory is a 32K x 8 space divided into 8 individual 4K x 8 pages. The 8-bit bytes are automatically packed into 24-bit instruction words by each processor and loaded into the onchip program memory.

Three bits in the processor's system control register select the page loaded by the boot memory interface. Another bit in the system control register allows a forced initiation load sequence under software control. Load from Boot If MMAP=0, page 0 will be automatically booted after reset.

Starting the memory interface can generate 0 to 7 wait states; after reset it defaults to three wait states. This allows the ADSP-21xx to boot from a low cost EPROM such as the 27C256. Program memory is started one byte at a time and converted to 24-bit program memory words.

The BMS and RD signals are used to select and select the boot memory interface. Only 8 bits of data are read on pins D8-D15 via the data bus. To accommodate up to 8 pages of boot memory, the two msbs of the data bus are used in the boot memory interface as the two msbs of the boot memory address: D23, D22, and A13 provide the boot page number.

The ADSP-2100 family of assemblers and linkers allows programs and data structures that require multiple boot pages to be created during execution.

Identify the BR signal in the leader sequence. This bus is granted after loading the current byte is complete. BR can be used during boot to effect boot under the control of the host processor.

bus interface

ADSP-21xx processors can hand over control of their data and address buses to external devices. When an external device needs to control the bus, it asserts the bus request signal (BR). If the ADSP-21xx is not performing an external memory access, it responds to an active BR input in the next cycle by:

(1), three data and address buses and PMS, DMS, BMS, RD, WR output drivers,

(2), assert the bus authorization (BG) signal,

(3), stop the program execution.

However, if Go mode is set, the ADSP-21xx will not halt program execution until it encounters an instruction that requires external memory access.

If the ADSP-21xx is performing an external memory access when the external device asserts the BR signal, the ADSP-21xx will not tri-state the memory interface or assert the BG signal until cycles after the access is complete (up to 8 cycles depending on the number of wait states) . Instructions do not need to complete when the bus is granted; if an instruction requires multiple external memory accesses, the ADSP-21xx will grant the bus between the two memory accesses.

When the BR signal is released, the processor releases the BG signal, re-enables the output driver, and resumes program execution from where it left off.

The bus request function always works, including when the processor is booting, and when RESET is active. If this function is not used, the BR input should be tied high (VDD).

Low Power Idle Instructions

The IDLE instruction puts the ADSP-21xx processor in a low-power state, waiting for an interrupt. When an interrupt occurs, it will be serviced and continue execution after the instruction is idle. Normally, the next instruction will jump back to the idle instruction. This enables a low-power standby cycle.

The IDLE n instruction is a special version of IDLE that slows down the processor's internal clock signal to further reduce power consumption. The reduced clock frequency is a programmable portion of the normal clock frequency, specified by an optional divisor n given in the idle instruction. The syntax of the instruction is: free n; where n = 16, 32, 64, or 128.

Instructions keep the chip idle, running at a lower rate. When it is in this state, the processor's other internal clock signals, such as SCLK, CLKOUT, and the timer clock, are reduced by the same ratio. After receiving the enable interrupt, the processor will stay in the IDLE state for up to N CKIN cycles, where N is the divisor specified in the instruction, and then resume normal operation.

When the IDLE n instruction is used, it slows down the processor's internal clock, so its response time to incoming interrupts - the 1-cycle response time of the standard idle state is increased by n, the clock divisor. When an enable interrupt is received, the ADSP-21xx will remain idle until a maximum of N CLKIN cycles (n = 16, 32, 64, or 128) before resuming normal operation.

When using the IDLE n instruction in a system with an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor's reduced internal clock rate. Under these conditions, interrupts cannot be generated at a faster rate than servicing because of the extra time the processor needs to come out of the idle state (maximum N CKIN cycles).

ADSP-216x

You can prototype ADSP-216x systems using ADSP-2101 or ADSP-2103 RAM-based processors. When the code is fully developed and debugged, it can be submitted to an analog device for conversion into an ADSP-216xrom product.

The ADSP-2101ez-ICE emulator can be used for ADSP-216x system development. For the 3.3V ADSP-2162 and ADSP-2164, the Voltage Converter Interface Board provides 3.3V emulation.

Additional overlay memory is used for emulation of the ADSP2161/62 system. It should be noted that due to the use of off-chip overlay memory to emulate the ADSP-2161/62, you may experience a performance penalty when executing instructions and fetching program memory data from off-chip overlay memory in the same cycle. This can be overcome by locating program memory data in on-chip memory.

Ordering Process for ADSP-216xrom Processors

To order a custom ROM encoded ADSP-2161, ADSP-2162, ADSP-2163, or ADSP-2164 processor, you must:

1. Complete the following forms included in the ADSP ROM ordering package, available from your analog device sales representative: ADSP-216x ROM Specification Sheet; ROM Release Agreement; ROM NRE Agreement and Minimum Quantity Order (MQO); Pre-Production ROM Products Acceptance Agreement.

2. Return the form to the emulated device along with two copies of the memory image file (.EXE file) of the ROM code. These files must be provided on two 3.5" or 5.25" floppy disks on an IBM PC (DOS 2.01 or later).

3. Order Non-Recurring Engineering Change (NRE) emulation devices related to ROM product development.

Once this information is received, it is entered into the emulated device's ROM management system, which assigns a custom ROM model to the product. This model number will be stamped on all prototypes and production units built to these specifications.

To minimize the risk of changing code in the process, the emulated device will verify that the .EXE files on both floppy disks are identical and recalculate the checksum of the .EXE files entered into the ROM manager system. The checksum data is returned to you for inspection as a ROM memory map.

Before any product can be produced, a ROM verification form and a purchase order from the production unit need to be signed. Prototype units can be applied in minimum order quantities.

Once the prototype is built, the simulation facility will ship the prototype unit and update the delivery schedule for the production unit. Your purchase order will be invoiced for NRE fees at this time.

Each ROM mask generated has a fee and minimum order quantity. Please consult your sales representative for details. Parts must be ordered separately for specific package types, temperature ranges and speed grades.

Functional Differences of Older Devices Older ADSP-21xx processors have slightly different features. The two differences are as follows:

(1) The bus grant (BG) is asserted in the same cycle of identifying the bus request (BR) (that is, the setup and hold times meet the requirements of the BR input). The bus request input is a synchronous input, not an asynchronous input. (Revision devices in newer versions, BG asserts in cycles after BR is recognized.)

(2) Only standard idle instructions are available, no clock reduction idle n instructions.

To determine the version of a specific ADSP-21xx device, check the markings on the device. For example, version 6.0 of the ADSP-2101 will have the following markings:

The revision codes for older versions of each ADSP-21xx device are as follows:

Instruction Set

ADSP-21xx assembly language uses algebraic syntax for ease of coding and readability. Source and destination calculations and data movement within each assembly statement, eliminating hidden assembler mnemonics. Each instruction is assembled into a 24-bit word and executed in one cycle. These instructions include various teaching types as well as operational parallelism. There are five basic classes of instructions: data movement instructions, calculation instructions, multifunction instructions, program flow control instructions, and other instructions. Multifunction instructions perform one or two data movements and one calculation. The instruction set is summarized below. The ADSP-2100 Home User Manual contains information on the instruction set.

Timing Parameters (ADSP-2103/2162/2164)

Use the given precise timing information. Don't try to get arguments from other addition and subtraction operations. While addition or subtraction will yield meaningful results for individual devices, the values given in this data sheet reflect statistical variation and worst-case scenarios. So you can't meaningfully add parameters to get longer.

Timing Considerations

The toggle attribute specifies how the processor changes its signals. You have no control over the timing circuits external to the processor's design must deal with these signal characteristics. The toggle feature tells you that the processor will operate in a given situation. You can also use the toggle feature to ensure that any timing requirements for devices connected to the processor (such as memory) are satisfied.

Timing requirements apply by circuits external to the processor, such as read operations. The time requirement guarantees that the processor works properly with other devices.