There are many ways to solve the EMI problem. Modern EMI suppression methods include: using EMI suppression coatings, choosing appropriate EMI suppression parts and EMI simulation design. This article starts from the most basic PCB layout and discusses the role and design techniques of PCB layered stacking in controlling EMI emissions.
The power bus is reasonably placed near the power pins of the IC with capacitors of appropriate capacity, which can make the transition of the IC output voltage faster. However, the problem does not end there. Due to the finite frequency response nature of capacitors, this prevents them from generating the harmonic power needed to drive the IC output cleanly over the full frequency band. In addition to this, transient voltages developed on the power busbars create a voltage drop across the inductance of the decoupling path, and these transients are the main source of common-mode EMI interference. How should we solve these problems?
In the case of ICs on our boards, the power planes around the IC can be thought of as good high frequency capacitors that harvest the energy leaked by the discrete capacitors that provide high frequency energy for a clean output. In addition, the inductance of a good power supply layer should be small, so that the transient signal synthesized by the inductance is also small, thereby reducing common mode EMI.
Of course, the wiring from the power plane to the IC power pins must be as short as possible, because the rising edge of the digital signal is getting faster and faster, and it is best to connect directly to the pad where the IC power pins are located, which is discussed separately.
To control common-mode EMI, the power plane must be a reasonably well-designed pair of power planes to facilitate decoupling and have sufficiently low inductance. One might ask, how good is it? The answer to the question depends on the layering of the power supply, the materials between the layers, and the operating frequency (ie, a function of the IC's rise time). Usually, the spacing of the power layer is 6mil, and the interlayer is FR4 material, the equivalent capacitance per square inch of the power layer is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.
There are not many devices with rise times of 100 to 300ps, but according to the current rate of development of ICs, there will be a high proportion of devices with rise times in the range of 100 to 300ps. For circuits with rise times of 100 to 300ps, 3mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use layering techniques with a layer spacing of less than 1 mil and replace the FR4 dielectric material with a material with a very high dielectric constant. Now, ceramics and ceramics can meet the design requirements of 100 to 300ps rise time circuits.
Although new materials and methods may be adopted in the future, for common today 1 to 3ns rise time circuits, 3 to 6mil interlayer spacing, and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and to keep transients low enough that That said, common mode EMI can be very low. The PCB layered stackup design examples given in this article will assume a layer spacing of 3 to 6 mils.

Electromagnetic shielding

From the signal routing point of view, a good layering strategy should be to place all signal traces on one or several layers next to power or ground planes. For power, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible, which is what we call the "layering" strategy.

What stacking strategies for PCB stacking help shield and suppress EMI? The following layered stacking scheme assumes that the supply current flows on a single layer, and that a single voltage or multiple voltages are distributed on different parts of the same layer. The case of multiple power planes is discussed later.

4 layer board

There are several potential issues with the 4-layer board design. First of all, for a traditional four-layer board with a thickness of 62 mil, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large.

If cost requirements are a priority, consider the following two alternatives to traditional 4-layer boards. Both solutions can improve EMI suppression performance, but only when the component density on the board is low enough and there is enough area around the components (where the required power copper layers are placed).

The first one is the preferred solution. The outer layers of the PCB are the ground layers, and the two middle layers are the signal/power layers. The power supply on the signal layer is routed with wide traces, which makes the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low. From an EMI control standpoint, this is the best 4-layer PCB structure available. In the second scheme, the outer layer takes the power and ground, and the middle two layers take the signal. Compared with the traditional 4-layer board, the improvement of this scheme is smaller, and the interlayer impedance is as bad as the traditional 4-layer board.
If trace impedance is to be controlled, the above stacking schemes require very careful routing of traces under the power and ground copper islands. In addition, copper islands on power or ground planes should be interconnected as closely as possible to ensure DC and low frequency connectivity.
6-layer board If the component density on a 4-layer board is relatively high, a 6-layer board is preferred. However, some stacking schemes in the 6-layer board design are not good enough to shield the electromagnetic field, and have little effect on reducing the transient signal of the power bus. Two examples are discussed below.
In the first example, the power supply and ground are placed on the 2nd and 5th layers, respectively. Due to the high impedance of the copper cladding of the power supply, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of impedance control of the signal, this method is quite correct.
The second example places power and ground on the 3rd and 4th layers, respectively. This design solves the problem of power supply copper cladding impedance. Differential mode EMI increases due to the poor electromagnetic shielding performance of the 1st and 6th layers. If the number of signal traces on the two outer layers is minimal and the trace length is short (less than 1/20 of the wavelength of the highest harmonic of the signal), this design can solve the differential mode EMI problem. The suppression of differential mode EMI is particularly good by filling the no-component and no-trace areas on the outer layer with copper and grounding the copper area (every 1/20 wavelength interval). As mentioned earlier, the copper area should be connected to the internal ground plane at multiple points.

Common high-performance 6-layer board designs typically have layers 1 and 6 as ground planes, and layers 3 and 4 for power and ground. EMI suppression is excellent due to two centered dual microstrip signal line layers between the power and ground planes. The disadvantage of this design is that there are only two layers of traces. As mentioned earlier, the same stack-up can be achieved with a traditional 6-layer board if the outer layer traces are short and copper is placed in the non-trace areas.
Another 6-layer board layout is signal, ground, signal, power, ground, signal, which enables the environment required for advanced signal integrity designs. The signal layer is adjacent to the ground plane, and the power and ground planes are paired. Obviously, the downside is the unbalanced stacking of layers.

This usually causes trouble in manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. If the copper density of the third layer is close to the power layer or the ground layer after copper filling, this board can be loosely regarded as a structurally balanced circuit board. . The copper filling area must be connected to power or ground. The distance between the connection vias is still 1/20 wavelength, not necessarily everywhere, but ideally should be connected.

10 layer board

Because the insulation between the multilayer boards is very thin, the impedance between layers of a 10- or 12-layer board is very low, and excellent signal integrity can be expected as long as there are no problems with delamination and stacking. Making a 12-layer board at 62 mil thickness is more difficult, and there are not many manufacturers that can process a 12-layer board.

Since there is always an insulating layer between the signal layer and the return layer, it is not optimal to allocate the middle 6 layers to route the signal lines in a 10-layer board design. Also, it is important to have the signal layer adjacent to the loop layer, i.e. the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.

This design provides a good path for the signal current and its loop current. A proper routing strategy is to route layers in the X direction, layer 3 in the Y direction, layer 4 in the X direction, and so on. Looking at the traces intuitively, layer 1 and layer 3 are a pair of layered combinations, layers 4 and 7 are a pair of layered combinations, and layers 8 and 10 are the last pair of layered combinations. When it is necessary to change the direction of the traces, the signal lines on the first layer should be changed to the third layer through "via holes". In practice, it may not always be possible to do so, but as a design concept try to adhere to it.

Likewise, when the trace direction of the signal is changed, it should be via vias from layers 8 and 10 or from layer 4 to layer 7. Routing this way ensures the tightest coupling between the forward path and the return path of the signal. For example, if the signal is routed on layer 1 and the loop is routed on layer 2 and only on layer 2, then the signal on layer 1 goes to layer 3 even if it is "via" The loop remains on layer 2, maintaining low inductance, high capacitance, and good electromagnetic shielding.

What if the actual wiring is not like this? For example, the signal line on the 1st layer goes to the 10th layer through the via hole. At this time, the loop signal has to find the ground plane from the 9th layer, and the loop current needs to find the nearest ground via hole (such as the ground pin of components such as resistors or capacitors) . If you happen to have such a via nearby, you're really lucky. If there are no such close vias available, the inductance will increase, the capacitance will decrease, and the EMI will definitely increase.

When the signal line must leave the current pair of wiring layers to other wiring layers through vias, ground vias should be placed near the vias, so that the loop signal can smoothly return to the appropriate grounding layer. For layer 4 and 7 layered combination, the signal return will be from the power or ground plane (i.e. layer 5 or 6), because the capacitive coupling between the power and ground planes is good and the signal is easy to transmit .

Design of Multiple Power Layers If two power layers of the same voltage source need to output a large current, the circuit board should be arranged into two sets of power layers and ground layers. In this case, insulating layers are placed between each pair of power and ground planes. In this way, we get the two pairs of power bus bars with equal impedance that we expect to divide the current equally. If the stacking of power planes creates unequal impedances, the shunting will not be uniform, the transient voltage will be much larger, and the EMI will increase dramatically.

If there are multiple supply voltages with different values on the board, then multiple power planes are required, keeping in mind to create their own paired power and ground planes for the different power supplies. In both cases above, keep in mind the manufacturer's requirements for a balanced structure when determining the placement of the mating power and ground planes on the board.

Summary Given that most engineers design boards as conventional printed circuit boards with a thickness of 62 mils and no blind or buried vias, this discussion of board layering and stacking is limited to this. For boards with too different thicknesses, the layering scheme recommended in this article may not be ideal. In addition, circuit boards with blind or buried vias are processed differently, and the layered approach in this paper is not applicable.

Thickness, via process and the number of layers in the circuit board design are not the key to solving the problem. Excellent layered stacking is to ensure the bypass and decoupling of the power busbars and to minimize the transient voltage on the power or ground plane. And the key to shielding the electromagnetic fields of signals and power. Ideally, there should be an insulating isolation layer between the signal trace layer and its return ground layer, and the paired layer spacing (or more than one pair) should be as small as possible. Based on these basic concepts and principles, a circuit board that can always meet the design requirements can be designed. Now that IC rise times are and will be shorter, the techniques discussed in this article are essential to solving EMI shielding problems.