Microelectronic circuits are more at risk than ever, and the main culprit is electrostatic discharge (ESD). Electrostatic discharge is a stealthy killer, especially sensitive ICs. A single ESD event can destroy a PCB. A single missed step in an ESD-resistant design can mean delays in time-to-market, slow development, and irritate customers. In some high-stress situations, it can even mean that your job is not guaranteed.
In the era of ever-shrinking microelectronics, if you don't actively stop ESD transients before they appear on a PCB trace unsuppressed, an ESD event is likely to ruin your product.
While writing this article, I just remembered a rather interesting incident a few months ago. A customer who was going mad contacted us for urgent help, hoping to protect his system from an "angry" ESD transient. The poor guy suffered a series of anti-ESD failures and ruined his product planning. He must have missed some steps.

First, he didn't implement a protection clamp circuit at any of the I/O interfaces, and he didn't place the PCB pads for the TVS clamp device as a "safety valve" measure that he needed to protect. To compound the challenge, the I/O ports on this particular product are connected to some high-speed and very sensitive communication ICs. It doesn't take much ESD to cause these boards to fail communications. Figure 1 shows an example of using clamp diodes on the data lines.

Figure 1: TVS diodes provide ESD protection on data lines. This example shows a USB 2.0 cable with ESD protection.

Revision 1 and Revision 2 are also introduced when the first board fails the ESD compliance test. This time it is no longer "guessing". The customer apparently found a Transient Voltage Suppression (TVS) clamp with an ESD rating of ±15kV. He put some TVS on some I/O ports on the board, and was pretty happy to think that the device would guarantee his system was ESD-resistant to ±15kV. While this step is in the right direction, he still fundamentally misunderstands the ESD threat. The second version of the circuit still failed the ±15kV test, although at this point he found that using TVS brought some improvement. Figure 2 shows how the TVS diode "clamps" the voltage from the ESD pulse.

Figure 2: Clamping diodes reduce the voltage from the ESL pulse, thus effectively preventing damage to your circuit. Transient Environment: Transient environment Transient voltage: Transient voltage Transient current: Transient current Clamped voltage: Clamping voltage TVS Diode: TVS diode Data Line Transceiver IC: Data Line Transceiver IC

Having suffered two electric shocks, the engineer turned to us in a panic. As we drilled down into the problem, I really felt the engineer's anxiety and fear. In fact, I have a deep feeling that ESD transients swarming on this engineer's PCB traces would not only harm the communication devices on the board, but could literally threaten his job. He has long needed a solution. With time running out and an impatient customer on the other end of this deferred design, we took over. He sent the board to our Semtech lab, expressly wanting us to protect the product from ESD damage, and thus his reputation and work.

However, the first misunderstanding we need to clear up is that the ±15kV rating on the TVS clamp device data sheet has little to do with the system level protection threshold he wants to achieve on the PCB. That rating refers to the fault threshold of the TVS device itself, but does not equate to the guaranteed noise immunity of the system. As it turns out, his system circuitry is too sensitive to achieve ±15kV system-level noise immunity while meeting the capacitance constraints and size requirements for TVS devices.

Also I want to explain that not all TVS devices are created equal. The clamping performance of the two TVS clamping devices from different manufacturers can be very different. If the product development cycle is very tight, choosing cheap, copycat TVS devices is not a good strategy. So we revamped his board with some newer high-performance low-side clamp devices - these can suppress very high peak currents. In this way, the anti-jamming performance of this board has been significantly improved, as shown in the figure below.

Figure 3: Adding transient voltage suppression can significantly reduce the clamping voltage, protecting sensitive ICs. Voltage: voltage

TVS Clamping Response ( 8kV Contact Discharge): TVS Clamping Response ( 8kV Contact Discharge) 8kV Contact voltage waveform: 8kV Contact Voltage Waveform No external TVS protection implemented: Clamped ESD voltage ( 8kV contact) with Semtech RClamp0531TQ TVS: Clamping ESD Voltage (8kV Touch Voltage) Using Semtech RClamp0531TQ TVS Time: Time

His system now passes the ±8kV test with ease (±8kV is enough in most cases). The board still failed the ±15kV contact discharge test (extended target), but it was much better than the previous results. On top of this, to further improve the robustness of the system, we added a small series resistance to the line, which is enough to suppress residual transient currents, but not enough to affect signal performance.

While adding resistance is not the most ideal solution, it does improve ESD resistance and provides a relatively easy fix to implement at such a late stage of the design. The end result is that all is well: robust products, happy end users, happy bosses, and engineers with a better understanding of ESD protection. As they say, "Adding the resistance makes a big difference." I suspect that in his next design, our friend will be more proactive in avoiding any last-minute ESD mishaps.