V_Offset (1Ch) - The difference between the reference VSYNC signal and the output VSync and/or V Blank Line, with a control range of 0 to +1 frame. All line-based timing output signals are delayed in this register by the programmed vertical offset. The coding scheme of the clock phase offset register (1Dh) is shown in Table 3-1. The programmed offset will be in the positive direction. Note that the step size will depend on the frequency of the output video clock. Note: If VID_STD[5:0]=63 and the reference format has been changed, care must be taken to ensure that the clock phase offset register is correctly programmed for the new output before applying the reference format.

The value programmed in the HL offset register (1BH) cannot exceed the maximum value. The number of clock cycles per line of the output video standard. Also, this value programmed in the VX offset register (1CH) cannot exceed the maximum number of lines per frame for the output standard. Both horizontal and vertical offsets will be in the positive direction. Negative offset (forward) is achieved by programming a value in the appropriate register equal to the maximum allowed offset minus the desired value. go ahead.

notes:

1. The device delays all output timing signals relative to the input by 2 PCLKsHSYNC reference. Even if the H_offset register is not programmed. The user can compensate for this delay by subtracting 2 PCLK cycles from the desired horizontal offset before loading the value into the host interface.

2. For sync and blanking based input references, the device will advance all line based output timing signals with respect to all output standards except VID_STD[5:0]=4, 6 and 8. even if the V_offset register is not programmed. The user can compensate for this when loading the value into the register.

3. To lock the "f/1.001" HD output standard to the 525 -line SD input reference time standard and vice versa, the device will delay all line-based output timing signals through the ΔVSync line relative to the input VSync reference. even if the V_offset register is not programmed. The user can compensate for this delay by subtracting the ΔVSync line value from the desired vertical offset into the register before loading. The value of ΔVSync is given by the following formula: HSYNC_IN_Period = period of the H reference pulse ΔVSYNC_HSYNC = time difference between the leading edges of the applied V and H reference pulse H Sync_OUT_Period = period of the generated H Sync output Figure 3-1. H_Feedback_Divide indicates the frequency at which the clock frequency is output to the H reference pulse.

4. For sync-based input references, the device will advance all line-based outputs if the value programmed in the H_offset register is greater than 1 line timing signal by more than 20. The user can pass the desired vertical offset before loading the value into the register. Also, internally when H_Offset=20, the device will remain genlocked though. The user can choose to block these lock signals so that the device continues to report in this situation.

5. For blanking-based input references, the device will advance all line-based outputs if the value programmed in the H_offset register is greater than 1 line timing signal from the start of H Sync to the end of the output video clock cycle number of active video ( from Hsync_ to EAV) +20. The value of Hsync_to_EAV is reported in register 51h and changes according to the selected output video. The user can compensate for this lead by adding a line to the previous desired vertical offset by loading this value into the register. Also, the internal Vúulock and Fúulock signals reported in bits 3 and 4 of register 16h when H_offset will be low = Hsync_to_EAV+20 only, but the device will remain in genlock. The user can choose to block these lock signals so that the device continues to report in this situation.

6. Offsets that occur as described in Notes 1-5 are independent of each other and must be interpreted as such.

3.2.1.2 Freeze Mode

The GS4911B /GS4910B will enter freeze mode when the device is in Genlock mode and the input reference is removed. The device describes the re-acquisition of the input reference signal in section 3.5.3 on page 47 and loss. In freeze mode, the frequency of the output clock and timing signals will remain unchanged within +/-2ppm. Assume that the loop bandwidth is 10Hz. Also, if the 27MHz reference crystal is moved in freeze mode, the frequency timing signal of the output clock will also change.

3.2.2 Free running mode

When the GENLOCK pin is set high, the GS4911B/GS4910B will enter free running mode at the application layer. In this mode, all frequencies appear based on the external 27MHz reference input. Therefore, the frequency and timing signal of the output clock will have the same accuracy as the crystal reference. If running in free running mode, using a more precise crystal (eg 10ppm) ensures accurate clock and timing signals are produced. Note: In free running mode, the audio clock of the GS4911B will remain the video clock.

Figure 3-2 summarizes the difference in output accuracy for each operating mode. Assuming the crystal reference is +/-100ppm, the output clock and timing signals will be as accurate as the crystal in free running mode. In Genlock mode the frequency will be as accurate as the input reference regardless of crystal accuracy. In freeze mode, the frequency of the output clock and timing signals will remain unchanged within +/-2ppm.

3.3 Output timing format selection

The application layer should set the external VID_STD[5:0] and ASR_SEL[2:0] pins immediately when the device is powered up (as described in section 3.14 on page 111). The Video Standard[5:0] pins are used to select a pre-programmed output video format, or to indicate that custom timing parameters will be programmed in the host interface. The ASR_SEL[2:0] pins are only available on the GS4911B and are used to select the base audio frequency or turn off the audio clock generation. The user-selectable output timing formats via the VID_STD[5:0] pins are listed in Section 1.4 on page 20. Section 3.7.2 on page 63 Table 3-7 lists the audio sample rates available through the ASR_SEL[2:0] pins. If the user sets VID_STD[5:0]=1-51 at power up, the device will first check for root lock pins. If GENLOCK is set low and a valid reference has been applied to the input, the device will output the selected video standard while trying to genlock. However, if no reference signal is applied and GENLOCK=LOW, the initial clock and timing outputs can be determined by the chip's internal default settings. If GENLOCK is set high, the device will immediately go into free running mode and will output the selected video standard correctly. If the user sets VID_STD[5:0]=62 at power up, the device will be configured to generate custom output timing signals. The initial output timing signal will be equal to the chip's internal default timing until the user program registers the host's 4Eh to 55h interface (see section 3.10 on page 74). Also, the output video clock will freeze at 74.25MHz at free running Genlock - 2ppm without input XTAL at 27MHz ± 100ppm - 100 ppm + 100 ppm

notes:

1.t represents the temperature change of the crystal

2. Charts are not scaled.

GS4911B/GS4910B HD/SD/Graphic Clock and Chrono Generator with Generator Lock Datasheet 36655 - Jun 5, 2009 Page 43 of 119 The frequency is determined by the chip's internal default settings until the user modifies it through registers 20h to 23h (see section 3.9.1 on page 72). If the user sets VID_STD[5:0]=63 at power up, the device will wait for a valid reference to have been applied, at which point it will output the same as the input reference, and if Genlock=LOW, enter Genlock mode. When running in Free Run or Genlock mode, the GS4911B/GS4910B will continuously monitor the settings of the VID_STD[5:0] and ASR_SEL[2:0] pins. If the user wishes to change the format of the output clock and timing signals, these pins can be reconfigured at any time, but it is recommended to change the output video standard

3.4 Input reference signal

HSYNC, VSYNC, FSYNC, and 10FID reference signals are applied to the GS4911B/GS4910B through the designated input pins. To operate in Genlock mode, the input reference signal must be valid and conform to a recognized video or graphics standard (see section 3.5 on page 45). Alternatively, if VID_STD[5:0]=62, the signal applied to the HSYNC input must be stable and less than 2.4ms period. In free-running mode, no references are required to be entered. Section 3.4.1 describes HSYNC, VSYNC, and FSYNC input timing. The 10 page 44 section 3.4.2 discusses the FID input signal. 3.4.1 Timing of HSYNC, VSYNC and FSYNC video formats HSYNC, VSYNC and FSYNC input reference signals may have analog timing, such as according to Gennum's GS4981/82 sync splitter (Figure 3-3), or may have digital timing, such as from Gennum's GS1559/60A/61 deserializer (Figure 3-4). Section 1.4 on page 20 lists the GS4911B/GS4910B. If the input reference format does not contain an F sync signal, the FSYNC pin should be kept low.

Graphical Format Timing The GS4911B/GS4910B are pre-programmed to recognize 16 different graphical formats of timing displayed to the input reference pin number. These graphic formats are described in section 1.4 on page 20. The supported graphics standards are all progressive and do not use the FSYNC signal. Therefore, FSYNC should be kept low by the application layer. The VESA format supports a frequency tolerance of 0.5%. VSYNC transitions are usually synchronized with the leading edge of HSYNC. The signal polarity for each format of duration is shown in Table 1-2. NOTE: The user must ensure that VID_STD[5:0]=47 and 49–54 remain active low. 3.4.2 10 Hydrogen Flame Ionization Detector The 10FID input is a reset pin that can be used to reset the voltage divider signal of the 10FID output. In the GS4911B, the 10FID input pin will also reset the splitter signal of the AFS output. This default setting interface can be modified using the host's audio control registers (see section 3.12.3 on page 79). The GS4911B resets the phase of the audio clock to the leading edge of the H sync and the 10FID input is high on the line 1 output of each output frame. This allows the user to reset the phase interface of the splitter when a custom signal is generated by the host (see section 3.7.2.1 on page 65). If the input reference format does not include a 10-field ID signal, the external 10FID input pin should be held low. The timing of the 10FID input signal is shown in Figure 3-5.

3.4.3 Polarity automatic identification

To accommodate any standard indicating display format that uses H and V sync signal polarity, the GS4911B/GS4910B will recognize the H and V sync polarity and automatically sync to the leading edge. The polarity of the HSYNC and VSYNC signals is in the video status register. Additionally, Bit 2 of this register reports the detection of analog or digital input timing. Detailed registration is described in section 3.12.3 on page 79.

3.5 Reference Format Detector

The reference format detector checks the validity of the input and analyzes the input format reference signal. It is designed to precisely differentiate between 59.94 and 60Hz frame rates.

3.5.1 Horizontal and Vertical Timing Characteristics Measurements

When a reference signal is applied to the designated input pin, the GS4911B/GS4910B will analyze the signal and report the following in registers 0Ah to 0Eh in the host interface: H Number of 27MHz clock pulses between the leading edges of the input reference signal (H_period register) Number of 27MHz clock pulses in 16 horizontal cycles (H_16_cycle register) Number of H reference pulses between leading edges of the V input reference signal (V_line register) Number of H reference pulses in two vertical cycles (V_2_line register) Number of H reference pulses in one F cycle (F_Line register) These parameters can be read through the host interface and used by the device to determine the validity of the reference signal

3.5.2 Input Reference Validity

Before the device attempts to operate in Genlock mode, the application to HSYNC and VSYNC must be valid and must conform to one of the 36 video-recognized standards described in section 1.4 on page 20 or the 16 recognized graphics standards. Alternatively, if VID_STD[5:0]=62, the device can be manually programmed so that genlock references are neither valid nor recognized (see section 3.10.1 on page 75). In order for the input reference signal to be considered valid, the periodicity of HSYNC must be between 9us and 70us, and the period of VSYNC must be between 8ms and 50ms. The FSYNC signal is not required for validity. The output video standard VID_STD[5:0]=62 is considered valid once the input reference signal is. If the input signal is valid, the device compares the input timing parameters to the reference signals of the 36 video and 16 graphics standards listed in Table 1-2 and determines whether the input reference is one of the recognized standards. If so, the VID_STD[5:0] value of the format is written to the input standard register at address 0Fh of the host interface. If the input signal is invalid, or the reference format is unrecognized, 00h has been programmed in this register. Once the reference signal is valid and recognized by the device, VSYNC and FSYNC will no longer be monitored. Loss of signal on these pins will not affect the unit. The GENLOCK pin should not be set low if VID_STD[5:0] is not set to 62 and the REF_LOST pin is high, or if the input signal is valid but not recognized as one of the 36 video or 16 graphics formats. If VID_STD[5:0]=62, the REF_LOST output will reflect the presence of a stable signal on the HSYNC input pin for a period of less than 2.4ms. This allows the user to program devices that are locked to only a single input reference. The REF_LOST output pin can also be read via Bit 0 of the Genlock_Status register (see Section 3.12.3 on page 79).

3.5.2.1 Criteria selection is not clear

There are standards that have the same H, V and F timing parameters, for example the reference format detector of the GS4911B/GS4910B cannot distinguish them. Table 3-2 groups criteria with shared H, V, and F cycles. Registered at host interface address 10h using Amb_Std_Sel, a user-selectable standard is identified with a specific set of measurements. For example, with 1716 clocks at 27MHz per line, 525 lines per frame, identified as 4fsc 525, the program Amb_Std_Sel[10:0]=xxx10xxx, where "X" means "don't care".