Video clock synthesis

Generate any video or graphics clock up to 165MHz

Pre-programmed for 8 video and 13 graphics clocks

The accuracy of the free-running clock frequency is only limited by the crystal reference

One differential and two single-ended video/graphics clock outputs

Each clock can be individually delayed for skew control Video output clock can be connected directly to Gennum's SMPTE compatible HD-SDI output Serializer Audio clock synthesis ( GS4911B only)

Three audio clock outputs

Generate any audio clock up to 512 *96kHz

Preprogrammed for 7 audio clocks

timed generation

Generates up to 8 timing signals at a time

Choose from 9 pre-programmed timing signals: H and V Sync & Blanking, F Sync, F Digital, AFS (GS4911B only), Display Enable, 10FID and up to 4 user-defined timing signals pre-programmed to 35 Different video generation timing formats and 13 different graphics display formats

Genlock function

Clock can be free-running or locked to a reference with variable offset steps of 100-200ps on the input (depending on exact clock frequency)

Variable timing offset steps of 100-200ps, up to one frame output can be cross-locked to different input references Freeze operation when reference is lost Selectable collision or drift locking when applying reference Automatic input format detection

General Features

Reduces design complexity and saves board space - 9mm x 9mm package + crystal reference replaces multiple VCOs, PLLs and timing generators Pb-free and RoHS compliant low power operation, typically 300mW 1.8V core and 1.8V or 3.3 VI/O power supply 64-pin QFN package

application

Video cameras; digital audio and/or video recording/playback backend equipment; digital audio and/or video processing equipment; computer/video monitors; DVD/MPEG equipment; digital equipment set-top boxes; video projectors; high-definition video systems; multimedia PC applications

illustrate

The GS411B is a highly flexible digitally controlled clock. Synthesizer and timing generator with genlock function. It can be used to generate video and audio clock and timing signals, and allows multiple devices to be genlocked to a single input reference. The GS4910B contains all the functions of the GS4911B, but does not provide audio clocking or AFS pulse generation. The GS4911B/GS4910B will recognize that the input reference signal conforms to 36 different video standards and 16 different graphics formats, and will generate an incoming reference to lock the output timing information. The GS4911B/GS4910B support cross-locking, allowing the output to be locked to a reference pick of a different incoming and outgoing video standard. Users can choose to output one of 8 different video sample clock rates or 13 different graphics display clock rates, or program any clock frequency between 13.5MHz and 165MHz. The selected clock frequency can use the internal divider for two video clock outputs and one LVDS video clock output pair. The video clock is frequency and phase locked to the horizontal timing reference, and can be independently delayed relative to the clock's timing output for tilt control. Provides eight user-selectable timing outputs that can automatically generate the following timing signals for 35 different video formats and 13 different graphics formats: HSync, Hblanking, VSync, Vblanking, F sync, F digital, AFS (GS4911B only) , DE and 10FID. These timing outputs can be locked to the input reference signal used for genlock timing and can be phase adjusted via internal registers. In addition, the GS4911B provides three audio sampling clock outputs that can generate audio clocks with a frequency range of up to 512fs from 9.7kHz to 96kHz. Audio-to-video phase adjustment via external 10FID input reference, 10FID signal via internal registers, or user-programmed sequence of audio frames. The GS4911B/GS4910B are lead free and the encapsulation compound is free of halogenated flame retardants (RoHS compliant).

Reference signal input

Signal levels are compatible with LVCMOS/LVTTL. The VSYNC external reference signal passes through the application layer. When the GS4911B/GS4910B is in Genlock mode, the device senses the polarity of the VSYNC input automatically and references the leading edge. If the user wishes to select a pre-programmed video and/or device-provided timing output signal, the signal must conform to one of the 36 defined video or 16 different graphics display standards supported by the device. When operating in this manner, the VSYNC input provides the vertical scan reference signal. The VSYNC signal may have analog timing, such as a delimiter from sync, or it may be digital, such as from an SDI deserializer. Section 1.4 on page 20 describes the 36 video formats and 16 graphics formats recognized by the GS4911B/GS4910B. 50, 62 IO U VDD – Power Supply Most positive power connections for digital I/O signals. Connect to +1.8V DC or +3.3V DC. NOTE: All 5 IO_VDD pins must be powered by the same voltage. 19 FSYNC Asynchronous Input Reference Signal Input signal level compatible with LVCMOS/LVTTL. The FSYNC external reference signal passes through the application layer. The first field is defined as the field of the first wide pulse (also called the sawtooth) located in the first half of the line. The FSYNC signal should be set high in the first field based on sync references. If the user wishes to select a pre-programmed video and/or device-provided timing output signal, the signal must conform to one of the 36 defined video or 16 different graphics display standards supported by the device. When operated in this way, the FSYNC input provides the parity field input reference. The FSYNC signal may have analog timing, such as a delimiter from sync, or it may be digital, such as from an SDI deserializer. 36 video formats and 16 graphics formats recognized by the GS4911B/GS4910B. For blanking-based references, the FSYNC signal should be set high in the second match. Note: If the input reference format does not include the F sync signal, this pin should be held low.

notes:

1. Capacitance values listed represent total capacitance, including discrete capacitance and parasitic plate capacitance.

2.X1 is used as an input, it can also accept a 27MHz clock source. To accommodate this, mismatched capacitor values are recommended.

Figure 1-1: XTAL1 and XTAL2 reference circuit

1.4 Preprogrammed Approved Video and Graphics Standards Table 1-2 describes the GS4911B/GS4910B. 36 Different Video Formats and 16 Different Graphics The display formats listed below can be applied to the GS4911B/GS4910B and automatically detected by the reference format detector. In addition, in addition to VID_STD[5:0]=2, 52, 53 or 54, the video standard[5:0] pin can be output by setting the timing output pin. In addition to the preprogrammed video standards listed in Table 1-2, custom output timing signals can be generated by the GS4911B/GS4910B. Custom Timing Parameters are programmed in the host interface when VID_STD[5:0] is set to 62 (see Section 3.10 on page 74). Setting VID_STD[5:0] to 63 will cause the device to produce timing with the same output format as the detected input reference. If desired, this can be done by setting the Video Control Register, which is available through the Host Interface's Video Standard[5:0] registers (see Section 3.12.3 on page 79). Although in this case the external video standard[5:0] pins will be ignored, they should not be left floating.

1.5 Output Timing Signals Table 1-3 describes the output timing signals Timing 1 to Timing 8 provided to the user through the pins. The user can output any of the signals listed below from the host interface by programming the output select registers on each pin. s Company Table 1-3: Output Timing Signal Signal Name Description Default Output Pin H Sync H Sync signal has a leading edge pulse at the start of horizontal sync. Its length is determined by the chosen video standard, or by the host interface. The width of the H sync output pulse is determined by the selected video standard. Table 1-2 lists each pre-programmed video and graphics standard GS4911B/GS4910B. Custom video timing parameters can also be programmed in the host interface to define a unique H-Sync width. In Genlock mode, the leading edge of the output H-Sync signal is nominally the half-amplitude point of the reference at the same time as the HSYNC input. This timing can be offset using the Genlock offset register starting at address 1Bh of the host interface. By default, the polarity of the H sync signal output will be actively low-key after a system reset. The polarity can be selected as active high by programming the polarity register at host interface address 56h. Timed 1H blanking The H blanking signal is used to indicate that the video line does not contain active video data. For video lines that contain valid video samples. The signal will be at the first valid pixel of the row, and the high pixel after the last valid pixel of the row. During the entire horizontal blanking process, the H blanking signal maintains a higher period. The width of this signal will be determined by the selected video standard, or by the host interface. In Genlock mode, the output H blanking signal will be phase locked to the HSYNC input. Genlock offset registers starting at host interface address 1Bh can be used. The default polarity of this signal can be programmed by programming the polarity register at address 56h of the host interface.

Detailed description

3.1 Function overview

The GS411B/GS410B is a highly flexible digitally controlled clock synthesis circuit. And a timing generator with genlock function. The device has two main modes of operation: Genlock mode and Free Run mode. In Genlock mode, the video clock and timing outputs will be frequency and phase locked to the detected reference input signal. In free-running mode, all frequencies are based on a 27MHz external crystal reference. The GS4911B/GS4910B will recognize input reference signals that conform to 36 different video standards and 16 different graphics formats. It supports cross-locking, allowing the output to be genlocked to a different video standard than the selected output video standard. The GS4911B/GS4910B will enter freeze mode when the device is in Genlock mode and the input reference is removed. In this mode, the output clock and timing signals will maintain their previously locked phase and frequency at +/- 2pm. Users can choose to output 8 different video sampling clock rates or 13 different graphics display clock frequencies, or programmable from 13.5MHz to 165MHz. The selected clock frequency can be further divided internally, and two video clock outputs and one LVDS video clock output pair are available. The video clock can be timing output for clock deviation, and should also be individually delayed phase control. Eight user-selectable timing outputs are provided to automatically generate timing signal formats that track 35 different video formats and 13 different graphics: HSync, Hblanking, VSync, Vblanking, F sync, F digital, AFS (GS4911B only), DE, and 10 hydrogen flame ionization detectors. Alternatively, a custom output timing signal interface can be programmed in the host. In addition, the GS4911B provides three audio sampling clock outputs that can generate audio clocks up to 512fs with a frequency range of 9.7kHz to 96kHz. The audio and video phases are referenced via an external 10FID input, via internal registers, or a user-programmed sequence of audio frames.

3.2 Operation Mode

The GS4911B/GS4910B will operate in Genlock mode or Free Run mode depending on the setting of the GENLOCK pin. If desired, this can be done by setting the Genlock_Control register (address 16h) so that the Genlock can pass through the host interface. Although the external GENLOCK pin will be ignored in this case, it should not be left floating

3.2.1 Genlock Mode

When the application layer sets the GENLOCK pin low and the device has successfully genlocked the output to the input reference, the GS4911B/GS4910B will enter Genlock mode. In this mode, all clock and timing generator outputs will be frequency and phase locked to the detected input reference signal. The PCLK output will be locked to the H reference. In Genlock mode, the applied reference signal is used. A 27MHz crystal reference is necessary; however, neither crystal accuracy nor crystal frequency changes (due to operating temperature) will affect the output signal. For example, the output signal will generate with the same accuracy whether a 27MHz reference crystal has an accuracy of 10ppm or 100ppm. The GS4911B/GS4910B support cross-locking, allowing the output to be locked to a different incoming reference than the selected output video standard. NOTE: Before setting, the user must reference GENLOCK=LOW on the device's input application. If the GENLOCK pin is set low and there is no reference signal, the generated device clock and timing outputs can set the chip to correspond to the internal defaults until the reference is applied. 3.2.1.1 Genlock Timing Offset By default, the phases of the clock and timeout signals are genlocked to the input reference signal. These output signals can be phase-adjusted relative to the input referenced through the programming host interface. The offset is programmed separately by clock phase, horizontal phase, and vertical phase (ie, fraction of pixels, pixels, and lines). Genlock timing offsets can be used to synchronize the output of devices including the GS4911B/GS4910B, where the outputs of other devices are located. Signals leaving a device containing the GS4911B/GS4910B may pass through a processing device switch with a significantly fixed delay before arriving. These delays can include video line delays or even field delays. To compensate for these delays, the genlock timing offset allows the user to reference the output of the device relative to the input. Using the host interface, once the device is stably locked: Clock Phase Offset (1Dh) - range from 0 to 1 clock pulse in increments between 1/64 and 1/512 of a clock period (depending on PCLK frequency). This increment is between 100ps and 200ps. All clock and timing output signals will be delayed by the clock phase offset programmed in this register. H_Offset (1Bh) - Reference to the difference between the HSYNC signal and the H sync and/or H blanking signal in the output clock pulse, with a control range of 0 to +1 lines. All timing output signals will be delayed in this register by the programmed horizontal offset.