Functional description

LMX2502 and LMX2512 highly integrated, high and small size performance, low power frequency synthesizer –5.0 mm x 5.0 mm x 0.75 mm 28 -pin WQFN system, optimized Korean PC and Korean computers Packaging honeycomb CDMA (1xRTT, IS-95) mobile phone. In terms of the radio frequency synthesizer system that uses proprietary digital locks, LMX2502 and LMX2512 generate very integrated RF VCO stable, low -noise local oscillator signals

–5.0 mm x 5.0 mm x 0.75 mm 28 stitches WQFN system

-The integrated ring circuit filter in wireless communication

-The scores of low, low phase noise.

-The 10 KHz frequency resolution PLL based on incremental-Sigma-based maker.

–Nteger-N, if PLL and LMX2512 support the frequency band of Korean honeycomb.

- Programmable charge pump current

- The programmable frequency includes a 4 -level programmable charge pump.

–19.20/19.68 MHz LMX2502 and LMX2512 completely closed

The ring -frequency combination system.

–2.8 ilgrimity is 17 mAh

The N -RF lock ring based on 11 -bit Delta Sigma LMX2502 and LMX2512 includes voltage controller oscillator (VCO), ring circuit filter and ring circuit filter, and the ring circuit If the score n radi frequency consistently, if the synthetic system is consistent, these modules constitute a closed -loop radio frequency synthetic system. LMX2502 supports the Korean PCS frequency band LMX2502 and LMX2512 If the PLL level, it includes an integer -N also. For the more flexible ring filter design, the mid-frequency lock ring is supported by the external VCO and the ring circuit filter, and the fast lock time: 500 μs serial data transmits to the device wired microfiller via three-low-current consumption transmission Interface (Data, Le, CLK). The voltage range of the working power supply is 2.7 V to 3.3 V.

2.7 V to 3.3 V operation LMX2502 and LMX2512 have low current characteristics

Digital filter lock detection output consumption: 17 mAh, 2.8 volts.

Hardware and software power off control LMX2502 and LMX2512 have 28 -pin WQFN packages.

Application

Korean PCS CDMA system

Korean honeycomb CDMA system

(1) Absolute maximum rated value indicates the limit that may cause damage. The proposed operating conditions indicate that the equipment is expected to work normally, but it cannot ensure the conditions for specific performance restrictions. To ensure specifications and test conditions, see the electrical characteristics part. The ensuring specifications are only applicable to the listed conditions.

(2) This device is a high -performance radio frequency integrated circuit, static discharge rated value lt; 2KV, which is sensitive to electrostatic discharge. The handling and assembly device should be held at the anti -static workstation.

(3) GND u003d 0 volts.

(4) If you need military/aerospace special equipment, please contact the Texas Instrument Sales Office/dealer to obtain standardization.

Electrical features

(VCC u003d VDD u003d 2.8 V, TA u003d 25 ° C; unless there is another instructions)

(1 ) In the power off mode, set the DATA, CLK and LE pin to 0 V (GND).

(2) You must also use the OSC_FREQ control bit to program the reference frequency.

Electrical features (continued)

(VCC u003d VDD u003d 2.8 V, TA u003d 25 ° C; unless otherwise explained)

] (3) For other frequency range, please contact Texas instruments.

(4) Locking time means that the time difference between the start of the frequency conversion and the frequency change point is kept within the +/- 1 kHz range of the final frequency.

(5) The frequency of text R4 and R5 can be used for programming except the default value. For details, see programming instructions.

General description

LMX2502/12 is a highly integrated frequency synthetic system that can generate a signal CDMA for the PC and cellular network. These devices include all functional module detectors and ring circuit filters of lock -locking loops, radio frequency pressure control oscillators, premature frequency, and radio frequency phase. The demand for external components is limited to a few passive components to match output impedance and power stable line components. In addition to the radio frequency circuit, the integrated circuit also includes the mid -frequency synthesis of the interior voltage control oscillator and the circuit filter of the mid -frequency splitter and the intermediate frequency viewer. Table 1 summarizes the default medium frequency. Using a low-mixed score N synthesizer based on the Delta-Sigma modulator, the circuit can support the channel interval of 10kHzpcs and the cellular CDMA system. Score N synthesizers can lock time faster, thereby reducing power consumption and system settings. In addition, compared with the INTEGER-N structure, the area of u200bu200bthe ring filter occupies a smaller area. This allows the loop to embed the filter into the circuit to minimize external noise coupling and total shape factor. Delta SIGMA standThe structure provides very low bruises, which may be an important issue in other PLL solutions. The circuit also supports the frequency of commonly used 19.20 MMS and 19.68 MMS.

The frequency generates

RF-PLL part

The following formula can be used to calculate the diversion ratio:

lmx2502 – pcs CDMA:

FVCO u003d {8 x RF_B+RF_a+(RF_FN/FOSC) x 104} x fosc (RF_a LT; RF_B)

lmx2512 -cellular cdma:

fvco u003d {6 x ×B+RF_a+(RF_ (RF_ -FN/FOSC) X 104} X FOSC (RF_A LT; RF_B)

FVCO: The output frequency of the voltage control oscillator (VCO)

RF_B: Pre -pre -pre -pre -programming counter pre -pre -programmaker pre -pre -pre -programmer pre -pre -mixed counter pre -pre -pre -programmeter pre -pre -pre -can counters Set frequency (2≤RF_B ≤15)

RF_a: The frequency -frequency ratio of the preset binary 3 -in swallow counters (for LMX2502, 0≤RF_A ≤ 7; for LMX2502, 0 ≤RF_a≤5lmx2512) [) [ 123]

RF_-Fn: Preset molecules of a binary 11-bit module counter (for FOSC u003d 19.20 mHz or 0≤, u200bu200b0≤RF_FN LT; 1920 for fosc u003d 19.68 mHz, RF_FN LT; 1968)

FOSC: Reference oscillator frequency

IF-PLL part

fvco u003d {16 x IF_B+IF_a} x fosc/If u r Where (if_a lt; if_b)

fvco : The output frequency of the voltage control oscillator (VCO)

IF_B: The preset frequency of the binary 9 -bit programmable counter (1≤IF_B ≤ 511)

IF_a: binary 4 swallows The preset division of the counter (0≤if_a≤15)

FOSC: Reference oscillator frequency

IF_R: Binary 9 -bit programmable reference counter preset frequency ratio (2≤ If_r ≤ 511)

According to the above equal formula, LMX2502/12 generates a fixed medium frequency summarized in Table 1.

VCO frequency tuning

The central frequency of the radio frequency pressure control oscillator is determined by the resonant frequency of the resonant circuit. This fuel tank circuit is implemented on the chip without external sensors.LMX2502/12 actively adjusts the frequency of the fuel tank to the built -in tracking algorithm. During the frequency capture period, the bandwidth control and frequency lock are significantly extended to the ring bandwidth to achieve the frequency lock. Once the frequency is locked, the locking loop will return to a stable state, and the ring bandwidth is set to the nominal value. The conversion between the collection and lock mode is seamless and extremely fast, so it meets the strict requirements related to the locking time and phase noise. Multiple controls (BW_DUR, BW_CRL, and BW_EN) are used to optimize locking time performance. In order to improve the bruises of the device, pseudo -restores can be selected by two kinds of strange inhibitory solutions:

Continuous optimization scheme, tracking environment and voltage changes, providing false false conditions under the optimal changes conditions Performance

One -time optimization scheme, only when PLL enters the lock state.

Miscellaneous suppression can also be disabled, but it is recommended that continuous optimization mode for normal operation.

Power off mode

LMX2502 and LMX2512 include power -off mode to reduce power consumption. LMX2502/12 By entering the CE pin at a low level or set the power -off mode in the register, enter the power -off mode R1. Table 2 summarizes the power -off function. If the CE settings are low, the storage value is regarded. When the CE is high, set the register position by setting up.

Lock detection

LD output can be used to indicate the lock status of the RF ring ring. The position 21 in the register R0 is displayed on the LD pin. When the RF lock is not locked, the LD pin is kept low. After obtaining the phase, the LD pin will have a logical high level. The output can also be programmed to always ground.

(1) When the phase error is greater than TW2, the LD output becomes lower.

(2) When the phase error is less than TW1, the LD output becomes higher when the phase error is less than TW1.

(3) Measure the phase error in the front edge. Only marked errors greater than TW1 and TW2.

(4) TW1 and TW2 are equal to 10 ns.

(5) FR and FN per lock detection comparison per 64 cycles.

Microfil interface

The programmable register group access through the micrine serial interface. The interface includes three signal pins: CLK, Data, and Le (闩 lock enable). Serial data (DATA) is recorded to the clock ascending edge (CLK). The last one decodes internal control register address. When the lock lock is enabled, the data stored in the displacement register is loaded to the corresponding control when it is enabled (le) to register.

Programming instructions

General programming information

The serial interface has a 24 -bit displacement register to store the input data bit when it comes. The transmitted data is loaded from MSB to the displacement register of LSB. The data rises along the clock signal. The lock memory enable signal from low to high, the data stored in the shift register is transmitted to the correct register depends on the setting of the address position. The selection of a specific register consists of binary representations of the address level equal to controlling register numbers. At the initial startup, Microwire loaded 4 default words (register R3, first loaded, then R0, loaded last). After initial programming the device, a single register (R0) can be used. If the medium frequency beyond the default value of the device is required, the SPI_DEF bit should be set to 0 if the value is set, and if the value of U is 0, set U to 0.

Control the contents of the register describes how to allocate the bit in each control register to a specific control function.

Note: The digital number represents the address position.

R0 register

The address bit of the R0 register (R0 [1: 0]) is ""00"".

SPI_DEF is selected between using the default IF counter value and user programming value. Only the default counter value is required to only R0 to R3 (register R3, first load, then to R0, and finally load) after the initial power is sent. RF-U LD activates the lock detection output of the LD pin (pin 19). The lock detection mode shows the state of locking the RF lock ring. The waveform of the lock detection mode is shown in the explanation part of the lock detection in Figure 2. The RF N counter consists of a 4 -bit programmable counter (RF_B counter), 3 swallow counter (RF_A) components), and 11 digits of Delta Sigma modulator (RF_FN counter). The calculation counter value is shown below.

RF_B: The preset frequency ratio of the binary 4 -bit programmable counter (2≤RF_B ≤ 15)

] RF_A: The frequency ratio of the binary 3-bit swallow meter (for LMX2502, 0≤RF_a≤7, for lmx2502, 0≤RF_a≤5lmx2512)

RF_-Fn: Pre-pre-pre-pre-made 11-bit module counter pre-pre-module countor Set molecules (0≤RF_FN LT; 1920, FOSC u003d 19.20 mHz; 0≤RF_FN LT; 1968, for FOSC u003d 19.68 MM).

Reference oscillator frequency

Note: If you need to use the reference frequency outside the regulations.

R1 register

R1 register address position (R1 [1: 0]) is ""01"".

The medium frequency level selection is applicable to the default medium frequency of a specific CDMA system. For the default IF frequency of LMX2502 is 440.76 MHz, the default IF frequency of LMX2512 is 367.20 MHz and 170.76 MHzmHz, depending on the variant. Reference frequency selection bit (OSC_FREQ) select 19.20 MHz or 19.68 MHz as the reference oscillator frequency. The internal bruises inhibitory scheme is controlled by the band [1: 0] bit. There are two different branch line simplified solutions: continuous tracking mode and single optimization mode. The continuous tracking mode will be adjusted according to changes in voltage and temperature. A single optimization mode fixes compensation parameters only when the lock -in -loop enters the lock state. Bone spurs can also be disabled, but it is recommended to use the continuous mode of normal operation. OB_CRL [1: 0] bit determines the power level of the radio frequency output buffer. The power level can be based on the system requirements. Two bits, rf_en and if_en, logically select the activation status of the radio frequency synthesizer system and the intermediate frequency lock ring, respectively. By using CE control pin (pin 20), the entire IC can be placed in a power off state.

R2 register

R2 register address position (R2 [1: 0]) is ""10"".

IF_UCUR [1: 0] bit programming IF oil supply pump current. Considering the external IF VCO and ring circuit filter, users can choose the amount of fuel pumps 100 μA, 200 μA, 300 μA, or 800 μA.

R3 register

R3 register address position (R3 [2: 0]) is ""011"". The register R3 contains controls for phase lock bandwidth control (BW_DUR, BW_CRL, and BW_en). The duration of the digital controller part of this bandwidth control is set by BW_DUR [1: 0]. Set the minimum use 00 and increase the duration to the maximum value set to 11. BW_CRL [1: 0] Set the phase offset standard for the bandwidth controller. Once the phase offset between the base clock and the divided VCO signal is in the set standard, the bandwidth control stops. The maximum phase offset is set to 00 and reduced to the minimum value set to 11. BW_EN enables bandwidth control when locking. VCO dynamic current is also controlled in the register R3 through VCO_CUR [1: 0]. The minimum value corresponds to 00 and increases to the maximum value of 11.