1.0 Main Features

Three on-chip phase-locked loops with programmable reference and feedback dividers

Four independently programmable mux and postscalers

I2 class C 8482 ; bus serial interface

Programmable power down for all PLLs and output clock drivers

One PLL and two mux/postscaler combinations are modifiable via the SEL_CD input

Tri-state outputs for board testing

5V to 3.3V operation

Accepts 5MHz to 27MHz crystal resonators

Commercial and industrial temperature ranges available

2.0 Overview

The FS6377 is a CMOS clock generator integrated circuit designed to minimize cost and component count in a variety of electronic systems. three. C-Programmable Phase Locked Loops (PLLs) provide a high degree of flexibility with four programmable mux and postscalers.

3.0 Function Block Description

3.1 Phase Locked Loop (PLL)

Each of the three on-chip PLLs is a standard phase-locked loop and frequency-locked loop structure that multiplies the reference frequency by the desired frequency expressed as an integer ratio. This multiplier is precise. As shown in the figure, each PLL consists of a reference voltage divider, a phase-frequency detector (PFD), a charge pump, an inner loop filter, a voltage-controlled oscillator (VCO), and a feedback divider. During operation, the reference frequency (fREF) generated by the on-board crystal oscillator is first lowered by the reference divider. The divider value is called the "modulus" and is expressed as the NR of the reference divider. The segmented reference is then fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through a charge pump and loop filter. The VCO provides a high-speed, low-noise, continuously variable frequency clock source for phase-locked loops. The output of the VCO is fed back to the PFD (modulus is represented by NF) closed loop through the feedback divider. The PFD will drive the VCO frequency up or down until the divided reference frequency and divided VCO frequency appear equal at the input of the PFD. The input/output relationship between the reference frequency and the VCO frequency is:

3.1.1. reference voltage divider

The reference divider is designed for low phase jitter. The divider receives the output of the reference oscillator and provides the divided down frequency to the PFD. The reference divider is an 8-bit divider that can be programmed to any modulo programming equivalent binary value between 1 and 255. Divide by 256 can also be achieved by programming 8 bits to 00h.

3.1.2. Feedback distributor

The feedback divider is based on a dual-modulus prescaler technique. This technique allows for a fully programmable feedback divider while still allowing the programmable part to operate at low speed. A high-speed prescaler (also called a prescaler), due to the high speed of the VCO, is placed between the VCO and the programmable feedback divider to operate. Dual-mode technology ensures reliable operation of the VCO at any speed and reduces the power consumption of the voltage divider.

FS6377

For example, a fixed division of 8 can be used in the feedback divider. Unfortunately, dividing by 8 limits the modulus of the entire feedback divider to multiples of 8. This limitation will limit the PLL's ability to achieve the desired input frequency to output frequency ratio without making both the reference and feedback divider values relatively large. A larger feedback modulus means that the VCO has a relatively low crossover, requiring a wider loop bandwidth to allow lower frequencies. A narrow loop bandwidth tuned to high frequencies is critical to minimize jitter; therefore, divider blocks should always be kept as small as possible. To understand the operation, see Figure 4. M counter (modulo is always equal to M) with dual modulo cascaded prescaler. A counter controls the modulo of the prescaler. If the value programmed in the A counter is A, the prescaler will be set to divide by N+1 as the prescaler output. After that, the prescaler divides by N until the M counter output resets the A counter and the cycle begins again. Note that N=8, A and M are binary numbers. Suppose the A counter is programmed to zero. The modulus of the prescaler is always fixed at N; and the feedback divider becomes MxN. Next, suppose the A counter is programmed to 1. This causes the prescaler to switch to divide by N+1 as its first divide cycle, and then revert to divide by N. Actually, a counter is feeding back the distributor. The total modulus is now considered equal to MxN+1. This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A

3.1.3. Feedback divider programming

In order to operate the feedback distributor correctly, the A counter must only be programmed for values less than or equal to Mcounter. Therefore, not all divider modules below 56 are available. The choice of divider value is shown in Table 2. Above modulo 56, the feedback divider can be programmed to any value up to 2047.

3.2 Mux after voltage divider

As shown, the input mux in front of each postscaler stage can select the frequency from the PLL frequency or the reference signal. Frequency selection is done via the I2 C-bus. The input frequency on two of the four muxes (mux C and D in Figure 2) can be changed without reprogramming on the SEL_CD pin through the logic level input.

3.3 Column divider

The post divider performs several useful functions. First, it allows the VCO to operate within a narrow range of speeds that the device needs to produce to produce changes in output clock speed. Second, it changes the basic PLL equation to where NF, NR, and NP are the feedback, reference, and post-division blocks, respectively, and fCLK and fREF are the output and reference frequency oscillators. The extra integer in the denominator makes loop programming more flexible for many applications where the frequency must be precisely reached. The modulo on two of the four post-divider muxes (post-dividers C and D in Figure 2) can be programmed without reprogramming by selecting the logic level on the CD pin.

4.0 Equipment Operation

The FS6377 is powered up with all internal registers cleared to zero, delivering the crystal frequency to all outputs. In order to operate, the registers must be loaded in Most Significant Bit (MSB) to Least Significant Bit (LSB) order. The register map of the FS6377 is shown in Table 3 and I2 C bus programming information is detailed in Section 5.0. The controls for the reference, feedback and post splitter are detailed in Table 5. Choosing these voltage dividers to directly control the speed of the VCO will run. The maximum VCO speed is recorded in Table 13.

4.1 Select CD input

The SEL_C D pin provides a means of changing the operation of PLL C, muxes C and D, and postscalers C and D without reprogramming. According to Table 3, a logic low on the SEL_CD pin selects the control bit with the "C1" or "D1" symbol. The logic of height selects control bits with "C2" or "D2" symbols according to Table 3. Note that using the SEL_CD pin to switch between the two operating frequencies may produce glitches in the output, especially if the postscaler is changed.

4.2 Power down and output enable

High logic on the PD pin enables only the partial power-down in the FS6377 with their respective power-down control bits. Note that the PD pin has an internal pull-up. When the post distributor is powered down, the associated output driver is forced down. The crystal oscillator is also powered down when all plls and post dividers are powered down. The heart pin is pushed low, while the XOUT pin is pulled high. A logic low on the OE pin tri-states all output clocks. Note that this pin has an internal pull-up.

4.3 Oscillator Overdrive

For applications that provide an external reference clock (which does not require a crystal oscillator), the reference clock should be left unconnected (floating) while connected to XOUT and XIN. For best results, make sure the reference clock signal is as jitter-free as possible, capable of driving a 40pF load with fast rise and fall times, and can swing side to side. If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01µF or 0.1µF capacitor. A minimum 1V peak-to-peak signal is required to drive the internal differential oscillator buffer. 5.0 Inch C-Bus Control Interface This device is a read/write slave device that meets all Philips I2 C-bus specifications except "General Call". The bus must be controlled. The master device that generates the serial clock SCL controls bus access and generates start and stop conditions, while this device acts like a slave. Both master and slave devices can work as transmitter or receiver, but the master device decides which mode is activated. A device that sends data onto the bus is defined as a transmitter, and a device that receives data is defined as a receiver.

The C-bus logic levels described herein are based on a percentage of the power supply (VDD). A logic 1 corresponds to VDD, while a logic zero corresponds to ground (VSS).

5.1 Bus Conditions Data transfers on the bus can only be initiated when the bus is not busy. During data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. When the clock line is high, changes on the data line will be interpreted by the device as a start or stop state. The following bus conditions are defined by the I2C bus protocol. 5.1.1. Both the not busy data line (SDA) and the clock line (SLC) are held high to indicate that the bus is not busy. 5.1.2. Beginning of data transfer When the SCL input is high, a high-to-low transition of the SDA line indicates a start condition. All commands to the device must precede the start condition. 5.1.3. Stopping Data Transfer A low-to-high transition of the SDA line while SCL is held high indicates a stop condition. All commands to the device must be followed by a stop state. 5.1.4. Data Valid If the SDA line remains stable during the high period of the SCL line after start-up, the state of the SDA line indicates that a valid data condition has occurred. The data on the SDA line can only change during the low period of the SCL signal. Each has one clock pulse data bit. Each data transfer is initiated by a START condition and terminated by a STOP condition. The condition between start and stop of the number of data bytes transferred is determined by the master and can continue indefinitely. However, data that is overwritten to the device after the first 16 bytes will overflow into the first register, then the second register, and so on.

5.1.5. Acknowledgment When addressing, the receiving device needs to generate an acknowledgment after each byte is received. The master must generate an additional clock pulse to coincide with the acknowledge bit. The acknowledgment device must be on the high cycle of the master acknowledgment clock pulse. Setup and hold times must be considered. The master must leave the slave by not generating an acknowledgment bit on the last read byte (by clock) to signal the end of data to the slave. In this case, the slave must hold the SDA line high for the master to generate a stop condition. 5.2 Two C-Bus Operation All programmable registers can be accessed randomly or sequentially through a bidirectional two-wire digital interface. The device accepts the following I2C bus commands. 5.2.1. Slave Address After generating the Start condition, the bus master broadcasts a 7-bit slave address followed by an R/W bit. The address of the device is:

where X is controlled by the logic level of the ADDR pin. The variable ADDR bit allows two different devices to exist on the same bus. Note that each device on the I2C bus must have a unique address to avoid bus collisions. The default address sets A2 to 1 via a pull-up on the ADDR pin. Section 5.2.2. Random Register Write Procedure The random write operation allows the host to write directly to any register. To initiate the write process, send the R/W bit followed by a logic low seven bits of the device address. This indicates to the addressed slave that the register address will be acknowledged by the slave at its device address. The register address is written to the address pointer of the slave. Following the slave acknowledgment allows the master to write eight bits of data to the address register. Returns the final acknowledgment that the stop condition is generated by the device and host. If a Stop or Repeated Start condition occurs during a register write, the transferred data is ignored. 5.2.3. Random Register Read Process The random read operation allows the host to directly read data from any register. To perform a read process, the R/W bit is transmitted logic low after the seven-bit address, as in a register write process. This indicates to the addressed slave that after the slave has confirmed its device address, the register address will follow. The register address is then written to the slave address pointer. After slave acknowledgment, the master generates a repeated START condition. Repeated starts terminate the write process, but not until the slave's address pointer is set. The slave address is then resent, this time with the R/W bit set to logic high, indicating to the slave that the data will be read. The slave will confirm the device address and then send 8 bits as a word. The host does not acknowledge the transfer, but does generate a stop condition. 5.2.4. Sequential Register Write Process Sequential write operations allow the host to write to each register in sequence. The register pointer is in each word. If multiple registers must be written, this process is more efficient than random register writes. To initiate the write process, the R/W bit sent after the seven-bit device address is logic low.