1.0 Main Features

A phase-locked loop (PLL) device synthesizes the output clock frequency from a crystal oscillator or external reference clock On-chip adjustable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning

Typically used to generate MPEG-2 decoder clocks

3.3V supply voltage

Very Low Phase Noise Phase Locked Loop

Use with "pullable" 14pF crystal - no external fill capacitor required

Small board footprint (8-pin 0.150" SOIC)

The FS6128 is a monolithic CMOS clock generator integrated circuit designed to minimize the cost and component count of digital circuits for video/audio systems. At the heart of the FS6128 is a circuit implemented by a Voltage Controlled Crystal Oscillator (VCXO) (nominal 13.5 MHz) connected when the external resonator is operating. The VCXO can precisely adjust the device frequency for use in systems with frequency matching requirements, such as digital satellite receivers. The high-resolution phase-locked loop generates the output clock (CLK) through a postscaler. The CLK frequency is scaled from the VCXO frequency. Locking the CLK frequency to other system reference frequencies eliminates artifacts in unpredictable video systems and reduces electromagnetic interference caused by frequency harmonic stacking.

Keys: AI=analog input; AO=analog output; DI=digital input; DIU=input with internal pull-up; DID=input with internal pull-down; DIO=digital input/output; DI-3=three-level digital input , DO=digital output; P=power/ground; #=active low pin

3.1 Voltage Controlled Crystal Oscillator (VCXO)

The VCXO provides a tunable, low-jitter frequency reference for other FS6128 system components. The load capacitor crystal is inside the FS6128. The operation of the VCXO requires no external components (other than the resonator itself). Continuous trimming of the VCXO frequency is accomplished by changing the voltage on the XTUNE pin. The value of this voltage controls the effective capacitance of the crystal. The actual amount of change in load capacitance that will change the oscillator frequency depends on the characteristics of the crystal as well as the oscillator circuit itself. It is important that the crystal load capacitance is properly specified to "center" the tuning range. See table.

Type FS6128-04

A simple formula for obtaining the "pull" capability of a crystal oscillator is:

C0 = shunt (or hold) capacitance of the crystal

C1 = motion capacitance of the crystal

CL1 and CL2 = the two extremes (minimum and maximum) of the load capacitance applied by the FS6128.

Example: Use a crystal with the following parameters: C1=0.025pF and C0=6pF. Using min and max CL1=10pF, CL2=20pF, the tuning range (peak-to-peak) is:

3.2 Phase-locked loop (PLL) The on-chip phase-locked loop is a standard frequency phase-locked loop structure. The PLL multiplies the reference oscillator frequency by the desired output frequency expressed as an integer ratio. Frequency multiplication is exact with zero synthesis error (unless otherwise specified).

4.0 Electrical Specifications

CAUTION: Stresses listed above Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress-only rating and the functional operation of the equipment at these or any other conditions above the operating limits stated in this specification is not meant to be. Exposure to extended conditions at maximum rating conditions may affect device performance, functionality, and reliability.

Caution: Static Sensitive Devices

Electrostatic discharge can cause permanent damage to function or performance if the device is subjected to high energy.

Table 5: DC Electrical Specifications

Note: Unless otherwise specified, for any output and ambient temperature range TA=0°C to 70°C, VDD=3.3V±10% no load. Parameters are marked with an asterisk (*) for nominal characteristic data and are not production tested to any specific limits. Among them, the minimum and maximum characteristic data are ±3σ of the typical value. Negative currents indicate current flow out of the device.

Table 6: AC Timing Specifications

Note: Unless otherwise specified, VDD=3.3V±10%, no load on any output, ambient temperature range TA=0°C to 70°C. Parameters are marked with an asterisk (*) for nominal characteristic data and are not production tested to any specific limits. Among them, the minimum and maximum characteristic data are ±3σ of the typical value.