feature

Serial I/O (microwire compatible); 2, 4, or 8-channel differential or single-ended multiplexer; analog input sample/hold function; power-down mode; variable resolution and conversion rate; programmable acquisition time ; Variable digital output word length and format; no zero-scale or full-scale adjustment required; fully tested and guaranteed with 4.096V reference voltage; 0V to 5V analog input range, single 5V power supply; no over-temperature lost codes supplied.

Main Specifications

Resolution 12-bit Plus; 12-bit Plus Conversion Time: - ADC12H030 Series 5.5 µs (max); - ADC12030 Series 8.8 µs (max); 12-bit Plus Throughput Time - ADC12H030 Series 8.6 µs ( max) - ADC12030 series 14 microseconds (max); integral linearity error ±1 LSB (max); single supply 5V ±10% n power consumption 33mW (max) - power down 100 microwatts (typ).

application

Medical devices; process control systems; test equipment.

General Instructions

ADC12030 and ADC12H030 series are successive approximation A/D converters and configurable input multiplexers with serial input and output of more than 12 bits. ADC12032/ADC12H032, ADC12034/ADC12H034 and ADC12038/ADC12H038 have 2, 4 and 8 multiplexers respectively. The differential multiplexer output and A/D input are provided on MUXOUT1, MUXOUT2, A/DIN1, and A/DIN2 pins. The ADC12030/ADC12H030 has a dual-channel multiplexer, and the multiplexer output is linked to the internal A/D input. The ADC12030 series is tested with a 5 MHz clock, while the ADC12H030 series is tested with an 8 MHz clock. On request, these A/Ds self-calibrate with linear, zero, and full-scale errors to less than ±1 LSB each. The analog inputs can be configured in various single-ended, differential or pseudo-differential modes. A fully differential unipolar analog circuit input range (0V to +5V) can be used with a +5V supply. In differential mode, even the negative input is larger than the output data format precisely because of the 12-bit plus sign. Serial I/O is configured to comply with NSC MICROWIRE 8482 ;. See the LM4040 or LM4041 for a voltage reference.

Program Tips

1.0 digital interface

1.1 Interface Concept

The example in Figure 7 shows a typical sequence of events after the ADC12030/2/4/8 is powered up:

Figure 7. Typical Power Supply Sequence

Auto-calibration is initiated by the first command of the DI input A/D. At that time, the data output on the DO was meaningless and completely random. The A/D will be sent to the A/D after it is determined whether the auto-calibration is complete. Also, the data output at the time is meaningless because the Auto-Cal process modifies the data in the output shift register. To retrieve status information, you also need to issue a read status command to the A/D. There is state data on DO at this time. Auto-calibration is complete if the calibration signal in the status word is low. So the next issued instruction can start the conversion. The data output at this time is again status information. Hold noise cannot read the state during conversion due to damage to the A/D conversion. If CS is brought down during a transition, the transition ends prematurely. The EOC can be used to determine the end of a conversion or the A/D controller can track in software when it is appropriate to communicate with the A/D again. Once it has determined that the A/D has completed the conversion, another command can be sent to the A/D. This converted data can be accessed when the next command is sent to the A/D.

Note that when CS is continuously low, the exact number of SCLK cycles is transmitted, as shown in the timing chart. Failure to do so will desynchronize the serial communication with the A/D (see Section 1.3).

1.2 Change configuration

The ADC12030/2/4/8 configuration at power-up defaults to 12-bit plus resolution, 12-bit or 13-bit MSB first, 10 CCLK acquisition time, user mode, no auto-calibration, no auto-zero, power-up mode. Changing the acquisition time and turning the sign bit on and off requires an 8-bit instruction to the ADC. This command does not initiate a conversion. Select the multiplexer address and format the output data to start the conversion. Figure 8 depicts the modification to the ADC12030/2/4/8.

During I/O Sequence 1, an instruction on DI configures the ADC12030/2/4/8 to convert at 12-bit + sign resolution. Note that when the 6 CCLK acquisition and data outputs are not issued a symbolic command to the ADC, I/O sequences 2 and 3, no new conversions will be initiated. The data output during these instructions comes from Conversion N initiated during I/O Sequence 1. The configuration modification timing diagram details the events required for data output without flag, with sign, or 6/10/18/34 CCLK acquisition timing mode selection. Table 5 describes the required input to the ADC to accomplish this configuration modification. This next instruction, shown in Figure 8, is sent to the A/D to initiate conversion N+1, first MSB in 8-bit resolution format. Again, the data output in this I/O cycle is from transition N.

The number of SCLKs applied to the A/D in any conversion I/O sequence should vary depending on the data output word format selected during the previous conversion I/O sequence. The various formats and resolutions available are shown in Table 1. In Figure 8, the number of SCLKs required during I/O Sequence 5 selected in I/O Sequence 4 is 8 because the 8-bit unsigned MSB is the first format. In the following I/O sequence, the format is changed to 12-bit, unsigned MSB first; therefore in I/O sequence 6 it is changed to 12 accordingly.

1.3 Continuous consideration of low CS

When CS is consistently low, transmit the exact number of SCLK pulses expected by the ADC. Not doing this will enable serial communication with the ADC. Expect to see 13 SCLK pulses per I/O transfer when power is first applied to the ADC. The ADC expects to see the same number of SCLK pulses as the digital output word length. The digital output word length is controlled by the data out (DO) format. This DO format may change at the start of the conversion or when the sign bit is turned on or off. The following table details the different DO formats:

If an erroneous SCLK pulse desynchronizes the communication, the easiest way to recover is to cycle power to the device. The inability to easily resync the device is a downside of keeping CS low.

When CS remains low continuity, the number of clock pulses required for an I/O exchange may be different - ly compared to the case when looping CS. Take the I/O sequence detailed in Figure 7 (Typical Power Sequence) as an example. The following table lists the number of SCLK pulses required for each instruction:

1.4 Analog input channel selection

The data input on DI also selects the channel configuration for a specific A/D conversion (see Tables 2, 3, 4 and 5). In Figure 8, the channel configuration can only be modified during I/O sequences 1, 4, 5, and 6. Input channels are reselected before each new conversion begins. The following is the data bit stream required for different versions of the ADC with CH1 set to positive input and CH0 set to negative input during I/O sequence number 4 in Figure 8:

where X can be logic high (H) or low (L).

1.5 Power on/off

The ADC can be powered down at any time by either the PD pin high or through a command input on DI (see Tables 5, 6 and power up/down timing diagrams). When the ADC is powered down in this way, the circuitry required for the A/D conversion is disabled. The circuitry required for the digital I/O remains active. Hardware power up/down is controlled by the state of the PD pin. Software power up/down is controlled by commands sent to the ADC. If a software power-up command is issued to the ADC while hardware power-down is in effect (PD pin high), the device will remain powered down. If a software power-down command is issued to the ADC while hardware power-up is in effect (PD pin low), the device will be powered down. When the device is powered down by software, it can be powered up by issuing a software power-up command or by pulling the PD pin high and then low. If a power down command is issued during an A/D conversion, the conversion will be interrupted. Therefore, the data output after power-up cannot be relied upon.

1.6 User Mode and Test Mode

The ADC can be commanded to enter test mode. Manufacturers use test patterns to verify the full functionality of the device. During test mode, CH0–CH7 become active outputs. Serial communications may become out of sync if the device is inadvertently put into test mode with CS continuously low. Synchronization can be restored by cycling the device's supply voltage. Cycling the supply voltage also sets the device to user mode. If CS is used in the serial interface, the ADC can be queried to see what mode it is in. This is done by issuing a "read status register" command to the ADC. When bit 9 of the status register is high, the ADC is in test mode; when bit 9 is low, the ADC is in user mode. As an alternative to cycling power, a sequence of instructions can be used to return the device to user mode. This command sequence must be sent to the ADC using CS. The following table lists the instructions required to return the device to user mode:

X = don't care

After returning to user mode using a user mode command, the power-on, signed or unsigned data and acquisition time commands need to be resent to ensure that the ADC is in the desired state before starting a conversion.

1.7 Reading data without initiating conversion

By ensuring that the CONV line is high during the I/O sequence, data from a specific conversion can be accessed without starting a new conversion. See the read data timing diagram. Table 6 describes the operation of the switch pins.

2.0 Analog Multiplexer Description

For the ADC12038, the analog input multiplexer can be configured with 4 differential channels or 8 single-ended channels with the COM input as the zero reference or any combination thereof (see Figure 9). The voltage difference on the VREF+ and VREF- pins determines the input voltage range (VREF). The analog input voltage range is 0 to VA+. When VIN->VIN+, a negative numeric output code is generated.

The actual voltage at VIN- or VIN+ cannot be lower than the active range.

CH0, CH2, CH4, and CH6 can be assigned to the OUT1 pins in a MUX-differential configuration, while CH1, CH3, CH5, and CH7 can be assigned to the MUXOUT2 pins. In a differential configuration, the analog inputs are paired as follows: CH0 and CH1, CH2 and CH3, CH4 and CH5, and CH6 and CH7. The A/DIN1 and A/DIN2 pins can be assigned positive and negative polarities.

For single-ended multiplexer configuration, CH0 to CH7 can be assigned to MUXOUT1 pins. The COM pin is always assigned to the MUXOUT2 pin. A/DIN1 is designated as the positive input; A/DIN2 is designated as the negative input. (See Figure 10).

The multiplexer assignment table for ADC12030, 2, 4, 8 (Tables 2, 3, 4) summarizes the above features of the different versions of the A/Ds.

2.1 Bias for Various Multiplexer Configurations

Figure 11 is an example of a biased single-ended operating device. The flag bit is always low. The digital output ranges from 0 0000 0000 to 0 1111 1111 1111. One LSB equals 1 mV (4.1V/ 4096 LSB).

For pseudo-differential symbol operation, the bias circuit shown in Figure 12 shows the signal AC coupled to the ADC. This makes the digital output range from -4096 to +4095. As shown, when the reference voltage is 2.5V, 1LSB equals 610 μV. Although the ADC is not production tested with a 2.5V reference, the linearity error typically does not vary by more than 0.1LSB (see the curves in the Typical Electrical Characteristics section). When the ADC is set to an acquisition time of 10 clock cycles, the input bias resistor needs to be less than or equal to 600Ω. Note though that the input coupling capacitor needs to be quite large to reduce the high pass angle. Increasing the acquisition time to 34 clock cycles (at 5mhz CCLK frequency) will allow the 600Ω to increase to 6k, while using a 1µF coupling capacitor sets the high pass angle to 26hz. Increasing R to 6k will allow R2 to be 2k.

Another way to bias pseudo-differential operation is to use the +2.5V bias from the LM4040 to drive any amplifier circuit of the ADC, as shown in Figure 13. The resistor pull-up bias value for the LM4040-2.5 will depend on the current required by the op amp bias circuit.

In the circuit of Figure 13, some voltage range is lost because the amplifier cannot swing to +5V and GND with a +5V supply. As shown in Figure 14, using the adjustable version of the LM4041 to precisely set the full-scale voltage to 2.048V, and using the lower-grade LM4040D-2.5 to bias all voltages to 2.5V, will allow the use of all the ADC's digital output ranges − 4096 to +4095 while leaving enough headroom for the amplifier.

Fully differential operation is shown in Figure 15. In this case, one LSB equals (4.1V/4096) = 1 mV.

3.0 Reference Voltage

The difference in the voltages applied to VREF+ and VREF defines the analog input span (the difference between the voltage applied between the two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground) value), where there are 4095 positive and 4096 negative codes. The voltage source driving VREF+ or VREF- must have very low output impedance and noise. The circuit in Figure 16 is an example of a very stable reference suitable for use with the device.

The ADC 12030/2/4/8 can be used for ratiometric measurements or absolute reference applications. In a ratiometric measurement system, the analog input voltage is proportional to the analog-to-digital converter reference voltage. When this voltage is the system power supply, the VREF+ pin is connected to VA+ and VREF- is connected to ground. This technique relaxes the system reference stability requirements as the analog input voltage and ADC reference voltage move simultaneously. This will maintain the same output code for a given input condition. For absolute accuracy, a time and temperature stable voltage source can be connected to the reference input when the analog input voltage varies between very specific voltage limits. Typically, the magnitude of the reference voltage requires an initial adjustment for the full-scale error due to a zero reference voltage.

Below are recommended references along with some key specifications.

The reference voltage input is not fully differential. If VREF+ is lower than VREF-, the ADC12030/2/4/8 will not generate correct conversions or comparisons. Correct transitions occur when VREF+ and VREF- are 1V apart and remain between ground and VA+ at all times. The VREF common mode range (VREF++VREF-)/2 is limited to (0.1 x VA+) to (0.6 x VA+). Therefore, when VA+=5V, the center of the reference ladder should not be lower than 0.5V or higher than 3.0V. Figure 17 is a graphical representation of the voltage limits VREF+ and VREF-.

4.0 Analog Input Voltage Range

The fully differential ADC of the ADC12030/2/4/8 produces a 2's complement output obtained by using the equation shown below: For (12-bit) resolution, the output code =

For (8-bit) resolution, output code =

If the result of the above formula is not an integer, it is rounded to the nearest integer value between -4096 and 4095 for 12-bit resolution and -256 to 255 for 8-bit resolution.

Examples are shown in the following table:

5.0 Input Current

At the beginning of the acquisition window (tA), depending on the input voltage polarity, charging current flows into or out of the analog input pins (a/DIN1 and a/DIN2). When A/DIN1 is tied to MUXOUT1 and A/DIN2 is tied to MUXOUT2, the analog input pins are CH0–CH7 and COM. The peak value of this input current will depend on the actual input voltage, source impedance, and internal multiplexer on-resistance. MUXOUT1 is connected to A/DIN1 and MUXOUT2 is connected to A/DIN2, and the on-resistance of the internal multiplexer is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux on-resistance is typically 750 Ω.

6.0 Input Source Resistance

For low-impedance voltage sources (<600Ω), the input charging current will decay to a value that does not introduce any conversion error before the end of the S/H acquisition time of 2 μs (10 CCLK cycles, fC = 5mhz). For high source impedance, the capture time of S/H can be increased to 18 or 34 CCLK cycles. For lower ADC resolution and/or slower CCLK frequency, the capture time of S/H can be reduced to 6 CCLK cycles. To determine the number of clock cycles (Nc) required for acquisition time with a specific source impedance at different resolutions, the following equation can be used:

where fC is the conversion clock (CCLK) frequency in MHz and RS is the external source resistance in kΩ. As an example, with a resolution of 12 bits+sign, a clock frequency of 5 MHz, and a maximum conversion time of 34 conversion clock cycles, the analog input to the ADC can handle source impedances up to 6 K. The acquisition time can also be extended to compensate for the settling or response time of external circuits connected between the MUXOUT and A/DIN pins.

The acquisition time tA begins with the falling edge of SCLK and ends with the rising edge of CCLK (see timing diagram). If SCLK and CCLK are asynchronous, an extra CCLK clock cycle can be inserted into the programmed synchronous capture time. Therefore, for asynchronous SCLKs and CCLKs, the acquisition time will change from transition to transition.

7.0 Input Bypass Capacitor

External capacitors (0.01µF–0.1µF) can be connected between the analog input pins CH0–CH7 and analog ground to filter any noise caused by inductive pickup associated with long input leads. These capacitors do not degrade conversion accuracy.

8.0 Noise

The traces for each analog multiplexer input pin should be as short as possible. This will minimize input noise and clock frequency coupling, which can lead to conversion errors. Input filtering can be used to reduce the effects of noise sources.

9.0 Power

Noise spikes on the VA+ and VD+ supply lines can cause conversion errors; the comparator will respond to the noise. ADCs are particularly sensitive to any power supply spikes that occur during auto-zero or linearity correction. The recommended minimum supply bypass capacitor is a 10µF or larger low inductance tantalum capacitor in parallel with a 0.1µF monolithic ceramic capacitor. Depending on the overall system requirements, more or different bypasses may be required. Separate bypass capacitors should be used for the VA+ and VD+ supplies and placed as close to these pins as possible.

10.0 Ground

With proper grounding techniques, the performance of the ADC120 30/2/4/8 can be maximized. This includes the use of separate analog and digital grounds. The digital ground plane is placed under all components that process digital signals, while the analog ground plane is placed under all components that handle analog signals. The digital and analog ground planes are connected together at only one point, the power ground or the pins of the ADC. This greatly reduces the occurrence of ground loops and noise.

Figure 18 shows the ideal ground plane layout for the ADC12038 and the ideal layout for the bypass capacitors. The board layout shown in Figure 18 uses three bypass capacitors: 0.01µF (C1) and 0.1µF (C2) surface mount capacitors and 10µF (C3) tantalum capacitors.

11.0 Clock Signal Line Isolation

The performance of the ADC12030/2/4/8 is optimized by routing the analog input/output and reference signal conductors as far as possible from the conductors carrying the clock signal to the CCLK and SCLK pins. A ground trace parallel to the clock signal trace can be used on the printed circuit board to reduce clock signal interference on the analog input/output pins.

12.0 Calibration Cycle

After the power supply, reference and clock are given enough time to stabilize after the initial turn-on, the calibration cycle needs to begin. During the calibration cycle, the offset voltage of the sampled data comparator and correction values for any linearity and gain errors are determined. These values are stored in internal RAM and used during analog-to-digital conversions to reduce overall full-scale, offset, and linearity errors to specified limits. Full-scale error typically varies by ±0.4lsb with temperature, and linearity error varies less; therefore, if supply voltage and ambient temperature do not change significantly (see curves in Typical Performance Characteristics), only one calibration cycle is required after power-up.

13.0 Auto-Zero Cycle

To correct for any changes in the A/D's zero (offset) error, an auto-zero cycle can be used. An auto-zero cycle may be required when the ambient temperature or supply voltage varies significantly. (See the curves titled "Zero Error Variation vs. Ambient Temperature" and "Zero Error Variation vs. Supply Voltage" in Typical Performance Characteristics.)

14.0 Dynamic Performance

Many applications require A/D converters to digitize AC signals, but standard DC integral and differential nonlinear specifications cannot accurately predict A/D converter performance with AC input signals. An important specification for AC applications reflects the converter's ability to digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic characteristics, such as signal-to-noise ratio (S/N), signal-to-noise ratio + distortion ratio (S/(N+D)), effective number of bits, full power bandwidth, aperture time and aperture jitter, etc., are a measure of A/D conversion Quantitative indicators of device performance.

The AC performance of an A/D converter can be measured using the Fast Fourier Transform (FFT) method. A sinusoidal waveform is applied to the input of the A/D converter, and the digitized waveform is transformed. Calculate S/(N+D) and S/N from the obtained FFT data, and also get the spectrogram. The typical value of S/N is shown in the electrical characteristics table, and the spectrum diagram of S/(N+D) is shown in the typical performance curve.

The noise and distortion levels of an A/D converter will vary with the frequency of the input signal, with more distortion and noise appearing at higher signal frequencies. This can be seen in the S/(N+D) vs frequency plot. These curves will also indicate the full power bandwidth (S/(N+D) or the frequency at which S/N drops by 3db).

The effective number of bits can also be used to describe the noise performance of the A/D. An ideal A/D converter will have some amount of quantization noise, determined by its resolution, that will yield the best signal-to-noise ratio given by the equation:

S/N=(6.02 x N+1.76)dB, where N is the resolution of the A/D in bits.

Therefore, the significant bits of the actual A/D converter can be found by:

As an example, this device with a differentially signed 5V, 10khz sine wave input signal typically has an S/N of 78db, which equates to 12.6 significant bits.

15.0 RS232 Serial Interface

IBM and PC compatible RS232 interface schematic CTS RS232 signal lines are buffered by level shifters and connected to the DI, SCLK and DO pins of the ADC12038, respectively. The D flip-flop drives the CS control line.

Note: V, V and Von ADC12038 have 0.01 and 0.1 μF chip caps, and 10 μF tantalum caps. All logic devices are bypassed with 0.1µF capacitors. a+ding+referee+

The assignment of the RS232 ports is as follows:

The next page shows a sample program written in Microsoft QuickBasic. The program prompts to send a data mode selection command to the A/D. This can be found from the pattern programming table shown earlier. Data should be entered with "1" and "0" as shown in the table, with DI0 first. Next, the program prompts for the number of SCLKs required for the programming mode selection command. For example, to send all '0's to the A/D, select CH0 as + input, CH1 as - input, select 12-bit conversion, select 13-bit MSB first data output format (if the sign bit was not turned off by the previous instruction ). This will take 13 SCLK cycles because the output data format is 13 bits. No auto-calibration, no auto-zero, 10 CCLK acquisition time, 12-bit conversion, signed data output, power-up, 12- or 13-bit MSB first, and user mode on part power-up. Auto-calibration, auto-zero, power-up, and power-down commands do not change these default settings. The following power-up sequence should be followed:

1. Run the program;

2. Apply power to ADC12038 before responding to the prompt;

3. In response to the program prompts, it is suggested that the first command issued to the ADC12038 is automatic calibration (see Section 1.1).

Physical dimensions in inches (mm) unless otherwise noted.