Power sequencing is an important aspect to consider when designing with field programmable gate arrays (FPGAs). Typically, FPGA vendors specify power sequencing requirements, as the number of power rails required for an FPGA can vary from 3 to more than 10.

By following the recommended power supply sequence, you can avoid drawing excessive current during startup, which in turn prevents damage to the device. Sequencing the power supplies in a system can be done in a number of ways. This article will detail power sequencing solutions that can be implemented depending on the complexity required by the system.

The power sequencing solutions discussed in this article are:

1. Cascade the PGOOD pin to the enable pin;

2. Use a reset IC to achieve sequencing;

3. Simulate power-on/power-off sequencer;

4. Digital system health monitor with PMBus interface.

Method 1: Cascade the PGOOD pin to the enable pin

A basic cost-effective way to implement sequencing is to cascade the power good (PG) pin of one power supply to the enable (EN) pin of the next power supply in succession.

The second supply starts when the PG threshold is met (usually when the supply reaches 90% of its final value). The advantage of this approach is low cost, but the timing cannot be easily controlled. Adding a capacitor to the EN pin introduces timing delays between circuit stages. However, this method is unreliable during temperature changes and repeated power cycling. Also, this method does not support power-down sequencing.

Method 2: Use a reset IC for sequencing

Another simple option to consider for power-up sequencing is to use a reset IC with a time delay. When this option is used, the reset IC monitors the power rails with tight threshold limits. Once a rail is within 3% (or less) of its final value, the reset IC enters a solution-defined wait period before powering up the next rail. This wait period can be programmed into the reset IC using EEPROM or programmed with an external capacitor. Figure 2 shows a typical multi-channel reset IC. The advantage of using a reset IC for power-up sequencing is that the solution is in a monitored state.

Each rail must be confirmed to be within regulation before releasing the next rail, and there is no need to provide a PGOOD pin on the power converter. The disadvantage of power sequencing solutions using reset ICs is that they do not implement power down sequencing.

Method 3: Simulate a power-up/power-down sequencer

Implementing power-up sequencing is easier than implementing power-down sequencing. To achieve power-up and power-down sequencing, simple analog sequencers have been introduced that can reverse the power-down sequence (Sequence 1) or even mix (Sequence 2) with respect to the power-up sequence.

At power-up, all flags are held low until EN is pulled high. After EN is asserted, each flag sequentially goes to an open-drain state (requires a pull-up resistor) after an internal timer expires. The power-down sequence is the same as the power-up sequence, but in reverse order.

Cascading Multiple Sorters

Sequencers can be cascaded together to support multiple power rails and provide fixed and adjustable delay times between enable signals. In Figure 4, two sequencers are cascaded together to achieve 6 ordered power rails. On power-up, the AND gate ensures that the second sequencer is not triggered until it receives an EN signal and the C rail is triggered.

When powered down, the AND gate ensures that the second sequencer survives falling EN edges regardless of the C output. The OR gate ensures that the first sequencer is triggered by the rising edge of EN. When powered down, the OR gate ensures that the first sequencer cannot tolerate falling EN edges until the D rail has fallen. This guarantees power-up and power-down sequencing, but does not provide a monitored sequence.

Monitored power-up/power-down sequencing

As shown in Figure 5, a monitored sequencing function can be added to the circuit in Figure 4 by simply adding a few AND gates between the FlagX output and the PG pin. In this example, PS2 is only enabled if PS1 exceeds 90% of its final value. This approach provides a low-cost, monitored sequencing solution.

Method Four: Digital System Health Monitor with PMBus Interface

If the system requires maximum flexibility, a PMBus/I2C compliant digital system health monitor such as the UCD90120A is a good solution. Such solutions provide maximum control for any sequencing need by allowing designers to configure power supply ramp up/down times, turn-on/turn-off delays, sequence dependencies, and even voltage and current monitoring.

The digital system health monitor features a graphical user interface (GUI) that can be used to set power-up and power-down sequencing and other system parameters (Figure 6). In addition, some digital system health monitors feature non-volatile error and peak logging capabilities to aid in system failure analysis in the event of an undervoltage event.

Examples of FPGA Sequencing Requirements FPGA vendors such as Xilinx or Altera provide recommended or required power-up sequences in their product manuals, which are readily available online. Sequencing requirements vary between vendors and between different FPGA families from the same vendor.

In addition, timing requirements for power supply ramp-up and shutdown are listed in the data sheet. The recommended power-down sequence is usually the reverse of the power-up sequence. Figure 7 shows an example of power-up sequencing.

in conclusion

Various power sequencing solutions are available to meet the requirements specified by the FPGA vendor. In addition to power-up and power-down sequencing, system requirements may include power monitoring, but the optimal power solution for an FPGA will depend on the complexity and specification of the system.