Gamma Correction

[24 hours-37 hours for HD, 66 hours-79 hours for SD] Gamma correction is available for SD and HD video. For each standard, there are 20 8-bit wide registers. They are used to program gamma correction curves A and B. HD Gamma Curve A is programmed at addresses 24h to 2Dh and HD Gamma Curve B is programmed at addresses 2h to 7h. SD gamma curve A is programmed at addresses 66h to 6Fh and SD gamma curve B is programmed at addresses 70h to 79h.

Typically gamma correction is used to compensate for the non-linear relationship between signal input and luminance level output (as seen on cathode ray tubes). It can also be applied anywhere nonlinear processing.

Gamma correction uses the function:

where = gamma power factor.

Gamma correction is only performed on luma data. The user can select either of two different curves, curve A or curve B. Only one of the curves can be used at any one time.

The response of the curve is programmed in 10 predefined positions. When changing the values at these locations, the gamma curve can be modified. Between these points, use linear interpolation to generate intermediate values. Considering that the total length of the curve is 256 points, the 10 positions are located at 24, 32, 48, 64, 80, 96, 128 , 160, 192, and 224, respectively. Positions 0, 16, 240 and 255 are fixed and cannot be changed.

For lengths from 16 to 240, the gamma correction curve is calculated as follows:

Where: y = gamma correction output; x = linear input signal = gamma power factor; to program the gamma correction register, y must be calculated using the following formula:

where: x(n-16) = the value of x at the point along the x axis; n = 24, 32, 48, 64, 80, 96, 128, 160, 192 or 224; yn = the value of y along the y axis, the Value must be written.

Gamma Correction Register

E.g:

*Round to the nearest whole number

The gamma curves in Figures 46 and 47 are examples only; any user-defined curve between 16 and 240 is acceptable.

HD Definition Filter Control and Adaptive Filter Control [subaddress 20h, 38h–3Dh]

There are three filtering modes on the ADV7310 /ADV7311: a sharpness filtering mode and two adaptive filtering modes.

HD Definition Filter Mode

To boost or attenuate the Y signal in the frequency range shown below, the following register settings must be used: HD sharpness filter must be enabled, and HD adaptive filter enable must be set to disabled.

To select one of the 256 individual responses, the corresponding gain value for each filter (ranging from -8 to +7) must be programmed into the HD Definition Filter Gain Register at address 20h.

HD adaptive filter mode

HD Adaptive Filter Threshold A, B, C registers, HD Adaptive Filter Gain 1, 2, 3 registers and HD Sharpness Gain registers are used in Adaptive Filter mode. To activate Adaptive Filter Control, HD Sharpness Filter must be enabled, and HD Adaptive Filter must be enabled.

The derivative of the input signal is compared to three programmable thresholds: HD adaptive filter thresholds A, B, C. Although any value in the range 0 to 255 can be used, the recommended threshold range is 16 to 235.

Edges can then be attenuated using the settings in the HD Adaptive Filter Gain 1, 2, 3 registers and the HD Sharpness Filter Gain register.

Depending on the setting of the HD Adaptive Filter Mode Control, two adaptive filter modes are available:

1. When the adaptive filter mode is set to 0, mode A is used. In this case, Filter B (LPF) will be used for the adaptive filter block. Also, only the programmed values of Gain B in HD Sharpness Filter Gain, HD Adaptive Filter Gain 1, 2, 3 are applied when needed. The gain A value is fixed and cannot be changed.

2. When the adaptive filter mode is set to 1, mode B is used. In this mode, a cascade of filter a and filter B is used. When required, the settings of HD Sharpness Filter Gain, Gain A and Gain B in HD Adaptive Filter Gain 1, 2, and 3 all become active.

The effects of the sharpness filter can also be seen when the application of the HD sharpness filter and the adaptive filter is used.

Cross hatch pattern generated inside the instance.

Adaptive Filter Control Application

Figures 45 and 46 show typical signals to be processed by the adaptive filter control block.

The following register settings are used to achieve the result shown in Figure 46, that is, to remove the ringing on the Y signal.

Input data is generated by an external signal source.

Adaptive filter control can also be demonstrated using an internally generated cross-hatched test pattern and toggling the adaptive filter control bits [Address 15h, Bit 7].

SD digital noise reduction [subaddress 63h, 64h, 65h]

DNR only applies to Y data. The filter block selects the high frequency, low amplitude components of the input signal [DNR input select]. Compare the absolute value of the filter output with a programmable threshold [DNR Threshold Control]. There are two DNR modes available: DNR Mode and DNR Sharpness Mode.

In DNR mode, if the absolute value of the filter output is less than the threshold, it is assumed to be noise. A programmable amount [coring gain bounds, coring gain data] that will subtract this noise signal from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, noise is assumed, as before. Otherwise, if the level exceeds the threshold (which is now recognized as a valid signal), a portion of the signal [coring gain boundary, core gain data] will be added to the original signal to enhance high frequency components and sharpen the video image.

In the MPEG system, the video information of the MPEG2 system is usually processed in blocks of 8 pixels×8 pixels, or the video information of the MPEG1 system is processed in blocks of 16 pixels×16 pixels [block size control]. DNR can be applied to block transition regions known to contain noise. Typically, the block transition area contains two pixels. This area can be defined as containing four pixels [boundary area].

[DNR block offset] can also be used to compensate for differences in variable block positioning or YCrCb pixel timing.

The digital noise reduction registers are three 8-bit registers. They are used to control DNR processing.

Coring Gain Boundary [Address 63h, Bits 3–0]

These four bits are assigned to the gain factor applied to the border region.

In DNR mode, the gain value ranges from 0 to 1 in 1/8 increments. This factor is applied to the DNR filter output that is below the set threshold range. Then subtract the result from the original signal.

In DNR sharpness mode, the gain value ranges from 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which is above the threshold range.

The result will be added to the original signal.

Core Gain Data [Address 63h, Bits 7–4]

These four bits are assigned to the gain factor applied to the luma data within the MPEG pixel block.

In DNR mode, the gain value ranges from 0 to 1 in 1/8 increments. This factor is applied to the DNR filter output that is below the set threshold range. Then subtract the result from the original signal.

In DNR sharpness mode, the gain value ranges from 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which is above the threshold range.

The result will be added to the original signal.

DNR Threshold [Address 64h, Bits 5–0]

These 6 bits are used to define a threshold in the range 0 to 63. Ranges are absolute values.

Frontier Area [Address 64h, Bit 6]

When this bit is set to logic 1, the block transition area can be defined as consisting of four pixels. If this bit is set to logic 0, the boundary transition region consists of two pixels, one of which represents two clock cycles at 27MHz.

Block Size Control [Address 64h, Bit 7]

This bit is used to select the size of the data block to be processed. Setting the block size control function to logic 1 defines a 16 pixel by 16 pixel data block, and a logic 0 defines an 8 pixel by 8 pixel data block, where one pixel represents two clock cycles at 27MHz.

DNR Input Select Control [Address 65h, Bits 2–0]

Three bits are assigned to select the filter, which is applied to the incoming Y data. The signal in the selected filter passband is the signal to be DNR processed. Figure 51 shows the filter responses that can be selected using this control.

DNR Mode Control [Address 65h, Bit 4]

This bit controls the selected DNR mode. Logic 0 selects DNR mode; logic 1 selects DNR sharpness mode.

DNR works by defining a low-amplitude, high-frequency signal as possible noise and subtracting that noise from the original signal.

In DNR mode, a portion of the signal below a set threshold (assumed to be noise) can be subtracted from the original signal. The threshold is set in DNR register 1.

When DNR sharpness mode is enabled, a portion of the signal above the set threshold can be added to the original signal, as this data is assumed to be valid data and not noise. The overall effect is that the signal will be boosted (similar to using an extended SSAF filter).

Block Offset Control [Address 65h, Bits 7–4]

Four bits are allocated to this control, which allows shifting of blocks of data of up to 15 pixels. Consider the coring gain position fixed. The block offset shifts the data in steps of one pixel so that the boundary core gain factor can be applied at the same location regardless of changes in the input timing of the data.

SD Active Video Edge [Subaddress 42h, Bit 7]

When activating video edges, the first and last three pixels of the active video on the LUMA channel are scaled in such a way that maximum transitions on these pixels are not possible. The scale factors are ×1/8, ×1/2, and ×7/8.

All other event videos are unprocessed.

SAV/EAV step edge control

The ADV7310/ADV7311 can control fast rising and falling signals at the beginning and end of active video to minimize ringing.

An algorithm monitors SAV and EAV and takes control if the edge is too fast. The result will be reduced ringtones at the beginning and end of the active video for fast transitions. Subaddress 0x42, bit 7=1 enables this feature.

Board Design and Layout Considerations

DAC Termination and Layout Considerations

The ADV7310/ADV7311 contain an on-board voltage reference. The ADV7310/ADV7311 can be used with an external VREF (AD1580).

The RSET resistor, connected between the RSET pin and AGND, controls the full-scale output current and thus the DAC voltage output level. For full-scale output, the value of RSET must be 3040Ω. The RSET value should not be changed. The full-scale output value of RLOAD is 300Ω.

Video output buffers and optional output filters To drive output devices such as SD or HD monitors, output buffering on all six DACs is necessary. Analog Devices produces a range of op amps suitable for this application, such as the AD8061. For more information on the line driver buffer circuit, see the relevant op amp datasheet.

If the ADV7310/ADV7311 are connected to a device that requires this filtering, an optional analog reconstruction low-pass filter (LPF) may be required as an inverse imaging filter.

Filter specifications vary by application.

PCB board layout considerations

The ADV7310/ADV7311 are optimized for the lowest noise performance in terms of both radiated and conducted noise. To complement the excellent noise performance of the ADV7310/ADV7311, great care must be taken with the PC board layout.

The layout should be optimized to minimize noise on the ADV7310/ADV7311 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. Lead lengths between VAA and AGND, VDD and DGND, and VDD-IO and GND-IO pin groups should be kept as short as possible to minimize induced ringing.

A 4-layer printed circuit board is recommended, with power and ground planes separating the signal transmission layers from the component and solder side layers. To separate noisy circuits, such as crystal clocks, high-speed logic circuits, and analog circuits, careful consideration should be given to component placement. There should be a separate analog ground plane and a separate digital ground plane.

Power planes should include digital power planes and analog power planes. The analog power plane should contain the DAC and all associated circuitry, VREF circuitry. The digital power plane should contain all logic circuits.

The analog and digital power planes should be individually connected to the common power plane at a single point with appropriate filtering means such as ferrite beads.

The DAC output traces on the PCB should be considered transmission lines. It is recommended to place the DAC as close to the output connectors as possible, with the analog output traces as short as possible (less than 3 inches). The DAC termination resistor should be as close as possible to the DAC output and should cover the ground plane of the PCB. In addition to minimizing reflections, short analog output traces will reduce noise pickup due to adjacent digital circuits.

To avoid crosstalk between the DAC outputs, it is recommended to leave as much space as possible between the tracks of the individual DAC output pins. It is also recommended to add ground trajectories between outputs.

Power decoupling

Noise on the analog power planes can be further reduced by using decoupling capacitors.

By using 10nF and 0.1 ceramic capacitors. Each group of VAA, VDD, or VDD-IO pins should be separated from ground individually. This should be achieved by placing the capacitors as close as possible to the device and keeping the capacitor leads as short as possible to minimize lead inductance. In addition to the 10nF ceramic, a 1µF tantalum capacitor is recommended in the VAA supply.

See the circuit layout in Figure 61.

digital signal interconnection

Digital signal lines should be isolated as much as possible from analog outputs and other analog circuits. Digital signal lines should not overlap analog power planes.

Due to the high clock frequencies used, long clock lines to the ADV7310/ADV7311 should be avoided to minimize noise pickup.

Any active pull-up termination resistors for digital inputs should be connected to the digital power plane, not the analog power plane.

Analog Signal Interconnect

The ADV7310/ADV7311 should be placed as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatches.

For best performance, the analog outputs should be source and load, respectively, as shown in Figure 61. Termination resistors should be placed as close as possible to the ADV7310/ADV7311 to minimize reflections.

For best performance, it is recommended that all decoupling and external components associated with the ADV7310/ADV7311 be located on the same side of the PCB, as close to the ADV7310/ADV7311 as possible. Any unused inputs should be grounded.

Appendix 1 - Copy Generation Management System PS CGMS Data Registers 2–0 [Subaddresses 21h, 22h, 23h]

PS CGMS can be used in 525p mode, compliant with CGMS-A EIA-J CPR1204-1, Method of Transmission of Video ID Information Using Vertical Blanking Intervals (525p Systems), March 1998, and IEC61880, 1998, Video Systems (525 /60) - Video and accompanying data for analog interface using vertical blanking interval.

When PS CGMS is enabled [subaddress 12h, bit 6=1], CGMS data is inserted into row 41. The PS CGMS data registers are located at addresses 21h, 22h and 23h.

SD CGMS Data Registers 2–0 [Subaddresses 59h, 5Ah, 5Bh]

The ADV7310/ADV7311 support a standards-compliant copy generation management system (CGMS). CGMS data is transmitted on line 20 of the odd field and line 283 of the even field. Bits C/W05 and C/W06 control whether CGMS data is output on the parity field. CGMS data can only be transmitted when the ADV7310/ADV7311 is configured in NTSC mode. The CGMS data is 20 bits long, and the function of each bit is shown in the table below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as the CGMS bits; see Figure 63.

HD/PS CGMS [Address 12h, Bit 6]

The ADV7310/ADV7311 supports Copy Generation Management System (CGMS) in HDTV mode (720p and 1080i) per EIAJ CPR-1204-2.

The HD CGMS data registers are located at addresses 021h, 22h, 23h.

Function of the CGMS bit

Word 0–6 bits; Word 1–4 bits; Word 2–6 bits; CRC 6-bit CRC polynomial = x6+x+1 (default 111111).

720p system

Apply CGMS data to line 24 of the luminance vertical blanking interval.

1080i system

CGMS data is applied to lines 19 and 582 of the luminance vertical blanking interval.

CGMS function

If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC [Subaddress 12h, Bit 7] is set to logic 1, the last 6 bits C19–C14 (forming the 6-bit CRC check sequence) are based on the data in the data register The lower 14 bits of (C0–C13) are automatically calculated on the ADV7310/ADV7311 and output with the remaining 14 bits to form the full 20 bits of CGMS data. The calculation of the CRC sequence is based on the polynomial x6+x+1 with a preset value of 111111. If SD CGMS CRC [Address 59h, Bit 4] and PS/HD CGMS, CRC [Address 12h, Bit 7] are set to logic 0, all 20 bits (C0–C19) are output directly from the CGMS register (CRC is not calculated, must be set by user calculation).

Appendix 2 - SD Widescreen Signals [Subaddresses 59h, 5Ah, 5Bh]

The ADV7310/ADV7311 support standards-compliant widescreen signaling (WSS). WSS data is transmitted on line 23. WSS data can only be transmitted when the device is configured in PAL mode. The WSS data is 14 bits long, and the function of each bit is shown in Table XIX. The WSS data is preceded by a run sequence and a start code; see Figure 66. If SD WSS [Address 59h, Bit 7] is set to logic 1, WSS data to be transmitted on line 23 is enabled. The latter part of line 23 (42.5µs from the falling edge of HSYNC) can be used to interpolate video.

The WSS portion of line 23 can be left blank with bit 7 of subaddress 61h.

Appendix 3 - SD Closed Captioning [Subaddresses 51h–54h]

The ADV7310/ADV7311 support closed captioning that conforms to standard TV sync waveforms for color transmission. Closed captioning is transmitted during the blanking active line time of the odd field of the even field and line 21 of line 284.

Closed captioning consists of a 7-cycle sinusoidal pulse, frequency and phase locked to the caption data. After the clock run signal, the blanking level for two data bits is maintained, followed by a logic 1 start bit. 16 bits of data follow the start bit. They consist of two 8-bit bytes, seven data bits and a parity bit. The data for these bytes is stored in the SD closed captioning registers [addresses 53h–54h].

The ADV7310/ADV7311 also support extended closed captioning operation, which is activated during even fields and encoded on scanline 284. The data for this operation is stored in the SD closed captioning registers [addresses 51h–52h].

The ADV7310/ADV7311 automatically generate all clock run signals and timings that support closed captioning on lines 21 and 284. If closed captioning is enabled, all pixel inputs are ignored during lines 21 and 284.

FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe closed captioning information on lines 21 and 284.

The ADV7310/ADV7311 use a single buffer method. This means that the closed captioning buffer is only 1 byte deep; so unlike other 2 byte deep buffer systems, there is no frame delay when outputting closed captioning data. Data must be loaded one line before (line 20 or 283) output to lines 21 and 284. A typical implementation of this method is to use VSYNC to interrupt the microprocessor, which will sequentially load the new data (two bytes) in each field. If the transfer does not require new data, 0s must be inserted in both data registers; this is called a null. It's also important to load the control codes, all of which are double bytes on line 21, otherwise the TV won't recognize them. If a message like "Hello World" contains an odd number of characters, it must be padded to an even number so that the 2-byte control code for "End Caption" falls in the same field.

Appendix 4 - Test Mode

The ADV7310/ADV7311 can generate SD and HD test patterns.

Appendix 5 - SD Timing Modes

[Subaddress 4Ah] Mode 0 (CCIR-656) - Slave Option (Timing Register 0 TR0 = XXXX 0 0 0) ADV7310/ADV7311 are controlled by SAV (Start Active Video) and EAV (End Active Video) timecodes in pixel data . All timing information is sent using 4-byte sync mode. During active frames and retraces, a sync pattern is sent immediately before and after each line. In this mode, the S_VSYNC, S_HSYNC, and S_BLANK (if not used) pins should be tied tightly. Blank output is available.

Mode 0 (CCIR-656) - Main Option (Timing Register 0 TR0 = XXXX 0 1)

The ADV7310/ADV7311 generate the H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video) timecodes in the CCIR656 standard. The H bit is output on S_HSYNC, the V bit is output on S_BLANK, and the F bit is output on S_VSYNC.

Mode 1 - Slave Option (Timer Register 0 TR0=XXXXX 0)

In this mode, the ADV7310/ADV7311 accept horizontal sync and parity field signals. When HSYNC is low, the transition of the field input represents a new frame, i.e. vertical retrace. Blank signals are optional. When blank input is disabled, the ADV7310/ADV7311 automatically blanks all normal blank lines according to CCIR-624. HSYNC is entered on S_HSYNC, blank on S_BLANK and field on S_VSYNC.

Mode 1 - main option (timer register 0 TR0=XXXX 0 1 1)

In this mode, the ADV7310/ADV7311 can generate horizontal sync and parity field signals. When HSYNC is low, the transition of the field input represents a new frame, i.e. vertical retrace. Blank signals are optional. When blank input is disabled, the ADV7310/ADV7311 automatically blanks all normal blank lines according to CCIR-624. Pixel data locked on rising clock

The transitioned edge of the timing signal. HSYNC is output on S_HSYNC, blank on S_BLANK, and fields on S_VSYNC.

Mode 2 - Slave Option (Timing Register 0 TR0=XXXX 1 0 0)

In this mode, the ADV7310/ADV7311 accept horizontal and vertical sync signals. Simultaneous low transitions of the HSYNC and VSYNC inputs indicate the start of an odd field. When HSYNC is high, a VSYNC low transition indicates the start of an even field. Blank signals are optional. When blank input is disabled, the ADV7310/ADV7311 automatically blanks all normal blank lines according to CCIR-624. HSYNC is the input S_HSYNC, BLANK on S_BLANK, and VSYNC on S_VSYNC.

Mode 2 - main option (timer register 0 TR0=XXXX 1 0 1)

In this mode, the ADV7310/ADV7311 can generate horizontal and vertical sync signals. Simultaneous low transitions of the HSYNC and VSYNC inputs indicate the start of an odd field. When HSYNC is high, a VSYNC low transition indicates the start of an even field. Blank signals are optional. When blank input is disabled, the ADV7310/ADV7311 automatically blanks all normal blank lines according to CCIR-624. HSYNC is output on S_HSYNC, BLANK on S_BLANK, and VSYNC on S_VSYNC.

Mode 3 - Master/Slave Option

(Timing Register 0 TR0 = XXXXX 11 0 or XXXX 1 1 1 1) In this mode, the ADV7310/ADV7311 accept or generate horizontal sync and parity field signals. When HSYNC is high, the transition of the field input represents a new frame, i.e. vertical retrace. Blank signals are optional. When blank input is disabled, the ADV7310/ADV7311 automatically blanks all normal blank lines according to CCIR-624. HSYNC is output in master mode, input on S_VSYNC, input on S_BLANK, and input on S_VSYNC.

Dimensions