feature

High Definition Input Formats 8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) Parallel YCrCb: Compliant: Skimmed Milk Powder 293M (525p) BTA T-1004 EDTV2 (525p); ITU-R BT. 1358 (625p/525p); ITU-R BT.1362 (625p/525p); SMPTE274M (1080i) at 30Hz and 25Hz; Skimmed Milk Powder 296M (720p); 310-bit 4: RGB in 4:4 input format; HDTV RGB supported: RGB, RGBHV; other high-definition formats using asynchronous; timing mode; high-definition output format; YPrPb progressive scan (EIA-770.1, EIA-770.2); YPrPb HDTV (EIA 770.3); RGB, RGBHV; CGMS-A (720p/1080i); Macrovision Version 1.1 (525p/625p) *CGMS-A (525p); Standard Definition Input Format; CCIR-656 4:2:2 8-/ 10-/16-/20-bit parallel input; standard defined output format; composite NTSC M/N; composite PAL M/N/B/D/G/H/I, PAL-60; SMPTE 170M NTSC compatible composite video; ITU -R BT. 470 PAL Compatible Composite Video; S-Video (Y/C); Euro RGB; Parts YPrPb (Betacam, MII, SMPTE/EBU N10 ) Macrovision Version 7.1.L1*CGMS/WSS System; Closed Captions.

General Features

Synchronized SD and HD inputs and outputs; oversampling up to 216MHz; programmable DAC gain control; synchronized outputs in all modes; on-board voltage reference; six 12-bit NSV precision video DACs; 2-wire serial I2C® interface; dual I/ O power supply 2.5 V/3.3 V operation; analog and digital power supply 2.5 V; on-board PLL; 64-lead LQFP package; lead-free product.

application

High-end DVD; high-end PS DVD recorder/player; SD/Prog scanning/HDTV display device; SD/HDTV set-top box; professional video system.

General Instructions

The ADV®7310/ ADV7311 is a high-speed, digital-to-analog encoder on a single chip. It includes six high-speed NSV video D/A converters with TTL compatible inputs. The ADV7310/ADV7311 have separate 8-/10-/16-/20-bit inputs for port video formats that accept high-definition and/or standard-definition data. For all standards, external horizontal, vertical, and blanking signals or EAV/SAV timing code control inserts the appropriate synchronization signal into the digital data stream and thus the output signal.

ADV7310/ADV7311 Detailed Features

HD Programmable Capabilities (720p 1080i); 2 Oversampling (148.5 MHz); Internal Test Pattern Generator (Color Shades, Black Bars, Flat Field/Frame); Fully Programmable YCrCb to RGB Matrix; Gamma Correction; Programmable Adaptive Filter Control; Programmable Sharpness Filter Control CGMS-A (720p/1080i); HD Programmable Functions (525p/625p); 8 Oversampling (216MHz Output); Internal Test Pattern Generator (Color Pattern Fill, Black bars, flat frame); single Y and PrPb output delay; gamma correction; programmable adaptive filter control; fully programmable YCrCb to RGB matrix; undershoot limiter; Macrovision version 1.1 (525p/625p) *CGMS -A (525p); standard defines programmable characteristics; 16 oversampling (216 MHz); internal test pattern generator (color bars, black bars); controlled edge rate for simultaneous active video; single Y and PrPb output delay; gamma Horse Correction; Digital Noise Reduction (DNR); Multiple Chroma and Luma Filters; Programmable Luma SSAF™ Filters; Gain/Attenuation; ;Macrovision version 7.1.L1*CGMS/WSS system; closed captions.

the term

Standard definition video, compliant with ITU-R BT.601/ITU-R BT.656.

High-definition high-definition video, i.e. progressive scan or HDTV.

PS progressive scan video, compliant with SMPTE293M, ITU-R BT.1358, BTAT-1004EDTV2 or BTA1362.

HDTV video, compliant with SMPTE274M or SMPTE296M.

YCrCb SD, PS or HD component digital video.

YPrPb SD, PS or HD component analog video.

MPU port description

The ADV7310/ADV7311 support a 2-wire serial (I2C compatible) microprocessor bus that drives multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCL), transfer information between any device connected to the bus and the ADV7310/ADV7311. Each slave device is identified by a unique address. The ADV7310/ADV7311 have four possible slave addresses for read and write operations. These are the unique addresses for each device, as shown in Figure 17. LSB sets read or write operations. A logic 1 corresponds to a read operation, while a logic 0 corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7310/ADV7311 to logic 0 or logic 1. When ALSB is set to 1, there is more input bandwidth on the I2C line, allowing high-speed data transfers on this bus. When ALSB is set to 0, the input bandwidth on the I2C line is reduced, which means that pulses less than 50ns do not enter the I2C internal controller. This mode is recommended for noisy systems.

To control various devices on the bus, the following protocols must be followed. First, the host initiates a data transfer by establishing a start condition defined by a high-to-low transition on SDA, while SCL remains high. This means that the address/data stream will follow. All peripherals respond to the start condition and move the next 8 bits (7-bit address + R/W bit). Bits are transferred from the MSB down to the LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is called an acknowledgement bit. All other devices exit the bus at this point and remain idle. The idle state is when the device monitors the SDA and SCL lines, waiting for the start state and the correct transfer address. The R/W bit determines the direction of the data.

A logic 0 on the LSB of the first byte indicates that the host will write information to the peripheral. A logic 1 on the LSB of the first byte indicates that the host will read information from the peripheral.

The ADV7310/ADV7311 are used as standard slave devices on the bus. The data on the SDA pin is 8 bits long and supports a 7-bit address plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. There is a subaddress autoincrement tool. This allows data to be written to or read from registers in an ascending sequence of subaddresses, starting at any valid subaddress. Data transfers are always terminated by a STOP condition. The user can also access any unique subaddress register one by one without updating all registers.

Stop and Start conditions can be detected at any stage of data transfer. If these conditions are inconsistent with the normal sequence of read and write operations, an immediate jump to the idle condition is caused. The user should only issue a START condition, a STOP condition, or a STOP condition followed by a START condition during a given SCL high period. If the user issues an invalid subaddress, the ADV7310/ADV7311 will not issue an acknowledgment and return to the idle state. If in auto-increment mode, the user exceeds the highest subaddress, the following actions will be taken:

1. In read mode, the contents of the highest sub-address register will continue to be output until the master sends a "No" confirmation. This indicates the end of the read. The no-acknowledge condition is that the SDA line is not pulled low on the ninth pulse.

2. In write mode, the data of the invalid byte will not be loaded into any subaddress register, the ADV7310/ADV7311 will issue a "No" acknowledgement and the part will return to the idle state.

The ADV7310/ADV7311 are required to reset at least once after power-up before writing to the subcarrier frequency register. Four subcarrier frequency registers must be updated, starting from subcarrier frequency register 0 to subcarrier frequency register 3. The subcarrier frequency is not updated until the last subcarrier frequency register byte is received by the ADV7310/ADV7311.

Figure 19 shows an example of a data transfer for a write sequence and start and stop conditions. Figure 20 shows the bus write and read sequence.

register access

The MPU can write or read all registers of the ADV7310/ADV7311, except the subaddress registers, which are write-only registers. The subaddress register determines which register is accessed by the next read or write operation. All communication with the component over the bus begins with accessing the subaddress register. A read/write operation is then performed from/to the target address, which increments to the next address until a stop command is executed on the bus.

Register programming

The following table describes the function of each register. All registers are readable and writable unless otherwise specified.

Subaddress Registers (SR7–SR0)

The communication register is an 8-bit write-only register. After accessing the part over the bus and selecting a read/write operation, the subaddress is set. The subaddress register determines which register the operation takes place on.

input configuration

When applying 10-bit input data, the following bits must be set to 1:

Address 0x7C, Bit 1 (Global Bit 10 Enable)

Address 0x13, bit 2 (HD 10 bit enabled)

Address 0x48, bit 4 (SD 10 bit enabled)

Note that the ADV7310 defaults to the synchronous standard definition and progressive scan at power up. Address[01h]: Input Mode=011.

standard definition only

Address[01h]: Input Mode=000

The 8/10-bit multiplexed input data is input on pins S9–S0 (or Y9–Y0, depending on register address 01h, bit 7), where S0 is the LSB in 10-bit input mode. The supported input standard is ITU-R BT.601/656. In 16-bit input mode, Y pixel data is input on pins S9–S2, and CrCb data is input on pins C9–C2. The 27MHz clock input must be input on pins CLKIN_A. The input sync signal is optional and is input on the S_VSYNC, S_HSYNC, and S_BLANK pins.

Progressive scan only or HDTV only

Address [01h] input mode is 001 or 010 respectively, YCrCb progressive scan, HDTV or any other HD YCrCb data can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, Y data is input to pins Y9–Y0, and CrCb data is input to pins C9–C0. In 4:4:4 input mode, Y data is input to pins Y9–Y0, Cb data is input to pins C9–C0, and Cr data is input to pins S9–S0. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i], SMPTE 296M[720p] or BTA-T1004/1362, the asynchronous timing mode must be used. RGB data can only be input in 4:4:4 format, only in PS input mode or HDTV input mode (only when HD RGB input is enabled). G data input pins Y9–Y0, R data input pins S9–S0, and B data input pins C9–C0. The clock signal must be input on Pin CLKIN_A.

Simultaneous standard definition and progressive scan or HDTV

Address[01h]: Input mode 011 (SD 10-bit, PS 20-bit) or 101 (SD and HD, SD oversampling), 110 (SD and HD, HD oversampling), respectively, must be entered in YCrCb, PS, HDTV or any other HD data, 4:2:2 format. In 4:2:2 input mode, HD Y data input pins Y9–Y0, HD CrCb data input pins C9–C0. If PS 4:2:2 data is interleaved onto a single 10-bit bus, Y9–Y0 are used for the input ports. Input data is clocked in at 27MHz, and the data is clocked on the rising and falling edges of the input clock. The input mode register at address 01h is set accordingly. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i], SMPTE 296M[720p], or BTA-T1004, the asynchronous timing mode must be used.

The 8-bit or 10-bit standard defines that the data must conform to ITU-R BT.601/656 in 4:2:2 format. Standard defines data input pins S9-S0, S0 is LSB. Using the 8-bit input format, data is input to pins S9–S2. The clock input for SD must be input on CLKIN UA, and the clock input for HD must be input on CLKIN UB. The sync signal is optional. SD sync is input on pins S_VSYNC, S_HSYNC and S_BLANK. HD sync on Pins P_VSYNC, P_HSYNC and P_BLANK.

If the two clocks are less than 9.25 ns or more than 27.75 ns out of phase in synchronous SD/HD input mode, the clock alignment bits [Address 01h, Bit 3] must be set accordingly. If the application uses the same clock source for SD and PS, the clock alignment bit must be set because the phase difference between the two inputs is less than 9.25 ns.

timing mode

HD Asynchronous Timing Mode [Subaddress 10h, Bits 3, 2]

Asynchronous timing mode can be used to connect to the ADV7310/ADV7311 for any input data that does not meet the criteria selectable in the input mode (subaddress 10h). The timing control signals for HSYNC, VSYNC, and BLANK must be programmed by the user. Macro vision and programmable oversampling rates are not available in asynchronous timing mode.

In asynchronous mode, the PLL must be turned off [subaddress 00h, bit 1=1].

Figures 29a and 29b show examples of how to program the ADV7310/ADV7311 to accept different high definition standards (except SMPTE 293M, SMPTE 274M, SMPTE 296M or ITU-R BT.1358).

The following truth table must be followed when programming control signals in asynchronous timing mode. For standards that do not require three sync levels, PúBLANK must always be limited to the low order.

The HD timing reset pin must remain high for the minimum time a clock

Timing reset is achieved by toggling the HD timing reset control loop; otherwise, the reset signal may not be recognized. This bit [subaddress 14h, bit 0] goes from 0 to 1. In this state, the horizontal timing reset only applies to the HD timing counter.

The vertical counter will remain reset. When this bit is set back to 0, the internal counter will restart counting.

SD Real Time Control, Subcarrier Reset and Timing Reset [Subaddress 44h, Bits 2, 1]

Together with the RTC_SCR_TR pin and SD mode register [address 44h, bits 1, 2], the ADV7310/ADV7311 can be used for

(a), timing reset mode, (b), subcarrier phase reset mode, or (c) RTC mode.

a. The timing reset is realized in the transition from low to high on the thyristor pin (pin 31). In this state, the horizontal and vertical counters will remain reset. When this pin is released (set low), the internal counter will start counting again, the field count will start from field 1, and the subcarrier phase will be reset. The minimum time the pin must be held high is one clock cycle; otherwise, the reset signal may not be recognized. This timing reset only applies to SD timing counters.

b. In the subcarrier phase reset, when the SD RTC/TR/SCR control bit at address 44h is set to 01, the low-to-high transition on the tc_SCR_TR pin (pin 31) will be field to reset the subcarrier phase to zero. The reset signal must remain high for at least one clock cycle.

Since the field counter is not reset, it is recommended to apply the reset signal to Field 7 [PAL] or Field 3 [NTSC]. Then do a phase reset on the next field (i.e. field 1) and properly align with the internal counter. The field count register at address 7Bh can be used to identify the number of active fields.

c. In RTC mode, the ADV7310/ADV7311 can be used to lock the external video source. The real-time control mode allows the ADV7310/ADV7311 to automatically change the subcarrier frequency to compensate for line length variations. When the part is connected to a device that outputs a digital data stream in RTC format, such as the ADV7183A video decoder (see Figure 32), the part will automatically change to the compensated subcarrier frequency line by line. The digital data stream is 67 bits wide, with subcarriers contained in bits 0 to 21. Each bit has two clock cycles. When using this mode, 00h should be written to all four subcarrier frequency registers.

reset sequence

Reset is activated by a high-to-low transition on the reset pin [Pin 33] according to the timing specification. The ADV7310/ADV7311 will revert to the default output configuration.

Figure 32 illustrates reset sequence timing.

SD VCR FF/RW Sync [Subaddress 42h, Bit 5]

In DVD recording applications where an encoder is used with a decoder, the VCR FF/RW sync control bits can be used for non-standard input video, i.e. in fast forward or fast reverse mode.

In fast forward mode, the sync information at the beginning of a new field in the input video usually occurs before the correct number of lines/fields is reached; in fast reverse mode, this sync signal usually occurs after the total number of lines/fields is reached. Traditionally, this meant that the output video would have corrupted field signals, one generated by the input video and the other generated when the internal line/field counter reached the end of the field.

When the VCR FF/RW sync control is enabled [subaddress 42h bit 5], the line/field counter is updated according to the incoming VSYNC signal and the analog output matches the incoming VSYNC signal. This control is available in all slave timed modes except Slave Mode 0.

ADV7311 Vertical Blanking Interval

The ADV7310/ADV7311 accept input data containing VBI data [CGMS, WSS, VITS, etc.] in SD and HD modes.

For the SMPTE 293M [525p] standard, VBI data can be inserted into lines 13 to 42 of each frame, or into lines 6 to 43 of the ITU-R BT.1358 [625p] standard.

For SD NTSC, this data can appear on lines 10 to 20, while PAL can appear on lines 7 to 22. If the VBI is disabled [address 11h, bit 4 for HD; address 43h, bit 4 for SD], no VBI data is present on output and the entire VBI is hidden. These control bits are valid in all master and slave modes.

In slave mode 0, if VBI is enabled, the blanking bits in the EAV/SAV code are overwritten, and VBI can also be used in this timing mode.

In slave mode 1 or 2, the blank control bit must be set to enable [Address 4Ah, Bit 3] to allow VBI data to pass through the ADV7310/ADV7311. Otherwise, the ADV7310/ADV7311 will automatically clear VBI to standard.

If CGMS is enabled and VBI is disabled, CGMS data is still available at the output.

Subcarrier Frequency Register [Subaddress 4Ch–4Fh]

Four 8-bit registers are used to set the subcarrier frequency. The values of these registers are calculated using the formula:

For example, in NTSC mode,

Subcarrier register value = 21F07C1Eh

SD FSC register 0:1Eh

SD FSC register 1:7Ch

SD FSC register 2: F0h SD FSC register 3: 21h

See the MPU Port Descriptions section for more details on how to access the subcarrier frequency registers.

square pixel timing [register 42h, bit 4]

In square pixel mode, the following timing diagram applies.

SD Internal Filter Response [Subaddress 40h; Subaddress 42, Bit 0]

The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, one extended (SSAF) response with or without gain enhancement attenuation, one CIF response, and one QCIF response. The UV filter supports several different frequency responses, including 6 low-pass responses, a CIF response, and a QCIF response, as shown in the figure below.

If SD SSAF gain is enabled, 12 responses can be selected, ranging from -4db to +4db [subaddress 47, bit 4]. The user can select the desired response by programming the correct value through I2C[Subaddress 62h]. The change in frequency response is shown in the graph on the next page.

In addition to the chrominance filters listed in Table VII, the ADV7310/ADV7311 contain an SSAF filter designed and adapted for the color difference component outputs U and V. As shown in Figure 38, the filter has a cutoff frequency of approximately 2.7MHz and -40dB at 3.8MHz. This filter can be controlled with address 42h, bit 0.

If this filter is disabled, the optional chroma filters shown in Table VII can be used for CVBS or Luma/chroma signals.

Passband ripple is the maximum fluctuation of the 0 dB response in the passband as measured by DB. The passband is defined as the low pass filter is frequency limited from 0 Hz to fc (Hz) and the notch filter is frequency limited from 0 Hz to f1 (Hz) and f2 (Hz) to infinity, where fc, f1 and f2 is the -3 dB point. 2 3 dB bandwidth refers to the -3 dB cutoff frequency.

Color control and RGB matrix

HD Y level, HD Cr level, HD Cb level [sub-address 16h–18h] Three 8-bit registers at addresses 16h, 17h, 18h are used to program the output color of the internal HD test pattern generator, whether it is cross fill The lines of the pattern are also uniform field test patterns. They cannot be used as color controls for external pixel data input. For this, an RGB matrix is used.

The standard used for Y value and color difference signals to obtain white, black and saturated primary and complementary colors conforms to the ITU-R BT.601-4 standard.

Table VIII shows the sample color values programmed into the color registers when the output standard selection is set to EIA 770.2.

HD RGB Matrix [Subaddress 03h–09h]

When the programmable RGB matrix is disabled [address 02h, bit 3], the internal RGB matrix handles all scaling of YCrCb to YUV or RGB according to the input standard programmed into the device.

Converts color components according to the 1080i standard [SMPTE 274M] when the programmable RGB matrix is enabled:

This is reflected in the pre-programmed values of GY=138Bh, GU=93h, GV=3B, BU=248h and RV=1F0.

If another input standard is used, the scale values for GY, GU, GV, BU, and RV must be adjusted according to that input standard. The user must take into account the fact that color component conversions may use different scale values. For example, SMPTE 293M uses the following transformations:

A programmable RGB matrix can be used to control the HD output level in case the video output is not compliant due to changes in the DAC output stage such as termination resistors. Programmable RGB matrix is used for external HD data and has no effect when HD test mode is enabled.

Program the RGB matrix

RGB matrix should be enabled [address 02h, bit 3], output should be set to RGB [address 02h, bit 5], sync on PrPb should be disabled [address 15h, bit 2], sync on RGB is optional [address 02h] , bit 4].

The GY of addresses 03h and 05h controls the output level of the green signal, the BU of 04h and 08h controls the output level of the blue signal, and the RV of 04h and 09h controls the red output level. To control the YPrPb output level, the YUV output [Address 02h, Bit 5] should be enabled. In this case, the Y output uses GY[Address 05h; Address 03, Bit 0-1], the Pr output uses RV[Address 09; Address 04, Bit 0-1], and the Pb output uses BU[Address 08h; Address 04h] , Bit 2-3].

If RGB output is selected, the RGB matrix scaler uses the following formula:

If YPrPb output is selected, the following formula is used:

At power up, the RGB matrix is programmed with the following default values.

When the programmable RGB matrix is not enabled, the ADV7310/ADV7311 automatically scales the YCrCb input to all standards supported in this part.

SD-Luma and Color Control [Subaddresses 5Ch, 5Dh, 5Eh, 5Fh]

SD Y Scale, SD Cr Scale and SD Cb Scale are three 10-bit wide control registers used to scale the Y, U and V output levels.

Each of these registers represents the value required to scale the U or V level from 0.0 to 2.0, and the value required to scale the Y level from 0.0 to 1.5 of its initial level. Calculate the value of these 10 bits using the following formula: Y, U or V scale value = scale factor x 512 Example: scale factor = 1.18

Y, U or V scale value=1.18×512=665.6

Y, U or V scale value = 665 (rounded to the nearest whole number)

Y, U or V scale value = 1010 0110 lbs

Address 5Ch, SD LSB register = 15h

Address 5Dh, SD Y Scale Register = A6h

Address 5Eh, SD V Scale Register = A6h

SD Hue Adjustment Value [Subaddress 60h]

Hue adjustment values are used to adjust the tint on composite and chroma output.

These eight bits represent the value required to change the hue of the video data, ie, the phase change in the phase of the sub-carrier during active video relative to the phase of the sub-carrier during the color burst. The ADV7310/ADV7311 offer a range of 22.5o increments of 0.17578125o. For normal operation (zero trim), this register is set to 80h. FFh and 00h represent the achievable upper and lower adjustment limits, respectively.

(Hue Adjustment)[o]=0.17578125o×(HCRd–128), for positive tone adjustment value.

For example, to adjust the hue by +4o, write 97h to the hue adjustment value register:

*Round to the nearest whole number

To adjust the hue by –4o, write 69h to the hue adjustment value register:

*Round to the nearest whole number

SD Brightness Control [Subaddress 61h]

Control brightness by adding programmable setting levels on scaled Y data. This brightness level can be added to the scaled Y data. For NTSC with pedestal, settings can vary from 0 to 22.5 inches. For NTSC without base and PAL, settings can vary from -7.5IRE to +15IRE.

The brightness control register is an 8-bit register. Seven bits of this 8-bit register are used to control the brightness level. This brightness level can be positive or negative.

E.g:

Standard: NTSC with base.

To add +20IRE brightness level, write 28h to address 61h, SD brightness.

Standard: PAL.

To add a –7IRE brightness level, write 72 hours to address 61h, SD brightness.

SD Luminance Detection [Subaddress 7Ah]

The ADV7310/ADV7311 allow monitoring of the brightness level of incoming video data. Brightness detection is a read-only register.

double buffering

[Subaddress 13h, bit 7; Subaddress 48h, bit 2] The double buffer register is updated once for each field on the falling edge of the VSYNC signal. Double buffering improves overall performance because register settings are not modified during active video, but take effect when active video begins.

Double buffering can be activated on the following HD registers: HD Gamma A and Gamma B curves and HD CGMS registers.

Double buffering can be activated on the following SD registers:

SD Gamma A and Gamma B Curves, SD Y Scale, SD U Scale, SD V Scale, SD Luminance, SD Closed Caption, and SD Macro Vision Bits 5–0.

Programmable DAC Gain Control DACs A, B, and C are controlled by REG 0A.

DACs D, E and F are controlled by REG 0B.

The I2C control register will adjust the output signal gain up or down from its absolute level.

In case A, a video output signal is obtained. Both the absolute level and the blanking level of the sync cue are increased relative to the reference video output signal. The overall gain of the signal is increased from the reference signal.

In case B, the video output signal is reduced. Both the absolute level and the blanking level of the sync cue are reduced relative to the reference video output signal. The overall gain of the signal is reduced from the reference signal.

The range of this characteristic is specified as ±7.5% of the nominal output of the DAC. For example, if the output current of the DAC is 4.33 mA, the DAC tuning function can change that output current from 4.008 mA (–7.5%) to 4.658 mA (–7.5%).

The reset value of the vid_out_control register is 00h → nominal DAC output current. The table below is an example of how the output current of a digital-to-analog converter changes at a rated output current of 4.33 mA.