Compensation networks ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19) are compensated networks. The compensation network must provide a closed -loop transmission function with a rapid response (but always lower than FSW/10) and the highest 0db cross -frequency of the highest gain at the highest increase in load adjustment under DC conditions. A stable control loop has an increase in gain with -20db/Decade slope, and the phase margin is greater than 45 °. Including the worst situation of the worst situation of phase margin changes. In order to locate the extreme point and zero point of the compensation network, the following suggestions can be used: the bizarre frequency of the modulator:

Set the gain R5/R3 to obtain the required converter bandwidth

Place ωz1 before the output filter resonance ωlc

Place ωz2 at the output filter at the resonance of ωlc

] Place ωp2 at half of the switch frequency

Considering the error placing the large -loop gain, check the loop gain.

15A demonstration board description

Demonstration board shows the operation of the device in a general application. According to the report table, the assessment board reduces voltage adjustment from 0.9V to 5V through the switch S2-S5, and uses the internal 0.9V reference voltage (G1 closed). Output currents exceeding 20A can be used by MOSFET: high and low -voltage side switches can use up to three SO8 MOSFETs. External reference can be used only to open the adjustment of G1 and switch S2-S5. The device can also be disabled using switch S1. VCC input rails are powered by the device, and the power conversion is input from Vin. The device can also work at a single power supply voltage; in this case, the crossover G2 is closed, and 5V to 12V inputs can be directly connected to Vin input. The four -layer demonstration board considers the high current of the circuit, and the thickness of the copper is 70 μm, so as to minimize the conduction loss. It can be handed to me PGOOD signals as logical levels. Because there is no other suitable voltage on the demonstration board. If the input voltage is higher than 7V (the maximum absolute rated value of the PGOOD pin), 5V reference voltage is required. Figure 12 shows the circuit principle diagram of the demonstration board

] Sensor select

To choose the appropriate inductor value, the application conditions must be fixed. For example, we can consider: vin u003d 12V voltage u003d 3.3V output voltage u003d 15A Considering that about 25%to 30%IOUT ripples, the inductor value will be l u003d 3μH. The 7-winding iron powder and iron core (TO50-52B).

Output capacitor

Poscap capacitors with 2 models with 6TPB330M have been selected. The maximum current of each capacitor is 40 m . Therefore, the ESR obtained is 20m . Considering the current ripple of 4A, the output voltage ripple is: #8710; vout u003d 4.0.02 u003d 80mv

Input a capacitor

The worst situation of ripples), the equal direction of the input capacitor is equal to 7.5A. The OSCON electrolytic capacitors 6SP680M, which is equal to two maximum ESRs is equal to 13m to maintain ripples. Therefore, ESR is equal to 13m /2u003d6.5m . In the worst case, the loss is: P u003d ESR · I2RMS u003d 366MW

Overcurrent protection

The current limit can be set to about 20A. Demonstration board parameters in the relationship reported in related chapters (iOSCmin u003d 170 μA; IP u003d 20A; RDSONMAX u003d 9m /2u003d4.5m ) can be substituted in ROCS u003d 510 [123 ]

Suggestions of high current application

For higher output currents up to 20A, the following configuration can be used (refer to the demonstration board schematic diagram): Q1, Q2, Q3: STS11NF30L Question 4. Question 5, Question 6: Question 6: Question 6: Question 6: Question 6: 6: Question 6: 6: Question 6: 6: Question 6: 6: Question 6: 6: Question 6: 6: Question 6: 6: Question 6: 6: Question 6: 6: Question 6: STS17NF3LL Fifty: 2.5 μH magnetic 77121A7 core 7T 2X AWG16 achieves the following performance:

For currents higher than 20A, it should be high -voltage side and low voltage low -voltage and low voltage Side (depending on the duty cycle and input voltage).

6A demonstration board description

A compact demonstration board has been implemented to manage the current within the range of 5A-6A. The external power MOSFET is included in a single SO8 package to save space and increase power density. Provide two separate rails for VCC and VIN. They can be connected by a short -handed cross -connected guide line J1. The PGOD signal is used as a logical level, and it is pulled to VIN because there is no other appropriate signal demonstration board to provide voltage. If the input voltage is higher than 7V (the maximum AB solution rated value of the PGOOD pin), a 5V reference voltage is required.

The performance of the compact demon loadThe relationship between current. The measurement has been completed under 5V and 12V input. The output voltage has been changed, and the demonstration board is reported in the modified R1 value parts list.

Application idea 1: DDR memory and terminal power dual data rate (DDR) memory requires a specific power management architecture. This is because the tracking between the driving chipset and the memory input must be terminated with a resistor. Because the chipset of the drive memory has a push -pull output buffer, the terminal voltage must be able to source current and sink current. In addition, the terminal voltage must be equal to half of the memory power supply (the input of the memory is a differential phase that requires a reference bias. DDRI is the supply of 2.5V, the end voltage of 1.25V, DDRII memory power supply 1.8V, the terminal connection voltage For 0.9V. FIG. 23 shows a complete DDRI memory and terminal power supply. Use 2 XL6910G.2.5V to supply power, while the 1.25V part provides terminal voltage. The voltage to implement the resistance division of the 2.5V.

The current required for the memory and terminal power supply depends on the type and size of the memory.

] Figure 22 and 23 showed the efficiency of L6910G for the terminal part of the application in the figure. 21, in the Sink and Source mode. The picture also shows the efficiency value when the input voltage is directly from the 12V orbit.

For a very large system (such as the server), the DDR memory terminal may require a higher current program to be 10A-15A and above. Figure 24, 25 and 26, 27 show that L6910G shows L6910G. , Receive and source model, up to 17addri and DDRII memories. That measurement value is implemented through 15A demonstration board. (See page 11)

Application ideas 2: Positive pressure rise: Positive pressure rise The voltage regulator 3V ～ 13.2V input/5V 2.5A output in some applications, the input voltage changes are wide, and the output voltage must be adjusted to the fixed value. In this case, in order to maintain the adjustment of the output voltage, it may need to need A Buck-Boost topology. The following schematic diagram shows how to achieve a downput of 33V and 5V output terminals 5V and 12V input bus. In the Buck-Buost topology, the current is only transmitted to the output end when the phase is closed to the output terminal Therefore, for the given current limit, the maximum output current depends to a large extent on the duty occupation ratio. Assuming the efficiency is 100%, the current ripples on the inductance, the current between the current limit and the maximum output is as follows:

Among them, ILIM is a current limit, D is the application of the application.The situation is DMAX.Because in the Buck-Buost application, D is given by the following formulas:

The worst case is gentle.Obviously, because the efficiency is less than 100%and the ripples are usually not ignored, the maximum output current is always lower than the value calculated above

Application ideas 3: Anti -voltage pressure reductionThe voltage regulator 3V to 5.5V input/-5V3A output can adopt a standard drop-voltage boost topical structure in applications that need negative output voltage.The factors related to the maximum output current are the same as the ""positive antihypertensive boost"" (application concept 2).One of this topology structure is that the voltage of the device is the sum of VIN and VOUT.Therefore, from 5V to -5V, the device will bear the voltage of 10V.The total voltage of the input and output must be checked below the maximum work input voltage of the device.