feature

Industry's smallest 22-bit serializer/deserializer for low power consumption with minimal impact on battery life – 100nA in standby mode with multiple power-down modes, 5mA typical operating conditions Highly rolled LVCMOS edge rate options Regulatory requirements Cable Reduction Ratio: 25:4 or greater Differential Signaling: – 90dBm EMI when using CTL under laboratory conditions – Minimized shielding – Minimized EMI filters – Minimal susceptibility to external interference Up to 22 bits in any direction 1.65V to 3.6V high ESD protection: >15kV HBM parallel I/O power supply (VDDP) range, 1.65V-3.6V can support microcontroller or RGB pixel interface

application

Image Sensor

Small Displays – LCD Monitors, Cell Phones, Digital Cameras, Portable Game Consoles, Printers, PDAs, Video Cameras, Automotive

FIN224AC compared to FIN24AC with 20% reduction in maximum power Double-width CKP pulses on FIN224AC Mode 3 Deserializer output crimp rate FIN224AC for single display applications Same voltage range Same pins and package

Note:

1. DSO/DSI serial port pins are arranged in such a way that if one device is relative to the other, the serial connection is properly aligned without any traces or cable signal crossings. Other layout directions may require track or cable crossing.

control logic circuit

FIN224AC can be used as a 22-bit serializer or a 22-bit deserializer. Pins S1 and S2 must be set to accommodate the range of the clock reference input frequency serializer. Table 1 shows the pin programming pins for these options based on the S1 and S2 controls. The DIRI pin controls whether the device is a serializer or deserializer. The device is configured as a deserializer when DIRI is asserted low. When the pin is asserted high, the device is configured as a serializer. Changing the state of the DIRI signal reverses the direction of the I/O signal and produces the opposite state signal on DIRO. For unidirectional operation the DIRI pin should be hardwired to a high or low state. The DIRI pin should be floating. For bidirectional operation, the direction system driving the master drives the slave's directory using the master's DIRO signal. Serializer/Deserializer with dedicated I/O variant Serialization and deserialization circuitry is 24-bit. Due to dedicated inputs and outputs, only 22 bits of data are serialized or deserialized. DP[21:22] sends input to serializer to DP[23:24] output on deserializer.

U-turn function

The device passes and inverts the DIRI signal. The device is asynchronous to the DIRO signal. Care must be performed by the system designer to ensure that the deserializer output communicates with other devices on this port. Devices that optimize peripherals to drive serializers should enter a high-impedance state before asserting the DIRI signal. When a device with private data output goes from deserializer to serializer, the private output remains at the last logical value of the assertion. Only this value will be overwritten if the device becomes the deserializer again and the value will be overwritten. Shutdown Mode: (Mode 0) Mode 0 is used to power off and reset the unit. When both mode signals are driven low, the PLL and reference are disabled, the differential input buffers are turned off, the differential output buffers are placed in a high impedance state, the LVCMOS outputs are placed in a high impedance state, and the LVCMOS inputs are internally is driven to a valid level. In addition, all internal circuits are reset. Loss of CKREF state is also enabled to ensure that only the PLL is powered up if a valid CKREF signal is present. In a typical application mode, the device's signal does not change beyond the desired frequency beyond the state range and power-down mode. This allows system-level power-down functionality to be connected to a pair of SerDes via a single wire. The S1 and S2 select signals, whose operating modes are driven to "logic 0" should be hardwired to GND. Signals S1 and S2 driving their operating mode to "Logic 1" should be connected to a system level power down or reset signal.

Table 1. Control Logic Circuit

Serializer Operation Mode

Serializer configuration is covered in the following sections. The basic serial circuit operation is basically the same in these modes, but the actual data clock flow differs depending on whether CKREF is the same as the strobe signal. As it is stated that CKREF is not equal to strobe, every signal is different and CKREF must run at a high frequency enough to avoid any data loss situations. CKREF must never go below strobe. Serializer Operation: Mode 1 or Mode 2, DIRI=1, CKREF=STROBEPLL must receive a stable CKREF signal to achieve lock before sending any valid data. The CKREF signal can be used as a data strobe signal to provide these data can be ignored during the phase locked loop lock phase. Once the PLL is stable and locked, the device can start capturing and serializing data. Data is captured and serialized on the rising edge of the strobe signal. when? When operating in serializer mode, the internal deserializer circuitry is disabled; includes serial clock, serial data input buffer, bidirectional parallel output, and CKP word clock. The CKP word clock is driven high. Serializer operation: DIRI=1, CKREF=STROBED If CKREF and STROBE are not using the same signal, the CKREF signal must run at a higher frequency than the strobe rate for properly serialized data. This actual serial transfer rate remains at the CKREF frequency.

When no valid data exists in the serial bit stream. Otherwise the operation of the serializer will remain unchanged. The exact frequency that the reference clock needs to run at depends on the stability of CKREF and the strobe signal. If the CKREF signal source implements the spread spectrum technique, the frequency of the spread spectrum clock should be used in the calculation of the strobe frequency and the CKREF frequency. Also, if the strobe signal has significant cycle-to-cycle variation, the maximum cycle time needs to be taken into account in the selection. CKREF frequency. Serializer operation: Mode 3 (S1=S2=1), Diri=1. CKREF divide by 2 mode. When operating in Mode 3, the effective serial speed is divided by two. This mode has been implemented for cases where the reference clock frequency is high compared to the actual gating frequency. The actual strobe frequency must be less than or equal to 50% of the CKREF frequency for this mode to operate. This mode, in all other respects, operates the same as described in CKREF and does not equal strobe. Serializer Operation: DIRI=1, No CKREF A third serialization method can be implemented by providing a free-running bit clock on the CKSI signal. This mode works by grounding the CKREF signal and driving the DIRI signal high. At power-up, the device is configured to accept a serialized clock from CKSI. This device will enable CKREF serialization mode if a CKREF is received. even after CKREF has stopped. To re-enable this mode, the device must be powered off, then use a "logic 0" on CKREF

Deserializer Operation Mode

The operation of the deserializer depends on the pair of data clock signals received on the DSI data signal pair and CKSI. The following sections describe the operating source conditions of the deserializer under different serializers. References to CKREF and strobe signals refer to serializer devices that generate serial data and clock signals that are inputs to the deserializer. When operating in deserializer mode, internal serializer circuitry is disabled, including parallel data input buffers. If the CKREF signal is provided, the CKSO serial clock continues to send the bit clock. At power-up (S1 or S2=1), the deserializer output data pin is low until valid. Data is passed through the deserializer. Deserializer Action: DIRI = 0 (Serializer When the DIRI signal is asserted low, the device is configured as a deserializer. Data is sent on the serial port and is sent along with the data by deserializing using the bit clock. Deserialization deserializer operation: DIRI=0 (serializer deserializer's logical operation is still if the frequency of CKREF is the same as or higher than the strobe. The actual serial data stream presented to the deserializer is different, Because it is on. The duty cycle of CKP varies according to the ratio to the CKREF signal frequency signal of the strobe circuit. The frequency of the CKP signal is equal to the strobe frequency. In modes 1 and 2, the CKP low time is equal to the CKREF period of the serializer half of. In Mode 3, CKP LOW is equal to the CKREF period. The CKP high time is approximately equal to the strobe period, minus the CKP low time.

LVCMOS data I/O

The LVCMOS input buffers have nominal thresholds equal to half VDD. Input buffers are only operational when the device is running as a serializer. When the device is running as a deserializer, the input is turned off to save power. The LVCMOS tri-state output buffers are rated at 1.8V for a source/sink current of approximately 0.5Ma. when the DIRI signal and S1 or S2 are asserted high. When the DIRI signal and S1 or S2 are asserted low, the bidirectional LVCMOS I/o is in the high Z state. Under purely capacitive load conditions, the output is at GND and VDDP. The state of the deserializer LVCMOS output is zero when either S1 or S2 initially transitions high. Unused LVCMOS input buffers must be tied to an active logic low or active logic high to prevent quiescent current consumption caused by floating inputs. Unused LVCMOS outputs should be left floating. Unused bidirectional pins should be connected to GND with a high value resistor. If the FIN224AC device is configured as a one-way serializer, unused data I/O can be treated as unused input. If the FIN224AC is hardwired as a deserializer, unused data I/O can be treated as unused output.

Application Pattern Diagram

Flexible Circuit Design Guidelines Serial I/O information is transmitted at high serial rates. Care must be taken to implement this serial I/O flex cable. When developing flex routing or flex PCB, the following best practice should be used: Keep all four differential wires the same length. No noise signals are allowed on or near the differential serial lines. Example: There are no LVCMOS traces on the differential wires. Use only one ground plane or differential serial line. Don't run the ground from top to bottom. Do not place test points on differential serial lines. Use a differential serial line, at least 2 cm away from the antenna

absolute maximum ratio

Pressure beyond the absolute maximum ratio may damage the equipment. The device may not function or be operatible above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratio of tea is only the stress ratio

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual equipment operation. Recommendations specify operating conditions to ensure optimum performance to data sheet specifications. Fairchild does not recommend exceeding or designing to absolute maximum ratings.

Note:

2. Absolute Maximum Ratings are DC values beyond which the device may be damaged or its service life impaired. Datasheet specifications should be met without exception to ensure that the system is designed within its power, temperature, and output/input load variables. Fairchild does not recommend manipulating datasheet specifications externally

DC characteristics

Unless otherwise specified, this value applies to overvoltage and operating temperature ranges. Typical values are given for VDD=2.775V and TA=25°C. Positive current values refer to the current flowing into the device and negative current values refer to the current flowing out of the pins. Unless otherwise specified, voltages are referenced to ground (except for ΔVOD and VOD).

supply current

Typical values for VDD=2.775V and TA=25°C are given. Positive current values refer to the current flowing into the device and negative values refer to the current flowing out of the pins. Voltage referenced to ground unless otherwise specified (except ΔVOD and VOD).

AC Electrical Characteristics

Characteristics over voltage and operating temperature ranges are recommended unless otherwise specified. Typical values for VDD=2.775V and TA=25°C are given. A positive current value means current flowing into the device and a negative value means current flowing out of the pin. Unless otherwise specified, voltages are referenced to ground (except ΔVOD and VOD).

notes:

3. The skew is measured from the rising or falling edge of the CKSO clock to the rising or falling edge of the data (DSO). Signal edge alignment. Both outputs should have the same load conditions for this test to be valid.

4. Power down time is a function of CKREF frequency before CKREF high or low is stopped, and the state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies depending on the device's operating mode.

5. Signals are transmitted synchronously from the serializer source. Note that in some cases, when the clock is still high. Skew time should only be measured when the data and clock are transitioning at the same time. The total measured input skew is the output skew from the serializer, a combination of load variation and ISI, and jitter effects.

6. After the falling edge of CKP output, about 13 bits of CKP rising edge appear on the rising edge of CKP. The falling edge of CKP occurs approximately eight bit times after a data transition or six bit times after the falling edge. queso. The variation of data relative to the CKP signal is due to differences in the data and CKP paths and propagation delays on the different data pins. Note that the CKP signal does not maintain a 50% duty cycle if CKREF is not equal to the gating for the serializer. CKP's low time remains 13-bit time