feature

New design replaces ADC574 ; complete sampling A/D; reference, clock and microprocessor interface; fast acquisition and conversion: 25 microseconds maximum; elimination of external sample/hold; in most applications; guaranteed AC and DC performance; Single supply +5V operation; low power: 100mW max; package options: 0.6" and 0.3" tilt, SOIC.

illustrate

ADS54 is a 12-bit successive approximation. CMOS technology is implemented with low power consumption using an innovative Analog-to-Digital Converter Capacitor Array (CDAC). This is a replacement for the ADC574 model in most applications, is internally sampled, consumes much lower power, and is capable of running from a +5V supply.

The ADS574 features an internal clock, microprocessor interface, tri-state outputs, and internal input ranges of 0V to +10V, 0V to + 20V , ±5V, ±10V. The maximum throughput time for 12-bit conversions is 25 microseconds over the entire temperature range of operation, including acquisition and conversion. Full user control over the internal sampling function helps eliminate external sample/hold amplifiers in most existing designs. The ADS574 requires +5V, optionally -12V or -15V, depending on the application. A +15V power supply is not required. Available packages include 0.3" or 0.6" wide 28-pin plastic dip and 28-lead SOIC.

theory of operation

In the ADS574, the advantages of advanced CMOS technology (high logic density, stable capacitors, precise analog switches, and Burr Brown's state-of-the-art laser trimming technology) are combined to produce a fast, low-power analog-to-digital with internal sample/hold converter.

A charge redistribution successive approximation circuit converts the analog input voltage into a digital word. Figure 1 shows a simple example of a charge redistribution A/D converter with only 3 bits.

Approximate by connecting S2 to reference and S3 to GND, and latching S2 according to the output of the comparator. After three consecutive approximation steps, the voltage level of the comparator will be within 1/0 of GND, and a digital word representing the analog input can be determined from the positions of S1, S2, and S3.

input scaling

Precision laser-trimmed scaling resistors on the input divide the standard input range (0V to +10V, 0V to +20V, ±5V, or ±10V) into levels compatible with the CMOS characteristics of the internal capacitor array.

sampling

When sampling, the capacitor array switch of the MSB capacitor (S1) is in the "S" position so that the charge on the MSB capacitor is proportional to the voltage level of the analog input signal. The remaining array switches (S2 and S3) are set to position "G". Switch S is closed, setting the comparator input offset to zero.

convert

When a convert command is received, switch S1 is opened to capture the charge on the MSB capacitor proportional to the analog input level at the time of the sampling command, and switch S is opened to float the comparator input. Now, by connecting switches S1, S2, and S3 to position "R" (connected to reference) or "G" (connected to GND), the charge trapped in the capacitor array can move between the three capacitors in the array, thereby Change the voltage developed at the input of the comparator.

During the first approximation, the MSB capacitance is connected to the reference through switch S1, while switches S2 and S3 are connected to GND. Depending on whether the comparator output is high or low, the logic will then latch S1 in position "R" or "G". Similarly, the second Figure 2 shows the minimum circuit required to operate the ADS574 in control mode (discussed in detail in later chapters) over the basic ±10V range. The falling edge of the conversion command (minimum 25ns low pulse on pin 5) switches the ADS574 input to hold and initiates the conversion. Pin 28 (status) will output high during conversions and will only go down after the conversion is complete and the data has been latched on the data output pins (pins 16 to 27). Therefore, the falling edge of state on pin 28 can be used to read data from the transition. In addition, during conversion, the status signal puts the data output pin into a high-Z state and inhibits the input line. This means that pulses on pin 5 are ignored, so new conversions cannot be initiated during conversions, either due to spurious signals or to shorten the period of the ADS574.

The ADS574 will start acquiring new samples after the conversion is complete (even before the state output has dropped) and will track the input signal until the next conversion begins. The ADS574 is designed to complete the conversion and accurately acquire the new signal with a maximum of 25 microseconds over the entire operating temperature range so that the conversion can take place at full 40kHz.

Controlling the ADS574

The Burr Brown ADS574 can be easily interfaced to most microprocessor systems and other digital systems. The microprocessor can have full control of each conversion, or the converters can operate in stand-alone mode, controlled only through the R/C input. Full control includes selecting an 8-bit or 12-bit conversion cycle, starting the conversion, and reading the output data when ready, selecting 12 bits at a time, or selecting 8 MSB bits followed by 4 LSB bits in left-justified format. The five control inputs (12/8, CS, A0, R/C and CE) are all TTL/CMOS compatible. The functions of the control input are shown in Table 2. The truth table of the control function is shown in Table 3.

Independent operation

For stand-alone operation, control of the converter - In this mode, CS and A0 are connected to digital common, CE and 12/8 are connected to +5V, and the output data is displayed as a 12-bit word. Standalone mode is used in systems that contain dedicated input ports that do not require full bus interface functionality.

A conversion is initiated by a high-to-low transition of R/C. The tri-state data output buffer is enabled when R/C is high and state is low. Therefore, there are two possible modes of operation; data can be read by a positive or negative pulse state on the R/C. In both cases, the R/C pulse must be held low for at least 25ns.

Figure 3 shows the timing of the R/C pulse going low and back high during a conversion. In this case, the tri-stated output goes into a high-impedance state in response to the falling edge of R/C and enables external access to the data after the conversion is complete.

Figure 4 shows the timing when a positive R/C pulse is used. In this mode, the output data of the previous converter - sion is enabled when R/C is high. A new conversion begins on the falling edge of R/C, and the tri-state output returns to a high-impedance state until the next high R/C pulse. The timing specification of stand-alone operation is shown in Table 4.

Full control operation conversion length

The conversion length (8-bit or 12-bit) is determined by the state of the A0 input, which is locked when a conversion is received to start a conversion (described below). If A0 is latched high, the conversion continues for 8 bits. If A0 is low, a full 12-bit conversion will occur. If all 12 bits are read after an 8-bit conversion, the 4LSB (DB0-DB3) will be low (logic 0). A0 is latched because it also participates in enabling the output buffer. No other control inputs are locked.

conversion starts

The converter initiates a conversion on any of the three logic inputs (CE, CS, and R/C) based on conversion, as shown in Table III. The transition is initiated by the last of the three logic inputs to reach the desired state, so all three logic inputs can be dynamically controlled. If necessary, all three can change state at the same time with the same nominal delay time regardless of which input actually starts transitioning. If a specific input is required to determine the actual start of a transition, the other two inputs should be stable at least 50ns before the critical input transition. The timing relationship of the start conversion timing is shown in Figure 5. See Table 5 for timing specifications.

The status output indicates the current state of con - high only during transitions. During this time, the tri-state output buffer remains in a high-impedance state and therefore cannot read data during the conversion process. During this time, additional transitions of the three digital inputs that control the transition are ignored, so transitions cannot be prematurely terminated or restarted. However, if A0 changes state after the transition has started, any additional start transition transitions will lock in the new state of A0, possibly resulting in an incorrect transition length for that transition (8 bits vs. 12 bits).

read output data

After a conversion is initiated, the output data buffer remains in a high-impedance state until the following four logic conditions are met simultaneously: R/C high, state low, CE high, and CS low. After these conditions are met, according to the input 12/8 and A0. See Figure 6 and Table V for timing relationships and specifications.

In most applications, the 12/8 input will be hardwired for a high or low condition, although it is fully TTL and CMOS compatible and can be actively driven if desired.

When 12/8 is high, all 12 output lines (DB0-DB11) are enabled simultaneously to transfer complete data words to the 12-bit or 16-bit bus. In this case, the A0 state is ignored when reading data.

When 12/8 is low, the data is presented as two 8-bit bytes, and the selection of the byte of interest is done through the A0 state during the read cycle. When A0 is low, the byte address contains 8msb. When A0 is high, byte addressing consists of the 4lsb from the conversion, followed by four logic zeros forced by the control logic. The left-aligned format of two 8-bit bytes is shown in Figure 7. The connection of the ADS574 to the 8-bit bus is used for data transfer, as shown in Figure 8. The design of the ADS574 guarantees that the A0 input can be switched at any time without damaging the converter; the outputs bundled together in Figure 8 cannot be enabled at the same time. The A0 input is normally driven by the least significant bit of the address bus, allowing output data words to be stored in two consecutive memory locations.

S/H control mode and ADC574 emulation mode

The basic difference between the two modes is the assumptions made about the state of the input signal before and during the transition. The differences are shown in Figure 9 and Table VI. In control mode, it is assumed that the signal does not rotate faster than the ADS574 during the required acquisition time of 4 microseconds. After the convert command arrives, no assumptions are made about the input level because the input signal is sampled and the conversion begins immediately after the convert command.

This means that the conversion command can also be used to switch the input multiplexer or change the gain on the programmable gain amplifier, allowing the input signal to settle before the next acquisition at the end of the conversion. Since aperture jitter is minimized by internal sample/hold circuitry, high input frequencies can be converted without external sample/hold.

In emulation mode, the input signal is not assumed before the convert command. Introducing a delay time between the conversion command and the start of the conversion allows the ADS574 enough time to acquire the input signal before conversion. The delay increases the effective aperture time from 0.02 microseconds to 4 microseconds, but allows the ADS574 to replace the ADC574 in any circuit. The slew system of any analog input (due to multiplexers in front of the converter, sample/hold, etc.) prior to an existing conversion command does not affect the accuracy of the ADS574 conversions in analog mode.

In both modes, as soon as the conversion is complete, the internal sample/hold circuit starts spinning to track the input signal. Basically, the provided control modes allow full use of the internal sample/hold and no external sample/hold is required in most applications. In contrast to systems using separate sample/hold and A/D, the ADS574 in control mode also requires no control signals, usually conversion commands. A command to put the internal sample/hold into hold also initiates a conversion, reducing time constraints in many systems.

Emulation mode allows the ADS54 to be dropped into almost all existing ADC54 sockets without changing any other existing system hardware or software. Before receiving the conversion command, the input to the ADS574 does not need to be stable in emulation mode, so as long as the analog input to the ADS574 is stable after receiving the conversion command, the multiplexer, programmable gain amplifier, etc. can be given A quick spin anytime before the conversion command, as it requires precise operation in existing ADC54 systems. In fact, even in emulation mode, system throughput can be accelerated because the input to the ADS54 can start spinning before the end of the conversion (after the acquisition time), which is not possible with the existing ADC57S.

Install

Layout Considerations

The analog (pin 9) and digital (pin 15) commons are not connected together inside the ADS574, but should be connected together as close as possible to the analog common ground plane under the converter on the unit and board assembly side. Also, the wide wire pattern should go directly from pin 9 to the analog power common, and a separate wide wire pattern from pin 15 to the digital power common.

If a single point system common cannot be established directly at the converter, pins 9 and 15 should still be connected together at the converter. Then, a single wide conductor pattern connects these two pins to the system common. In both cases, the common return of the analog input signal should be referenced to pin 9 of the ADC. This prevents any voltage drop that might occur in the power common return in series with the input signal.

Power decoupling

On the ADS574, +5V (to pin 1) is the only supply required for proper operation. Pin 7 is not connected internally, so no problem in the existing ADC54 socket, which is connected to +15V here. Pin 11 (VEE) is used only as a logic input to select the control mode of the sampling function as described above. When used in an existing ADC54 socket, -15V on pin 11 selects ADC54 emulation mode. Since pin 11 is used as a logic input, it is immune to typical power supply variations.

The +5V supply should be bypassed with a 10µF tantalum capacitor close to the converter to facilitate noise-intrusive operation, as shown in Figure 2. Noise on the power line can degrade the performance of the converter. Noise and spikes in switching power supplies are particularly troublesome.

range join

The ADS574 offers four standard input ranges: 0V to +10V, 0V to +20V, ±5V, or ±10V. Figure 10 and Figure 11 show the necessary connections for each range, as well as optional gain and offset trim circuits. If a 10V input range is required, the analog input signal should be connected to pin 13 of the converter. Signals that require a 20V voltage range are connected to pin 14. In both cases, the other pin is not connected. Pin 12 (bipolar offset) connects to pin 9 (analog common) for unipolar operation, or pin 8 (2.5V reference output), or external reference, for bipolar operation. Full scale and offset adjustments are described below.

The input impedance of the ADS574 is typically 84kΩ in the 20V range and 21kΩ in the 10V range. This is significantly higher than the traditional ADC574 architecture and reduces the loading of the input source in most applications.

input structure

Figure 12 shows the resistive divider input structure of the ADS574. Since the input drives the capacitors in the CDAC during acquisition, the input will look for high impedance - if using a 10V analog input range (bipolar or unipolar), the 20V range input (pin 14) should be shielded from a ground plane to reduce noise pick up.

Coupling between analog input lines and digital lines should be minimized through careful layout. For example, if lines must intersect, they should intersect at right angles. Parallel analog and digital lines should be separated from each other by a pattern connected to a common line. If external full-scale and offset potentiometers are used, the potentiometers and associated resistors should be as close as possible to the ADS574. Compared to the traditional ADC574 structure, in this structure, the resistor divider network observes the comparator input node on virtual ground.

To understand how this circuit works, it is necessary to know that the input range on the internal sampling capacitor is 0V to +3.33V, and the analog input of the ADS574 must be converted to this range. The unipolar 20V range can be used as an example of how a divider network works. In 20V operation, the analog input goes to pin 14. Pin 13 is not connected and pin 12 is connected to analog common pin 9. It is clear from Figure 12 that the input to the capacitor array will be the analog input voltage on pin 14 divided by the resistor network (68kΩ + 68kΩ | | 17kΩ). The 20V input at pin 14 is split into 3.33V at the capacitor array, and the 0V input at pin 14 is 0V at the capacitor array.

The main effect of the 10kΩ internal resistor on pin 12 is to provide the same offset adjustment response as the traditional ADC574 structure without changing the external trim value.

Single supply operation

The ADS574 is designed to operate from a +5V supply and handles all unipolar and bipolar input ranges, whether in control mode or emulation mode as described above. Pin 7 is not connected internally. This is where +12V or +15V is available on traditional ADC574s. The –12V or –15V power input pin 11 on the legacy ADC574s is only used as a logic input on the ADS574. There is a resistor divider inside pin 11 to reduce this input to the correct logic level within the ADS574, this resistor will increase the power dissipation of the ADS574 by 10mW to 15mW when -15V is provided on pin 11. To minimize power consumption in the system, pin 11 can simply be grounded (for emulation mode) or tied to +5V (for control mode) with no additional modifications required when the ADS574 uses a single +5V supply.

calibration

Optional external full scale and offset adjustment

For unipolar and bipolar operation, the offset and full-scale errors can be trimmed to zero using external offset and full-scale trim pots connected to the ADS574, as shown in Figures 10 and 11.

Calibration Procedure - Unipolar Range

If external adjustment of full scale and offset is not required, replace R2 in Figure 10 with a 50Ω, 1% metal film resistor, eliminating the other adjustment components. Connect pin 12 to pin 9.

If adjustments are required, connect the converter as shown in Figure 10. The input is scanned through the endpoint transition voltages (0V + 1/2LSB; +1.22mV for the 10V range and +2.44mV for the 20V range), resulting in an output code of DB0 on (high). Adjust potentiometer R1 until DB0 turns on and off alternately with all other bits off. Then, adjust full scale by applying an input voltage of negative 3/2LSB of nominal full scale, which should turn all bits on. For the 10V range, this value is +9.9963V; for the 20V range, this value is +19.9927V. Adjust potentiometer R2 until bits DB1DB11 turn on and DB0 turns on and off.

Bipolar Span Calibration Procedure

If external adjustment of full scale and bipolar bias is not required, replace the potentiometer in Figure 11 with a 50Ω, 1% metal film resistor.

If adjustments are required, connect the converter as shown in Figure 11. The calibration procedure is similar to the steps above for unipolar operation, except that the offset adjustment is performed with the input voltage above 1/2LSB of the negative full-scale value (–4.9988V for the ±5V range, –9.9976V for the ±10V range ). Adjust R1 so that DB0 turns on and off with all other bits off. To adjust full scale, apply a DC input signal 3/2LSB below the nominal full scale value (+4.9963V for ±5V range, +9.9927V for ±10V range) and adjust R2 of DB0 to Turns on and off with all other bits turned on.