In your previous study of circuit theory, you may have learned many techniques for analyzing circuits. Nodal voltage analysis and mesh analysis are two well-known similar techniques. In the nodal voltage analysis method, you first need to select a node and use it as a reference node. This node is usually assumed to have absolute zero potential, and we usually call it the "ground" node.

As long as you don't care about the voltage relationship between the circuit and other objects, you generally don't find this assumption harmful. Using a node common to multiple subcircuits as a ground node is often an excellent choice for mathematically simplifying circuit analysis.

When we study electronic circuits, we often forget many circuit analysis techniques, such as superposition, Thevenin equivalent, Norton equivalent, and mesh analysis, etc., and focus on one technique, node voltage analysis (Figure 1).

Figure 1: Nodal voltage analysis often simplifies the analysis of electronic circuits. The left side of the above figure is an example of a node voltage analysis, and the right side is an example of a mesh analysis of the same circuit.

As a student and engineer, after years of in-depth study, you may have forgotten some basic concepts in electronic circuit theory, just when fatal misconceptions seep into our minds.
common misconceptions

The ground node is often mistaken for the physical entry point of all charges. Of course this is not right. The ground node is just a node of our personal choice. It's nothing special except that it's usually a common node for many subcircuits. And being a public node does not add any special physical properties. The only charge stored on the ground node is the negative plate charge of the capacitor with one end connected to ground. All other charges circulate in the circuit and never stop (Figure 2). Remember that all current flows in a loop and the charge returns to its source.

Figure 2: The current charge circulates in the loop, the only charge stored on the ground node (–Q) is the charge on the ground capacitor.

The ground node is a safe harbor from noise. This is also not true, most of the different noise currents will pass through the ground node (Figure 3). However, only for a well-designed ground rail, the impedance of the conductor rail is negligible, and the noise potential difference across the rail is almost zero.

Figure 3: Different signal currents and different noise currents through the ground node. The low impedance of the ground rail is the only guarantee that the potential difference between any two physical points in the conductor rail is negligible, at least in DC circuit analysis.
It is widely believed that isolating the ground pads of the two interacting domains protects the quiet domain from the noisy domain. This is probably one of the worst mistakes an RF engineer can make without knowing it. In many cases, the separation of the ground pads can cause severe noise coupling from the noise domain output to the quiet domain input. You may find this counterintuitive, but it becomes clear when you use bond wires to draw the complete circuit down to the PCB layers, as shown in Figure 4. A similar effect occurs when all MOS bodies are connected to dedicated ground pads.

Figure 4: When the ground pads on the left side of the above figure are separated, the transmitted signal from one domain to the other can become very noisy. Its analysis steps are marked with purple circles. On the other hand, as shown in the figure on the right, after merging the domains, the signal is transmitted safely. However, if the PSRR is poor, the quiet domain may be affected.

In a digital circuit design that considers power dissipation, floating outputs are not only related to breaking the ground path, but also breaking the power path (Figure 5). Physical design preferences often favor switching ground paths. This is because NMOS devices with smaller area than PMOS devices will be used for the same on-resistance.

Figure 5: When power or ground is turned off, it is inevitable that the output voltage can be indeterminate. And this indeterminate output voltage depends on the last active output state stored on the load capacitor, the OFF resistance ratio between the power supply and ground, and the leakage current at the various junctions.

The ground and power rails do not appear to be relevant for timing closure. Timing closure is related to different cell delays and different signal edges. When the ground rail has a relatively high impedance, a considerable IR drop occurs between the power rail and the ground rail, which reduces the effective supply voltage and thus increases the delay of the CMOS cell. Also, even if the average IR drop across the power rails is negligible, switching noise currents can create significant transient noise voltages on the ground rails. Therefore, as shown in Figure 6, signal edges arriving at gates farther from the signal source can be "moved" in time and efficiently [1]. The time shift depends on the magnitude and polarity of the transient noise. This effect becomes more pronounced for high rise/fall time signals.

Figure 6: According to the analysis steps shown by the purple circles, the transient power/ground current curve produces a similar voltage curve at ground, which affects the valid arrival time of the signal edge. This problem can be mitigated by greatly increasing the local decoupling capacitors to sink the AC current curve and reducing the impedance of the power/ground rails.

Do ground pads need to be separated?
This is a tricky question and requires elaboration. The foregoing may give the impression that ground pad separation is a bad design practice, although it may be a common practice in many chips. In general, designing a single unified ground with low resistance and low inductance is far superior to designing multiple ground rails. Multiple ground rails can cause problems such as complex return current paths between multiple scopes, and magnetic coupling caused by large-area loops carrying high-frequency currents.
However, in some cases separation of the ground pads is unavoidable. For example, consider a crystal oscillator and a noisy digital block that share a ground pad, as shown in Figure 7. Digital blocks draw noise current from the power supply and return it through the ground rail and bond wires. Therefore, there will be a significant voltage fault on the ground wire. Since this bond wire is shared with the crystal oscillator's ground, the noise voltage fault is loaded onto the crystal's pure sinusoidal voltage at the crystal's internal nodes.

Figure 7: According to the analysis steps shown in the purple circle, the noise block will indirectly generate a noise voltage across the ground wire. Since the crystal is actually a bandpass filter with very good cut-off characteristics, during oscillation there is a pure sinusoidal voltage on each of its terminals. However, the internal nodes of the crystal oscillator sense the superposition of pure and noise voltages across the ground line.

In the event that you need to separate the ground pads, do the following:

Place as many decoupling capacitors as possible around the noise block (Figure 8). This reduces the transmission of noisy supply currents outside the chip, thereby minimizing noise voltages on the module rails and their outputs.
Minimize electrical interactions between noisy modules and other module blocks, or just reduce the current passed. For this purpose, drivers with relatively high output impedance are used in the noise domain and drivers with high input impedance buffers are used in the quiet domain.

Figure 8: Decoupling capacitors on the noise block side absorb most of the AC current components flowing through power and ground. Minimizing the transfer current from the noise domain to the sensitive domain ensures that the transfer of noise is minimized.

The ground node is simply a node defined for circuit analysis. All current is still carried in the loop and does not stop at the ground node.

To predict and solve ground-related problems, simply draw the complete circuit with all physical connections, without defining ground nodes, and visualize the different current loops and common paths.

Carefully understand the expected gain and potential impact before deciding to unify or separate ground pads for different domains.

Figure 9 shows an exercise problem. The left side shows a simple NMOS current source with finite drain resistance. So, what is the low frequency AC impedance of the supply voltage source seen?

Figure 9: Does the ground node definition affect the input impedance value?
The answer is very simple. Keeping the circuit physically the same, but choosing the NMOS drain as the ground node instead of the NMOS source, as shown on the right side of Figure 9, would the impedance remain the same? Don't let grounding fool you.