feature

Specified VDD is 2.7 V to 5.25 V; AD7470 1.75 MSPS (10-bit); AD7472 1.5 MSPS (12-bit); low power; AD7470: 3.34 mW, 1.5 mSv/sec, 3 V supply; 7.97 mW, 1.75 mSv/sec, 5V power supply; AD7472: 3.54 mW, 1.2 mSv/sec with 3V power supply; 8.7 mW, 1.5 mSv/sec, 5V power supply; wide input bandwidth; 500 kHz input frequency 70 dB typical signal-to-noise ratio; flexible power/throughput management; no pipeline latency; high-speed parallel interface; sleep mode: 50 mA; 24-lead SOIC and TSSOP packages.

General Instructions

The AD7470/AD7472 are 10-bit/12-bit high speed, low power, successive approximation ADCs. Operating these parts from a 2.7V to 5.25V supply, the 12-bit AD7472 has a throughput of up to 1.5ms and the 10-bit AD7470 has a throughput of up to 1.75ms. These parts contain a low noise, broadband track/hold amplifier that can handle input frequencies in excess of 1 MHz.

The conversion process and data acquisition are controlled using standard control inputs, allowing easy connection to a microprocessor or DSP. The input signal is sampled on the falling edge of CONVST, at which point the conversion also begins. The busy tone goes high at the start of a conversion and goes low 531.66ns after the falling edge of CONVST (AD7472, clocked at 26mhz) to indicate that the conversion is complete. There are no pipeline delays associated with parts. Conversion results are accessed via standard CS and RD signals through a high-speed parallel interface.

The AD7470/AD7472 employ advanced design techniques to achieve very low power consumption at high throughput rates. With a 3v supply and 1.5msps throughput, the AD7470 consumes only 1.1ma on average. With a 5V supply and 1.75ms/sec, the average current draw is typically 1.6mA. This section also provides flexible power/throughput management. Operating the AD7470 with a 3 V supply and 500 kSPS throughput reduces current consumption to 713 μA. At 5 V supply and 500 kSPS, the part consumes 944 microamps.

It is also possible to operate the part in an automatic sleep mode, in which the part wakes up for a transition and automatically goes to sleep mode when the transition ends. Very low power consumption can be achieved at lower throughput using this approach. In this mode, the AD7472 can operate at 100 kSPS from a 3 V supply, with an average current consumption of only 124 µA. With a 5 V supply and 100 kSPS, the average current consumption is 171 µA.

The analog input range for this part is 0 to REF IN. The +2.5 V reference voltage is externally applied to the reference input pin. The conversion rate is determined by the externally applied clock.

Product Highlights

1. High throughput and low power consumption. The AD7470 has a throughput of 1.75 MSPS and the AD7472 has a throughput of 1.5 MSPS and consumes 4 mW.

2. Flexible power/throughput management. The slew rate is determined by an externally applied clock that allows for power reduction as the slew rate decreases. The part also features an automatic sleep mode to maximize power efficiency at lower throughput rates.

3. No pipeline delay. The part has a standard continuous approximation ADC, with precise control of the sampling moment by sampling the input and one conversion control.

term integral nonlinearity

This is the maximum deviation of a straight line through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, 1/2 LSB point below the first code transition and 1/2 LSB point above the last code transition.

Differential nonlinearity

This is the difference between the measured value and the ideal 1 LSB change between any two adjacent codes in the ADC.

offset error

This is the deviation of the first code transition (00). . . 000) to (00.. . 001) from the ideal state, which is AGND+1 LSB.

gain error

The last conversion should occur at 1 1/2 LSBs of the analog value below the nominal full scale. The first transition is 1/2 LSB above the low end of the scale (zero in the case of the AD7470/AD7472). Gain error is the deviation of the actual difference between the first and last transcoding from the ideal difference between the first and last transcoding, and offset errors are eliminated.

Track/Hold Acquisition Time

After conversion, the track/hold amplifier returns to track mode. The track/hold capture time is the time it takes for the output of the track/hold amplifier to reach its final value (within ±1 LSB) after a conversion has ended.

signal to noise ratio

This is the signal-to-noise ratio (noise + distortion) measured at the output of the A/D converter. The signal is the rms amplitude of the fundamental wave. Noise is the sum of all non-fundamental signals up to half the sampling frequency (fS/2), excluding DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio (noise + distortion) of an ideal N-bit converter with a sine wave input is given by:

So, for a 12-bit converter, that's 74 decibels, and for a 10-bit converter, it's 62 decibels.

total harmonic distortion

Total Harmonic Distortion (THD) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7470/AD7472, the definitions are as follows:

where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fS/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 Wait. The intermodulation distortion term refers to the term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7470/AD7472 are tested using the CCIF standard using two input frequencies near the top of the input bandwidth. In this case, the second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the THD specification, where is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.

Aperture delay

In sample/hold, the time it takes for the switch to fully open after a hold command is the aperture delay. In effect, the samples are delayed by this interval, and for accurate timing, the hold command must be advanced by this amount.

Aperture jitter

Aperture jitter is the variation in aperture delay. In other words, it's uncertainty about when to sample. Jitter is the result of noise modulation maintaining the commanded phase. This specification establishes the maximum timing frequency for a given resolution, and therefore the maximum sampling frequency. This error will increase as the input dV/dt increases.

Circuit Description Converter Operation

The AD770/AD772 are capacitive DAC based 10-bit/12-bit successive approximation analog-to-digital converters. The AD7470/AD7472 can convert analog input signals in the 0 V range to VREF. Figure 2 shows a very simple ADC schematic. Control logic, synthetic aperture radar (SAR), and capacitive digital-to-analog converters (DACs) are used to add and subtract a fixed amount of charge from the sampling capacitor to bring the comparator back into balance.

Figure 3 shows the ADC during the acquisition phase. SW2 is closed and SW1 is in position A. The comparator remains in equilibrium and the sampling capacitor picks up the signal on the VIN.

Figure 4 shows the ADC during a conversion. When the conversion begins, SW2 will open and SW1 will move to position B, causing the comparator to become unbalanced. The ADC then goes through its successive approximation routine and brings the comparator back to equilibrium. When the comparator is rebalanced, the conversion result is available in the SAR register.

Typical Wiring Diagram

Figure 5 shows a typical connection diagram for the AD7470/AD7472. Conversions are initiated by a falling edge on CONVST. Once CONVST goes low, the BUSY signal goes high, and at the end of the conversion, the falling edge of BUSY is used to activate the interrupt service routine. Then, the CS and RD lines are activated in parallel to read 10 or 12 data bits. The recommended reference voltage is 2.5 V, providing an analog input range of 0 V to 2.5 V, making the AD7470/AD7472 a unipolar A/D. It is recommended to perform a dummy conversion after power up, as the first conversion result may not be correct. This also ensures that the part is in the correct operating mode. When powered on, the CONVST pin should not be floating, as the rising edge of CONVST may not wake up the part.

In Figure 5, the VDRIVE pin is connected to DVDD, which results in a logic output voltage of 0V or DVDD. Voltage value of the voltage control output logic signal applied to VDRIVE. For example, if DVDD is powered by a 5v supply and VDRIVE is powered by a 3v supply, the logic output voltage level will be 0v or 3v. This feature allows the AD7470/AD7472 to interface with 3v parts while still allowing the A/D to process signals from a 5v supply.

ADC transfer function

The output encoding of the AD7470/AD7472 is straight binary. The designed transcoding occurs at consecutive integer LSB values (ie 1 LSB, 2 LSB, etc.). For the AD7472, the LSB size is = (REF IN)/4096, and for the AD7470, the LSB size is (REF IN)/1024. The ideal transfer characteristics of the AD7472 are shown in Figure 6.

AC acquisition time

In AC applications, it is recommended to always buffer the analog input signal. The source impedance of the driver circuit must be as low as possible to minimize the acquisition time of the ADC. A larger impedance value at the VIN pin of the ADC will cause the THD to degrade at high input frequencies.

reference input

The following references are best suited for use with the AD7470/AD7472.

ADR291

AD780

AD192

For best performance, a 2.5 V reference is recommended. The part can operate with reference voltages as high as 3V and as low as 2V, but with degraded performance.

DC acquisition time

The ADC starts a new acquisition phase at the end of the conversion and ends it on the falling edge of the CONVST signal. At the end of the conversion, there is a settling time associated with the sampling circuit. This settling time lasts about 135 nanoseconds. The analog signal on VIN is also acquired during this settling time, so the minimum required capture time is about 135 nanoseconds.

Figure 8 shows the equivalent charging circuit for the sampling capacitor when the ADC is in the acquisition phase. R3 is the source impedance of the buffer amplifier or resistor network, R1 is the internal switch resistance, R2 is the bandwidth control, and C1 is the sampling capacitor. C2 is the backplane capacitance and switch parasitic capacitance.

During the acquisition phase, the sampling capacitor must be charged to within 1lsb of its final value.

analog input

Figure 9 shows the equivalent circuit of the AD7470/AD7472 analog input structure. Two diodes D1 and D2 provide ESD protection for the analog inputs. Capacitor C3 is typically around 4pf and can be attributed mainly to pin capacitance. Resistor R1 is an internal switching resistor. This resistance is usually about 125Ω. Capacitor C1 is the sampling capacitor, while R2 is used for bandwidth control.

clock source

The AD7470 has a maximum CLK specification of 30 MHz, while the AD7472 has a maximum CLK specification of 26 MHz. These frequencies are not readily available standard oscillator frequencies. Many manufacturers produce oscillator modules close to these frequencies; a typical one is the 25.175 MHz IQD Ltd. AEL Crystal Ltd manufactures 25 MHz oscillator modules in various packages. Crystal oscillator manufacturers will produce 26 MHz and 30 MHz oscillators to order. Of course, any clock source can be used, not just crystal oscillators.

Parallel interface

The parallel interfaces of the AD7470 and AD7472 are 10 and 12 bits wide, respectively. When both CS and RD are at logic low, the output data buffer is activated. At this point, the contents of the data register are placed on the data bus. Figure 10 shows the timing diagram for the parallel port.

Figure 11 shows that when CS and RD are always low. In this setup, once the busy line goes from high to low, the transition process is complete. Data is available on the output bus before the falling edge of BUSY.

It must be noted that the data bus cannot change state while the A/D is converting, as this would adversely affect the ongoing conversion. When the RD or CS line goes high, the data output line will again go to three states. Therefore, CS can be permanently fixed low, leaving the RD line to control conversion result access. Please refer to the VDRIVE section for output voltage levels.

Operating mode

The AD7470 and AD7472 have two possible modes of operation, depending on the state of the CONVST pulse at the end of the conversion, Mode 1 and Mode 2. There is a continuous clock on the clock pin.

Mode 1 (High Speed Sampling)

In this mode of operation, the CONVST pulse is driven high just before the end of the conversion (ie, before busy goes low) (see Figure 10). If the CONVST pin changes from high to low while BUSY is high, the conversion will be restarted. When operating in this mode, a new conversion should not be initiated until the busy state goes low for 135 ns. This acquisition time allows the track/hold circuit to accurately acquire the input signal. As mentioned before, reads should not be done during conversion. This mode contributes to the fastest throughput time of the AD7470/AD7472.

Mode 2 (Sleep Mode)

Figure 13 shows the AD7470/AD7472 in Mode 2 operation, where the ADC enters sleep mode after conversion. The CONVST line is brought low to initiate a conversion and remains low until the end of the conversion. If CONVST goes high and low again while BUSY is high, the conversion is restarted. Once busy goes from high to low, the CONVST line will check its state, and if low, the part goes into sleep mode. The device wakes up again on the rising edge of the CONVST signal. There is typically a 1 µs wake-up time after the rising edge of CONVST before the busy line goes high to indicate the start of a conversion. BUSY will go high only when CONVST goes low. During this wakeup time, the CONVST line can go from high to low, but after the 1 microsecond wakeup time, the conversion will still not start. Excellent power performance can be obtained in this mode of operation by waking up only the AD7470 and AD7472 to perform conversions.

burst mode

Burst Mode on the AD7470/AD7472 is a subsection of Mode 1 and Mode 2, and the clock is discontinuous. Figure 12 shows how the ADC works in burst mode in Mode 2. The clock only needs to be turned on during the conversion, at least 12 clock cycles for the AD7470 and 14 clock cycles for the AD7472. System power is saved because the clock is turned off during non-transition intervals. A busy signal can be used to pulse strobe CLK. The ADC will not start the conversion process until the first CLK goes high on the rising edge after busy. The clock needs to start less than two clock cycles from the active edge of CONVST, otherwise the INL will be poor; for example, if the clock frequency is 28MHz, the clock must start within 71.4ns of CONVST going low. In Figure 12, after the conversion is completed, the AD converter section will enter sleep mode and wake up again on the rising edge of CONVST; the user must pay attention to the wake-up time, as this will reduce the sampling rate of the ADC.

V drive

The VDRIVE pin is used as a voltage source for the output driver and is a separate power supply for AVDD and DVDD. The purpose of using a separate power supply for the output driver is that the user can vary the output high voltage VOH from the VDD supply to the AD7470/AD7472. For example, if AVDD and DVDD are using a 5v supply, the VDRIVE pin can be powered by a 3v supply. The ADC has better dynamic performance at 5v than at 3v, so operating the part at 5v, while still able to interface with the 3v part, pushes the AD7470/AD7472 onto the top bracket of high performance 10-bit/12-bit A/Ds. Of course the ADC can have its VDRIVE and DVDD pins tied together and be powered by a 3v or 5v supply.

All outputs are powered by VDRIVE. These are data output pins and busy pins. The CONVST, CS, RD, and CLK input signals are related to the DVDD voltage.

power ups

It is recommended that the user perform a dummy conversion after power up, as the first conversion result may not be correct. This also ensures that the part is in the correct operating mode. The recommended power-up sequence is as follows:

1>GND 4>Digital input

2>VDD 5>reference input

3 >VDRIVE 6>VIN

Power and Throughput

The two operating modes of the AD7470 and AD7472 will yield different power and throughput performance, Mode 1 and Mode 2; see the Operating Modes section of the datasheet for a detailed description of these modes. Mode 2 is the sleep mode of the part, which achieves the best power performance.

Mode 1

Figure 14 shows the AD7472 conversion sequence in Mode 1 using a throughput of 500 kSPS and a clock frequency of 26 MHz. With a 5 V supply, the current consumption of the part is 2 mA while switching, and the quiescent current is 650 µA. The conversion time of 531.66 ns contributes 2.658 mW to the total power dissipation by:

The contribution of the total power consumed for the remaining 1.468 microseconds of the loop is 2.38mw.

Therefore, the power dissipated in each cycle is:

Mode 2

Figure 15 shows the AD7472 conversion sequence in Mode 2 using a throughput of 500 kSPS and a clock frequency of 26 MHz. On a 5 V supply, the current consumption of the part is 2 mA while transitioning, while the sleep current is a maximum of 1 µA. The power dissipated during this power outage is negligible and therefore not worth considering in the total power graph. During the wake-up phase, the AD7472 will consume 650 microamps. The total power consumption is:

Figure 16 and Figure 17 show typical graphical representations of power versus throughput for the AD7472 in (a) Mode 1 @ 5V and 3V and Mode 2 @ 5V and 3V.

Grounding and Arrangement

The analog and digital power supplies are independent and fixed separately to minimize coupling between the analog and digital parts within the device. To complement the excellent noise performance of the AD7470/AD7472, attention must be paid to the PCB layout. Figure 25 shows the recommended connection diagram for the AD7470/AD7472.

All AD7470/AD7472 ground pins should be soldered directly to the ground plane to minimize series inductance. The AVDD, DVDD, and VDRIVE pins should be separated from the analog and digital ground planes. Large value capacitors decouple low frequency noise from analog ground, and small value capacitors decouple high frequency noise from digital ground. The power pins of all digital circuits should be disconnected from the digital ground plane. Using a ground plane separates sensitive analog components from noisy digital systems. The two ground planes should only be connected in one place and should not overlap to minimize capacitive coupling between them. If the AD7470/AD7472 are in a system with multiple devices requiring an AGND to DGND connection, the connection should still be made at only one point, the star ground, as close as possible to the AD7470/AD7472.

Noise can be minimized by applying a few simple rules in PCB layout: analog signals should be kept away from digital signals; fast switching signals such as clocks should use a digital ground shield to avoid radiating noise to other parts of the board, clocks Signals must not run near the analog inputs; avoid running digital lines under the device as these can couple noise onto the die; use the largest possible traces for the power lines of the AD7470/AD7472 to provide a low impedance path and reduce power effects of line faults; avoid digital and analog signal crossing, and place traces at right angles to each other on opposite sides of the board.

As shown in Figure 25, using multiple decoupling capacitors can further reduce noise on the analog power lines. The decoupling capacitors should be placed directly at the power supply entry of the printed circuit board, as close as possible to the power supply pins of the AD7470/AD7472. The same decoupling method applies to other integrated circuits on the PCB, with capacitor leads as short as possible to minimize lead inductance.

power supply

AVDD and DVDD require separate power supplies, but DVDD can share a power connection with AVDD if necessary. During normal operation, the digital power supply (DVD) must not exceed the analog power supply (AVDD) by more than 0.3 V.

Microprocessor interface between AD7470/AD7472 and ADSP-2185

Figure 26 shows a typical interface between the AD7470/AD7472 and the ADSP-2185. The ADSP-2185 processor can be used in one of two memory modes: full memory mode and host mode. The Mode C pin determines which mode the processor operates in. The interface in Figure 26 is set up to operate the processor in full memory mode, which allows full external addressing capabilities.

When the AD7470/AD7472 completes a conversion, a busy request for an interrupt via the IRQ2 pin. The IRQ2 interrupt must be set as edge sensitive in the interrupt control register. The DMS (Data Memory Select) pin latches the A/D address into the address decoder. The read operation starts here.

AD7470/AD7472 to ADSP-21065 Interface

Figure 27 shows a typical interface between the AD7470/AD7472 and the ADSP-21065L SHARC® processor. This interface is an example of one of three DMA handshake modes. The MSX control lines are actually three memory select lines. internal

ADDR25–24 are decoded to MS3-0, then these lines are asserted as chip selects. DMAR1 (DMA Request 1) is used in this setup as an interrupt to signal end of conversion. The rest of the interface is standard handshake operations.

AD7470/AD7472 to TMS320C25 Interface Figure 28 shows the interface between the AD7470/AD7472 and the TMS320C25. The CONVST signal can be applied from the TMS320C25 or an external source.

When the conversion is complete, the line interrupts the digital signal processor. The TMS320C25 does not have a separate RD output to directly drive the AD7470/AD7472 RD input. This has to be generated by the processor STRB and R/W output, with some glue logic added. The RD signal is strobed together with the MSC signal to provide the wait states required for the read cycle for correct interface timing. The following instructions are used to read conversions from the AD7470/AD7472: at D, ADC, where D is the data memory address and ADC is the AD7470/AD7472 address. Read operations must not be attempted during conversion.

AD7470/AD7472 to PIC17C4x interface

Figure 29 shows a typical parallel interface between the AD7470/AD7472 and the PIC17C42/43/44. The microcontroller sees the A/D as another memory device with its own specific memory address on the memory map. The CONVST signal can be controlled by a microcontroller or an external power supply. When the conversion is over, the busy signal provides an interrupt request to the microcontroller. The INT pin on the PIC17C42/43/44 must be configured to activate on a negative edge. PORTC and PORTD of the microcontroller are bidirectional and are used to address the AD7470/AD7472 and also to read 10-bit (AD7470) or 12-bit (AD7472) data. The OE pin on the PIC can be used to enable the output buffer on the AD7470/AD7472 and perform a read operation.

AD7470/AD7472 to 80C186 interface

Figure 30 shows the AD7470/AD7472 interfaced to the 80C186 microprocessor. The 80c186dma controller provides two independent high-speed DMA channels in which data transfers can occur between memory and I/O space. (The AD7470/AD7472 occupy one of the I/O spaces.) Each data transfer takes two bus cycles, one to fetch the data and the other to store the data.

After the AD7470/AD7472 completes the conversion, the busy generates a DMA request (DRQ1) for channel 1. As a result of the interrupt, the processor performs a DMA read operation, which also resets the interrupt latch. The DMA channel must be assigned enough priority to ensure that the DMA request is serviced before the next conversion is completed. This configuration is available for 6 MHz and 8 MHz 80C186 processors.

Dimensions

Dimensions are in inches and (mm).