feature

256 -bit +2.7V to + 30V single-supply operation; ±2.7V to ± 15V dual-supply operation; end-to-end resistance 10 kΩ, 50 kΩ, 100 kΩ; low temperature coefficient 35ppm/°C; power on preset to midscale; SPI compatible interface; automotive temperature range -40°C to +105°C; compact MSOP-10 (3 mm x 4.9 mm) package.

application

Programmable Gain and Offset; Programmable Power Supply; Industrial Actuator Control; LED Array Drivers; Audio Volume Control; Universal DAC Replacement; Mechanical Potentiometer Replacement.

Overview

The AD5290 is a low-cost, compact 2.9mm×3mm+30V/±15V, 256-bit digital potentiometer. This device performs with mechanical potentiometers or variable resistors, enhanced resolution, solid state reliability and superior low temperature coefficient performance. Wiper settings are available via an SPI-compatible digital interface. The wiper and fixed resistor endpoints are transferred with a digital code to the RDAC latch.

The AD5290 compact is available in 10k, 50k, and 100kΩ MSOP-10 packages. The AD5290 can operate from a single supply +2.7 V to +30 V or dual supplies ±2.7 V to ±15 V. All parts are guaranteed to operate in the automotive temperature range of -40°C to +105°C.

Note: The terms digital potentiometer and RDAC are used interchangeably.

operate

The AD5290 is a 256-bit digitally controlled variable resistance device that can be digitally controlled through an SPI interface. A built-in power-up preset places the wipers at mid-scale when powered up, which simplifies recovery from fault conditions at power-up.

Determine variable resistance and voltage

Rheostat mode operation

If only the W-to-B or W-to-A terminals are used as variable resistors, the unused terminals can be opened or shorted with W. This operation is called rheostat mode (Figure 3).

The nominal resistance (R) of the RDAC has 256 contact points, which are connected by the wiper terminal, and if R is considered, the B terminal contact is added. The 8-bit data in the RDAC latch is decoded to select one of 256 settings. Assuming a 10 kΩ part is used, the first connection to the wiper starts at the B terminal of data 0x00. Since the wiper contact resistance is 60Ω, this connection creates a minimum resistance of 60Ω between terminals W and B. The second connection is the first tap point, corresponding to 99Ω of data 0x01 (R=(1)×R/256+R), and so on. For each additional LSB data value, the wiper moves up the resistance ladder until the last tap point reaches 10020Ω ((255)×R/256+R). Figure 6 shows a simplified diagram of the equivalent RDAC circuit. The general equation for determining R is:

where: D is the decimal equivalent of the 8-bit binary code. RAB is end-to-end resistance. RW is powered by an internal switch.

Since a finite wiper resistance of 60° exists in zero order conditions, care should be taken to limit the current between W and B in this state to a maximum pulsed current of no more than 20 mA. Failure to do so may result in degradation or damage to the internal switch contacts.

Similar to a mechanical potentiometer, the RDAC resistor between wiper W and terminal A also produces a complementary resistor R. When using these terminals, the B terminal can be opened or shorted to W. Setting the resistance value of R starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general equation for this operation is:

The typical distribution of resistance tolerance among devices depends on the process lot and may have a tolerance of ±30%.

Potentiometer Mode Operation

If all three terminals are used, the operation is called potentiometer mode. The most common configuration is voltage divider operation (Figure 7).

Ignoring the effect of wiper resistance, the transfer function is simply:

A more precise calculation, including the wiper drag effect, yields:

If there is an applied voltage at terminal B, the transfer function becomes:

Unlike varistor mode operation, which has a higher absolute tolerance, potentiometer mode operation produces almost a ratio function of D/256, and the error due to the RW term is relatively small, so tolerance effects are almost canceled. Although the thin film step resistor R and the CMOS switch resistor R have very different temperature coefficients, the ratio adjustment also reduces the overall temperature coefficient effect to 5ppm/°C, except in low value codes where R dominates.

Potentiometer mode operation includes other operations such as op amp inputs, feedback resistor networks, and other voltage scaling applications. The A, W and B terminals can actually be input or output terminals as long as |V|, |V| and |V| do not exceed |V| and |V|.

SPI Compatible 3-Wire Serial Bus

The AD5290 contains a 3-wire SPI compatible digital interface (SDI, CS, and CLK). The 8-bit serial word MSB must be loaded first. The format of the words is shown in the table.

The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register.

Standard logic families work fine. CS should start high, and when it goes low, the clock loads data into the serial register on every positive clock edge (see Figure 3).

The data settings and data hold times in the specification table determine the effective timing requirements. The AD5290 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when CS returns logic high. If the dataword contains more than 8 bits, the extra MSB bits are ignored.

ESD protection

All digital inputs are protected with series input resistors and parallel Zener ESD structures, as shown in Figure 8 and Figure 9. This applies to the digital input pins SDI, CLK and CS.

Terminal voltage operating range

The AD5290 V and GND supplies define the boundary conditions for proper operation of the 3-terminal digital potentiometer. Supply signals that appear on terminals A, B, and W in excess of V or GND are clamped by internal forward-biased diodes (see Figure 10).

power-on sequence

Since the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 10), powering V-to-GND and V-to-GND before applying any voltage to terminals A, B, and W is important; otherwise, the diode will be forward biased energizing V inadvertently and potentially affecting the rest of the user's circuit. The ideal power-up sequence is as follows: GND, V, V, digital input, then V. The relative power-up order of V, V, V, and the digital inputs doesn't matter, as long as they power up relative to GND after V and V.

Layout and Power Bypass

It is good practice to design a layout with a compact, minimum lead length. Wires to the input should be as direct as possible with minimal wire length. The ground path should have low resistance and low inductance.

Also, for best stability, it is a good practice to bypass the power supply with a high quality capacitor. A 0.01µF to 0.1µF chip or chip ceramic capacitor should be used to bypass the device's power supply lines. A low ESR 1µF to 10µF tantalum or electrolytic capacitor should also be used at the power supply to minimize any transients and low frequency fluctuations (see Figure 4). Note that the digital ground should also be remotely connected to a point on the analog ground to minimize ground bounce.

Daisy Chain Operation

The serial data output pin (SDO) can be used to cascade multiple devices for simultaneous operation, see Figure 12. The SDO pin contains an open-drain N-Ch FET that requires a pull-up resistor. The user needs to bind the SDO pin of one package to the SDI pin of the next package. If many devices are daisy-chained, the user may need to increase the clock period to accommodate the time delay introduced by the pull-up resistors and capacitive loading of the SDO-SDI interface, see Figure 12.

If two AD5290s are daisy-chained, a total of 16 bits of data are required. The first 8 bits go into U2, and the last 8 bits go into U1. CS should be held low until all 16 bits are in their respective serial registers. Then pull CS high to complete the operation.

Dimensions