feature

8 differential analog inputs; 1VPP differential input range; internal/external voltage reference; analog/digital power supply 1.8V; digital I/O power supply 1.8V/3.3V; integral nonlinearity: ±0.8LSB; signal-to-noise ratio: 58dB, fIN =20MHz; spurious free dynamic range: 72dB at; fIN=20MHz; 794mW power dissipation; individual channel powered down; 257-lead, 0.8 ball pitch, plastic MicroSTAR BGA 8482 ; (16•16mm).

application

Portable Ultrasound; Portable Instrument.

illustrate

The ADS5120 is a low power, 8-channel, 10-bit, 40MSPS CMOS analog-to-digital converter (ADC) that operates from a single 1.8V supply and provides both 1.8V and 3.3V digital I/O flexibility. A single-ended input clock is used to sample up to eight analog differential input channels simultaneously. A flexible duty cycle adjustment circuit (DCASEL) allows the use of clock duty cycles other than 50%. A single spare pin allows the user to turn off any number of ADCs. A sample and hold stage is added before the ADC, and a digital error correction circuit is used to generate the final digital code. The internal reference can be bypassed and an external reference used to meet the application's accuracy and temperature drift requirements. The 10-bit parallel bus on eight channels has tri-state outputs.

The speed, resolution, and low power consumption of the ADS5120 make it ideal for applications requiring high-density signal processing in low-power environments.

The ADS5120 is characterized for operation from 0°C to 70°C.

application information

Inverter operation

The ADS5120 is an 8-channel simultaneous sampling ADC. Its low power consumption (100mW/channel) and high sampling rate of 40MSPS are achieved by a state-of-the-art switched capacitor pipeline structure built on an advanced low voltage CMOS process. The ADS5120 is primarily powered by a single +1.8V supply. For added interface flexibility, the digital I/O power supply can be set to +1.8V or 3.3V. The ADC core for each channel consists of 10 pipeline stages. One digit is generated every 10 levels. Using rising and falling clock edges to propagate samples through the pipeline every half clock, for a total of five clock cycles. Two additional clock cycles are required to pass the sample data through the digital error correction logic and the output latch. Therefore, the total pipeline delay or data delay is 7 clock cycles. Since a common clock controls the timing of all eight channels, the analog signal and simultaneously updated data on the parallel port are sampled simultaneously.

analog input

The analog input of each channel of the ADS5120 consists of a differential track-and-hold amplifier implemented using switched capacitor techniques, as shown in Figure 1. This differential input topology and closely matched capacitors yield high levels of AC performance up to high sampling rates.

When the track and hold amplifiers are in track mode, the conversion current charges and discharges the input sampling capacitor. The input impedance of the ADS5120 is also a function of the sampling rate. As the sampling frequency increases, the input impedance decreases linearly at a rate of 1/fs. For most applications, this does not represent a limitation, as the impedance is kept relatively high, for example, around 83KΩ at a maximum sampling rate of 40MSPS. For applications using an op amp to drive an ADC, it is recommended to add a series resistor, typically 10Ω to 50Ω, between the amplifier output and the converter input. This will isolate the capacitive input of the converter from the driver and avoid potential gain peaking, or instability.

input bias

The ADS5120 operates from a +1.8V analog supply and requires each analog input (AIN+, AIN-) to be externally biased by an appropriate common-mode voltage. For example, with a common-mode voltage of +1V, a 1VPP full-scale differential input signal will swing symmetrically around +1V, or between 0.75V and 1.25V. This is determined by two reference voltages, the upper reference voltage (REFT) and the lower reference voltage (REFB). Typically, the input common-mode level is related to the reference voltage, defined as (REFT+REFB)/2. This reference midpoint is located at the CML pin and can be used directly for input biasing purposes. The voltage at CML will be assumed to be the midpoint of the internal or external reference operation. In any case, it is recommended to bypass the CML pin with a ceramic 0.1µF capacitor.

input resistance

Since the switched capacitor input track-and-hold amplifier is used, the input impedance of the ADS5120 is effectively capacitive, and the drive power supply needs to provide enough.

Driving analog inputs with single-ended differential

The analog inputs of the ADS5120 allow single-ended or differential drive. Differential operation of the ADS5120 requires an input signal consisting of an in-phase part and a 180° out-of-phase part applied simultaneously to the inputs (AIN+, AIN–). The full-scale input range of the ADS5120 is defined by the reference voltage according to FSR = 2 x (Reference - Reference B). For a typical 1VPP range, the differential input configuration only requires each input to see a signal swing of 0.5VPP. Operating the converter in a single-ended configuration requires applying a full 1VPP swing to the selected input. Differential operation has a number of advantages that will help achieve the best dynamic performance of the ADS5120 in most applications:

(1) The signal swing is half of the swing required for single-ended operation, so while maintaining the good linear performance of the signal source, the implementation requirements are lower.

(2) The reduced signal swing allows the interface circuit to have a larger headroom, so the most suitable driver op amp can be selected more widely.

(3) Minimize even harmonics.

(4), based on the common mode input rejection of the converter, improve the noise immunity.

For single-ended mode, the signal is applied to one of the inputs, while the other input is biased by a DC voltage to the desired common-mode level. The two inputs are identical in impedance and performance. However, applying the signal to the complementary input (AIN-) instead of the AIN+ input will reverse the direction of the input signal relative to the output code. For example, this may help if the input driver is operating in reverse mode using the input AIN, as the signal input will restore the phase of the signal to its original direction.

Enter driver configuration

Transformer coupled interface

If the application requires signal conversion from a single-ended source to drive the ADS5120 differentially, an RFtransformer can be a good solution. The selected transformer must have a center tap to apply the common-mode DC voltage required to bias the converter input. Grounding the center tap will create a differential signal swing on the secondary winding. Consider a step-up transformer that utilizes signal amplification without introducing other sources of noise. Furthermore, reduced signal swing from the source can result in improved distortion performance.

The differential input configuration offers the significant advantage of obtaining good SFDR performance over a wide input frequency range. In this mode, both inputs of the ADS5120 (AIN+ and AIN-) see matched impedances. Figure 2 shows a schematic diagram of the proposed transformer-coupled interface circuit. The component values of the RC low pass can be optimized according to the desired roll frequency.

Single-Ended AC-Coupled Drivers

The circuit of Figure 3 shows an example of driving the input of the ADS5120 in a single-ended configuration. The signal is AC coupled between the driver amplifier and the converter input (AIN+). This allows the desired common-mode voltage to be set separately for the ADC and op amp. A single-supply op amp is biased by two resistors connected at its non-vertical input terminals on the mid-supply. Connect each input to the CML pin to provide the required common-mode voltage to the inputs of the ADS5120. Here, the two resistors are equal in value, ensuring that the input sees closely matched source impedances. If the op amp has a disable function, it can easily be connected to the power-down pin of the ADS5120 channel (STBY). In the circuit example shown in Figure 3, the OPA355 EN pin is directly connected to the STBY pin, allowing a power-down mode for the entire circuit. Other suitable op amps for single-supply driver applications include the OPA634, OPA635, or OPA690, for example.

DC coupled interface with difference amplifier

Differential I/O amplifiers can simplify drive circuits that require input-to-DC coupling. Flexible configuration, such an amplifier can be used for single-ended to differential conversion, allowing the signal to be amplified and filtered before the ADC. Figure 4 shows one possible circuit implementation using the THS4130 amplifier. Here, the amplifier operates with a gain of +1. The common-mode voltage on the CML pin can be conveniently connected to the amplifier VOCM pin to set the input bias required by the ADS5120.

For proper operation of the ADS5120 and its reference signal, an external 6.19kΩ resistor must be connected from the IREFR pin to analog ground (AGND) (as shown in Figure 5). When a 1% resistance tolerance is sufficient, deviations from this resistance value will result in altered and degraded performance.

To ensure proper operation in any reference configuration, robust bypassing must be provided on all reference pins to keep clock feedthrough to a minimum. Figure 5 shows the recommended decoupling scheme. Good performance can be obtained with low inductance ceramic capacitors of 0.1µF. Depending on the application, adding tantalum capacitors (1µF to 10µF) can result in improved performance. All bypass capacitors should be placed as close as possible to their respective pins.

The internal reference circuit of the ADS5120 consists of a bandgap reference voltage source, upper and lower reference drivers, and a resistance reference ladder diagram. The corresponding reference pins are REFT, REFB, CML, IREFR, BG, and PDREF. To enable internal references, pin PDREF must be logic low = 0. Also, the bandgap pin BG must have a 100kΩ pull-up resistor to AVDD and should be separated from the 1µF capacitor. Reference circuits provide reference voltages for each of the eight channels.

The reference buffer can be used to supply up to 1 mA to external circuits (sink and source). The common mode level output pin, CML, represents the midpoint of the internal resistance ladder and is the unbuffered node. Loading this pin should be avoided as this will result in reduced converter linearity.

Use external references

For greater design flexibility, the internal reference can be disabled and an external voltage reference used. For applications that require higher accuracy or improved temperature performance, an external reference can be considered. Especially in multi-channel applications, using a common external reference signal helps to better match the full-scale range between converters.

Setting the ADS5120 to external reference mode requires setting the PDREF pin high. Also, pins BG and REFT must be connected together (as shown in Figure 6). The common-mode voltage at the CML pin will be maintained at approximately the midpoint of the applied reference voltage, according to CML(VRFT-VReFB)/2. When the ADS5120 is operating in external reference mode, the internal buffer amplifiers for REFT and REFB are disabled. The external reference circuit must be designed to drive the internal reference ladder (80Ω) located between the REFT and REFB pins. For example, setting REFT=+1.25V and REFB=+0.75V will require a current drive capability of at least 0.5V/80Ω=6.25mA. As long as the value of the external top reference (REFTEXT) remains within the range of +1.15V to +1.35V and the external bottom reference (REFBEXT) remains within the range of +0.65V to +0.85V (as shown in Figure 7), the external reference can be changed.

Digital Input Output Clock Input

The clock input is designed to operate at +1.8V or +3.3V CMOS logic levels. The clock circuit is internally connected to the DRVDD power supply. Therefore, the input high and low levels will vary depending on the applied DRVDD supply; see the DC Characteristics table. Since both edges of the clock are used in this pipelined ADC, the ideal clock would be a square wave logic signal with a 50% duty cycle.

Since this situation is not easily satisfied, the ADS5120 has an internal clock adjustment circuit that can be activated through the duty cycle adjustment pin (DCASEL).

The DCASEL pin is a logic input whose logic level is related to the DVD power supply (+1.8V only):

a), DCASEL = low (GND); in this mode, the clock condition circuit is disabled. Use this setting if the applied clock signal is a square wave clock with a 50% duty cycle, or if the duty cycle remains in the range of 48% to 52%.

b), DCASEL = high (DVD D); in this mode, the clock adjustment circuit is enabled. Use this setting if the applied external clock signal is a square wave clock that does not meet the above criteria but has a duty cycle in the range of 30% to 70%.

Minimum sample rate

The pipelined structure of the ADS5120 uses switched capacitor technology in the internal rail and hold stages. During each clock cycle, a charge representing the level of the captured signal moves within the ADC pipeline core. High sampling rates require the use of very small capacitor values. To keep the droop error low, the capacitor needs a minimum refresh rate. In order to maintain full accuracy of the collected sample charge, the sampling clock of the ADS5120 should not fall below the specified minimum 1MSPS.

Data output format

The output data format of the ADS5120 is straight offset binary (SOB) code. Tables 1 and 2 show the output encoding for single-ended differential signals. For all data output channels, the msb is on the D9x pin.

Digital output loading

Reducing capacitive loading on the digital outputs is important for optimum performance. The total load capacitance usually consists of two sources: the next stage input capacitance and parasitic/printed circuit board (PDB) capacitance. It is recommended to keep the total capacitive loading on the data lines as low as possible (≤15pF). A higher capacitive load will result in a higher dynamic current when the digital output changes state. Large current surges can cause feedback into the analog portion of the ADS5120 and affect performance. If necessary, use external buffers or latches close to the converter output pins to minimize capacitive loading. The recommended device is the SN74AVC16827 (20-bit buffer/driver), which is a member of the Advanced Very Low Voltage CMOS Logic Family (AVC). Using such a logic device also provides the added benefit of isolating the ADS5120 from any digital noise activity on the bus, which couples back into high frequency noise. Using series resistors (≤100Ω) in the data lines may also help in some applications. This will provide current limiting and reduce any existing overshoot or undershoot.

output enabled

The ADS5120 provides an output enable pin (OE) to control the digital outputs of all channels simultaneously. A low (L=0) level on an OE pin will activate all channel inverters to work normally. Setting the OE pin high (H=1) will disable or tri-state all output channels. Note that the OE pin does not have an internal pull-up resistor, so an application needs to be defined. The timing relationship between operating experience and output bus enable/disable time is shown in the timing diagram.

power-on sequence

Ideally, the three mains of the ADS5120 should be used and boosted simultaneously. If this cannot be ensured, the following power-up sequence is recommended:

1. Average depreciation rate (+1.8 typical value)

2. DVD drive (+1.8 type)

3. DRVDD (+3.3 type)

The clock signal should also be at the appropriate logic levels during power-up of the ADS5120. Deviations from this power-up sequence may cause the device to enter a mode where the digital outputs do not approach the full specified output levels.

Power off (standby)

The ADS5120 has a power-down capability for each of the eight channels. Marked as a spare pin, the normal operating mode is when this pin is tied to logic high (H=1). If the corresponding STBY pin is tied to logic low (L=0), the selected ADC channel will be in power-down mode. The logic level of the STBY pin depends on the DRVDD power supply. The power-down function controls the internal bias node, so any data present in the converter pipeline will be invalid. This is independent of whether the clock remains applied during power down. After power-up, new valid data will be available after at least seven clock cycles. It is worth noting that the STBE pin is not used to dynamically multiplex between the eight channels of the ADS5120.

Digital output drive power

The ADS5120 uses a dedicated power supply connection for the output logic driver, DRVDD, and a digital driver ground connection labeled DRGND.

When the voltage at DRVDD is set to +3.3V or +1.8V, the output logic levels will be set accordingly, allowing the ADS5120 to connect directly to the selected logic family. The output stage is designed to provide enough current to drive various logic families. However, it is recommended to use the ADS5120 and a +1.8V drive supply. This will reduce power dissipation in the output stage due to the lower output swing and reduce current glitches on the power lines that could otherwise affect the converter's AC performance. In some applications, it may be advantageous to use additional capacitors or pi filters to separate the DRVDD supply.

Grounding and Decoupling

Proper grounding and bypassing, short lead lengths, and use of ground planes are especially important for high-frequency designs. Multilayer printed circuit boards are recommended for optimal performance as they offer significant benefits such as minimizing ground impedance, separating signal layers by ground planes, etc. The ADS5120 should be considered an analog component. Whenever possible, the power pins should be powered by the analog supply. This will ensure the most consistent results, as digital power lines tend to carry high levels of noise that would otherwise couple into the converter and degrade achievable performance. The ground pins should be connected directly to the analog ground plane covering the PCB area under the converter. When designing the layout, it is important to keep the analog signal traces separate from any digital lines to prevent noise coupling onto the analog signal paths. Due to its high sampling rate, the high frequency current transients and noise (clock feedthrough) generated by the ADS5120 are fed back to the power and reference lines. This requires all supply and reference pins to be fully bypassed. In most cases, a 0.1µF ceramic chip capacitor per pin is sufficient to maintain low impedance over a wide frequency range. Their effectiveness is largely dependent on proximity to individual supply pins. Therefore, they should be placed as close as possible to the power pins. Also, larger bipolar capacitors (1µF to 22µF) should be placed on the PCB near the converter circuit.

PCB layout with MICROSTAR-BGA package

The ADS5120 is packaged in a polyimide film based chip scale package (CSP). Like most CSPs, solder alloy balls are used as the interconnect between the package substrate and the PCB to which the package is soldered. For more information on these packages, see literature number SSYZ015B, MicroStar BGA Package Reference Guide, which describes specific issues to consider when integrating MicroStar BGA packages into PCB designs.

the term

analog bandwidth

Simulate the input frequency at which the spectral power of the fundamental frequency (determined by FFT analysis) is reduced by 3dB.

Aperture delay

Delay between the 50% point of the rising edge of the clock and the instant the analog input is sampled.

Aperture uncertainty (jitter)

Sample-to-sample variation of aperture delay.

Effective Number of Bits (ENOB)

ENOB is calculated from the measured SINAD with the following formula:

gain error

Gain error is the deviation between the actual difference between the first and last transcoding and the ideal difference between the first and last transcoding.

Gain matching

Variation of gain error between adjacent channels.

Harmonic Distortion, sec

The ratio of the rms signal amplitude of the second harmonic component to the rms value, expressed in dBc.

Harmonic Distortion, 3rd

The ratio of the rms signal amplitude to the rms value of the third harmonic component, expressed in dBc.

Intermodulation Distortion

Two-tone IMD is the decibel ratio of the input tone to the worst third-order (or higher) intermodulation product. A single input tone level is -6.5dB full scale, and its envelope is -0.5dB full scale.

Offset error (zero-scale error)

The first conversion should occur when the analog value is above 1/2 LSB of negative full scale. Offset error is defined as the deviation of the actual transition point from this point.

offset match

Variation in offset error between adjacent channels.

power supply rejection ratio

Ratio of input offset voltage change to supply voltage change.

Signal to Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set to 0.5dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding DC.

Signal-to-noise ratio (no harmonics)

The ratio of the rms signal amplitude (set to 0.5dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and DC.

Spurious Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral components. Peak spurious components may or may not be harmonics. Can be reported in dBc (that is, decreases as signal level decreases) or dBFS (always relative to converter full scale).