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Low startup current (100µA typical) Low operating current (2.5mA typical) Low total harmonic distortion and high power factor 4800 -ic/" title=" ML4800 Product Specifications, Documentation and Sourcing Information" target=" _blank">ML4800’s Pin Compatible Upgraded Average Current, Continuous or Discontinuous Boost, Leading Edge PFC Slew Rate Enhanced Transconductance Error Amplifier for Ultra-Fast PFC Response Internal Synchronous Leading Edge Power Factor Correction and Pulling PWM, Reduced Storage Capacitor The ripple current between the PFC and the PWM section is PWM configurable for current mode or voltage mode

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Additional PWM Part Foldback Current Limiting 20V BiCMOS Process at 2.25V, VIN Normal, Guaranteed Turn-On PWM VCC OVP Comparator, Low Power Detect Comparator Current Feedback to Improve Noise Gain Modulator Immunity to Power-Down Control, Overvoltage Protection, UVLO, Soft-Start, Reference Normal Available in 16-DIP, 16-SOIC (Wide) Packages

application

desktop computer power supply

internet server power

Uninterruptible Power Supply (UPS)

battery charger

DC motor power supply

monitor power

Telecom System Power

Distributed Power

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FAN4800 is a power factor correction controller, switching power supply. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and switching FETs, and produces full IEC-1000-3-2 compliance. Intended as a BiCMOS version of the industry standard ML4800, the FAN4800 includes a pulse width modulator (PWM) for implementing leading edge, average current, boost power factor correction and trailing edge. A gate driver capable of 1A will require external driver circuitry. Low power requirements increase efficiency and reduce component cost. The overvoltage comparator shuts down the PFC section if the load decreases suddenly. The PFC section also includes peak current limiting and input voltage eyebrow protection. The PWM section operates in current or voltage mode, up to 250kHz, and includes a precise 50% duty cycle limit to prevent transformer saturation. Fan 4800 is included to provide short circuit protection.

Absolute Maximum Ratings

"Absolute Maximum Ratings" are values at which the safety of the device cannot be guaranteed. Devices should not operate within these limits. The parameter values defined in the Electrical Characteristics table are not guaranteed at Absolute Maximum Ratings.

Electrical Characteristics

Unless otherwise noted, these specifications apply: VCC=15V, RT=52.3KΩ, CT=470pF, TA=-40°C to 125°C.

Electrical Characteristics (continued)

Unless otherwise noted, these specifications apply: VCC=15V, RT=52.3kΩ, CT=470pF, TA=-40°C to 125°C.

Electrical Characteristics (continued)

Unless otherwise noted, these specifications apply: VCC=15V, RT=52.3kΩ, CT=470pF, TA=-40°C to 125°C.

notes:

1. Although this parameter is guaranteed by design, it is not 100% production tested.

2. Includes all bias currents for other circuits connected to the VFB pin.

3. Gain=K×5.375V; K=(ISENSE–IOFFSET)×[IAC×(VEAO–0.625)]-1; VEAO(MAX.)=6V

Function description

The Fan 4800 consists of a controlled average current, continuous power factor correction (PFC) front end and a synchronous pulse width modulator (PWM) back end. Available in current or voltage mode. In voltage mode, the output bus from the PFC can be used to improve PWM line supervision. In either mode, the PWM stage uses traditional trailing edge duty cycle modulation. This patented leading/trailing edge modulation results in usable PFC error amplifier bandwidth and can significantly reduce the size of the PFC DC bus capacitors. Synchronization of PWM to PFC simplifies control of ripple induced PWM compensation PFC output capacitors (PWM input capacitors). The PWM portion of this fan 4800 is at the same frequency as the power factor correction. In addition to power factor correction, the FAN4800 has many built-in protection functions. These include soft-start, power factor correction overvoltage protection, peak current limit, overvoltage protection, duty cycle limit and undervoltage lockout (UVLO). Power Factor Correction Power factor correction treats the nonlinear load as a resistive load on the AC line. For resistors, the current drawn from this line is related to the line voltage, so the power factor is 1. A common nonlinear load is the power supply, which is fed from the line using a bridge rectifier and capacitive input filter. The peak charging effect, which occurs on the input filter capacitors in these supplies, produces brief high-amplitude current pulses that flow from the supply line instead of sinusoidal currents that are in phase with the line voltage. Such supplies have less than one power factor to the line (ie, they contribute to the frequency of the supply line appearing at the input).

If the input current drawn by such a power supply (or any non-linear load) can cause it to instantaneously track the input voltage amplitude, it is a resistance to the power supply. To keep the input current consumption of the device pulling power from the AC line with the input voltage, the device must be prevented from loading the line unless it is proportional to the instantaneous line voltage. To achieve this the FAN4800 uses a boost mode DC-DC converter. The input to this converter is the full-wave rectified AC line voltage. No batch screening rectifier is applied after the bridge, so the input voltage range of the boost converter (twice the frequency) is from zero volts to the peak of the AC input and back to zero. By forcing the boost converter to meet both conditions, it ensures that the slave supply line is proportional to the input line voltage. One of the conditions is that the boost converter must be set above the peak line voltage. A common value is 385VDC allowing 270VAC rms for high voltage lines. The second condition is that the instantaneous voltage from any given must be proportional to the line voltage. Building a suitable voltage control loop for the converter, which in turn drives the current error amplifier and switching output driver, meets the first requirement above. The second requirement is to control the line voltage loop of the output by using rectified AC to adjust the voltage. This modulation causes the current error amplifier to command the power stage current to directly vary the input voltage. To prevent ripple at the output of the boost circuit (usually 10 volts AC at the level of about 385 volts DC), the bandwidth voltage loop is kept deliberately low from the introduction of distortion through the voltage error amplifier. The final improvement is to adjust the overall gain of the PFC section to be proportional to 1/VIN to linearize the transfer function of the system to the AC input voltage. Because the boost converter in the Fan 4800 PFC is current averaging, slope compensation is not required.

1. PFC segment

1.1 The gain modulator diagram shows the fan 4800. The gain modulator is a PFC because the circuit block controls the current loop to line voltage waveform and frequency, rms line voltage and power factor corrected output voltage. There are three inputs to the gain modulator: the current representing the instantaneous input voltage (amplitude and waveform) to the power factor corrected AC input sine wave converted to a proportional current through a resistor and then input to the gain modulator at the IAC. Sampling the current in this way minimizes the ground noise transition environment required for high power switching power supplies. The gain modulator responds linearly to current.

2. A voltage proportional to the long-term rms AC line, scaled and filtered from the rectified line voltage. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to VRMS (except for unusually low VRMS values, where special gain profiles can limit the power dissipation of circuit elements under severe power-down conditions). The relationship between VRMS and gain is called K as shown.

3. The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to this change in voltage. The output of the gain modulator is the current signal, in the form of a full-wave sine wave at twice the frequency of the straight line. This current is applied at the virtual ground at the (negative) input of the current error amplifier. In this way, the gain modulator forms a reference error loop for the current and ultimately controls the instantaneous current consumption of the power factor correction circuit from the power line. The output form of the general gain modulator is:

More precisely, the output current of the gain modulator is given by:

where K is in V-1.

Note that the output current of the gain modulator is limited to about 228.57µA and the maximum output voltage. The gain modulator is limited to 228.57µA x 3.5K = 0.8V. This 0.8V also determines the maximum input power. However, IGAINMOD cannot be used directly from yes. ISENSE=IGAINMOD – IOFFSET and IOFFSET can only be used when VEAO is less than 0.5V and IGAINMOD is 0A. A typical IOFFSET is about 60µA. 1.2 Selecting the IAC pin The RACIAC pin is the input to the gain modulator. IAC is also the current mirror input and requires the current input. Proper selection of the resistor RAC provides a good sine wave current source from the line voltage, helping to program the maximum input power and minimum input line voltage. RAC=VIN peak x 7.9K. For example, if the minimum row voltage is 80VAC, RAC=80 x 1.414 x 7.9K=894kΩ. 1.3 Current Error Amplifier The output of the current error amplifier controls the PFC duty cycle to maintain the average current through the boost cycle as a linear function of the inductor line voltage. At the inverting input of the current error amplifier, the total current output to the current gain modulator is the result of the negative voltage applied to the Isen pin. A negative voltage on ISENSE means that all current flowing in the power factor correction circuit is fed into the terminals of the bridge rectifier from the current sense resistor in series with the negative terminal. The inverting input of the current error amplifier is a virtual ground. Considering this fact, and the polarity of the duty cycle modulator is inside the PFC, a positive current increase of the gain modulator causes the output stage to increase its duty cycle until the voltage on ISENSE is negative enough to cancel this increase in current. Likewise, if the gain modulator output is reduced, the output duty cycle is reduced to achieve a lower negative voltage on the ISENSE pin.

1.4 Cycle-by-cycle current limiter and selection of RS as part of the current feedback loop The ISENSE pin is a direct input to the cycle-by-cycle current PFC segment limiter. If the input voltage to this pin is below -1V, the output of the PFC is disabled until the clock pulse resets the protection flip-flop at the beginning of the next PFC power cycle. RS is the sense resistor of the PFC boost converter. During steady state, the line input current x RS is equal to IGAINMOD x 3.5 km. Due to the maximum output voltage of the gain modulator IGAIMMOD max X 3.5K = 0.8V state, the RS x line input current is limited below 0.8V. Therefore, to choose RS, use the following formula:

For example, if the minimum input voltage is 80VAC and the maximum input rms power is 200W, RS=(0.8V x 80V x 1.414)/(2 x 200)=0.226Ω.

1.5 Power Factor Correction Overvoltage In FAN4800, the PFC OVP comparator is used to protect the power supply circuit from excessive voltage when the load changes suddenly. A resistor divider feeds VFB from the high voltage DC output of the PFC. When the voltage on VFB exceeds 2.78V, the PFC output driver is turned off. The PWM part continues to work. The OVP comparator has 280mV of hysteresis and the PFC does not restart until the VFB voltage drops below 2.50V. VCC OVP can also be protected as redundant PFC OVP. The VCC OVP threshold is 17.9V with 1.5V hysteresis.

1.6 Error Amplifier Compensation The PWM load of the PFC can be modeled as a negative resistance because the input current decreases due to pulse width modulation. This response determines an appropriately compensated transconductance error amplifier for both. The figure shows the types of compensation networks most commonly used in voltage and current error amplifiers, and their respective return points. This current loop compensation returns to VREF to produce a soft-start characteristic on the PFC: as the reference voltage increases from 0V, it produces a differential voltage on IEAO, preventing the PFC from immediately requiring a full duty cycle boost converter. 1.7 The power factor correction voltage loop responds to the error amplifier in the compensation voltage loop. Optimizing transient interaction response and stability requires the error amplifier open loop crossover frequency to be half the line frequency, or 23Hz for a 47Hz line (minimum expected international mains frequency). Gain vs. Input Voltage The voltage error amplifier (VEAO) of the FAN4800 has a specially shaped nonlinearity that allows it to operate under steady-state conditions with the transconductance error amplifier at a local minimum. Rapid disturbances on the line or load conditions cause the input voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the voltage error of the transconductance amplifier increases significantly, as shown in Figure IV. This improves the gain-bandwidth product of the voltage loop, resulting in a faster voltage loop response to such disturbances as the traditional linear gain characteristic.

The voltage loop gain is given by:

ZC: Compensation network for the voltage loop. GMV: Transconductance of veal. PIN: Average Power Factor Corrected Input Power. Version 2 OUTDC: PFC boost output voltage (typical design value is 380V). CDC: PFC boost output capacitor. 1.8 Power Factor Correction Current loop current amplifier (IEAO) compensation is similar to voltage error amplifier (VEAO) compensation with the exception of crossover frequency selection. The crossover frequency of this current amplifier should be at least ten times that of the voltage amplifier to prevent interaction with the voltage loop. It should also be limited to less than one sixth of the switching frequency, eg. , 100kHz switching frequency is 16.7kHz. The current loop gain is given by: