feature

8 analog-to-digital converters (ADCs) in one package; 93.5 mW ADC power per channel (50 msec/sec); SNR = 73 dB (to Nyquist); ENOB = 12 bits; SFDR=84 dBc (to Nyquist); good linearity; DNL=±0.4 LSB (typ.); INL=? 1.5 LSB (typical) serial LVDS (ANSI-644, default); low power, reduced signal option (similar to IEEE 1596.3); data and frame clock outputs; 325MHz , full power analog bandwidth; 2V pp input voltage range; 1.8V power supply operation; serial port control; full-chip and single-channel power-down modes; flexible bit positioning; built-in and custom digital test pattern generation; programmable clock and data calibration; programmable output resolution; standby mode.

application

Medical Imaging and Nondestructive Ultrasound; Portable Ultrasound and Digital Beamforming Systems; Quadrature Radio Receivers; Diversity Radio Receivers; Tape Drives; Optical Networks; Test Equipment.

General Instructions

AD9252 is an 8-digit, 14-bit, 50ms/sec ADC with on-chip sample-and-hold circuit, low design cost, low power consumption, small size, and easy use. Operating at slew rates up to 50msps, it is optimized for excellent dynamic performance and low power consumption in applications where small package size is critical.

The ADC requires a 1.8v supply and LVPECL-/CMOS-/LVDS compatible sample rate clock for full performance operation. Many applications do not require external references or driver components.

The ADC automatically multiplies the sample rate clock by the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling to send new output bytes are provided. Single channel power down is supported and typically consumes less than 2 mW when all channels are disabled.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. Available digital test patterns include built-in deterministic and pseudo-random patterns, as well as custom user-defined test patterns entered via the Serial Port Interface (SPI).

The AD9252 uses a RoHS-compliant 64-lead LFCSP. Specified over the industrial temperature range from -40°C to +85°C.

Product Highlights

1. Small footprint. There are eight ADCs in a small package.

2. Low power 93.5 mW per channel at 50 msec per second.

3, easy to use. The Data Clock Out (DCO) operates up to 350MHz and supports Double Data Rate (DDR) operation.

4. User flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.

5. Pin compatible series. This includes the AD9212 (10-bit) and AD9222 (12-bit).

theory of operation

The AD9252 architecture consists of a pipelined ADC divided into three sections: 4-bit first stage, 8 1.5-bit stages, and 3-bit flash. Each stage provides enough overlap to correct flash errors in the previous stage. In the digital correction logic, the quantized outputs from each stage are combined into a final 14-bit result. The pipelined architecture allows the first stage to use a new input sample operation, while the remaining stages use the previous sample operation. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline (excluding the last stage) consists of a low-resolution flash ADC connected to a switched-capacitor DAC and residual amplifiers (eg, multiplying digital-to-analog converters (MDACs)) between the stages. The residual amplifier amplifies the difference between the reconstructed DAC output and the flash input in the next stage of the pipeline. One bit redundancy is used per stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The output scratch block aligns the data, corrects errors, and passes the data to the output buffer. The data is then serialized and aligned to the frame and data clocks.

Analog Input Considerations

The analog input of the AD9252 is a differential switched capacitor circuit designed to process differential input signals. The circuit can support a wide common-mode range while maintaining good performance. The input common-mode voltage of the intermediate supply minimizes signal-dependent errors and provides optimum performance.

A clock signal alternates the input circuit between sample mode and hold mode (see Figure 33). When the input circuit switches to sampling mode, the signal source must be able to charge and stabilize the sampling capacitor within half a clock cycle. A small resistor in series with each input helps reduce peak transient currents injected from the output stage of the drive source. Additionally, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce the high differential capacitance at the analog input and thus achieve the maximum bandwidth of the ADC. When driving the converter front end at high frequencies, a low-Q inductor or ferrite bead is required. A shunt capacitor or two single-ended capacitors can be placed at the input to provide a matched passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. For more information, see AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; AN-827 Application Note, Resonance Methods for Interfacing Amplifiers with Switched-Capacitor ADCs; and the Analog Dialogue article "Transformers for Wideband A/D Converters" Coupling Front Ends" (Volume 39, April 2005). In general, the exact value depends on the application.

The analog inputs of the AD9252 have no internal dc bias. Therefore, in AC-coupled applications, the user must provide this bias externally. Set the device to V=AVDD/2 for best performance, but the device can operate over a wider range with reasonable performance, as shown in Figure 34 and Figure 35.

For best dynamic performance, the source impedances driving VIN+x and VIN-x should be matched so that the common-mode regulation errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. Internal reference buffers generate positive and negative reference voltages REFT and REFB, respectively, which define the span of the ADC core. The output common mode of the reference buffer is set to "medium supply", and the reference voltage and reference voltage range are defined as:

As can be seen from these equations, the REFT and REFB voltages are symmetrical with respect to the mid-supply voltage, and by definition, the input span is twice the value of the VREF voltage.

Maximum SNR performance is achieved by setting the ADC to maximum span in differential configuration. In the case of the AD9252, the maximum input span available is 2V pp.

Differential Input Configuration

There are several ways to drive the AD9252 actively or passively; however, the best performance is obtained by driving the analog inputs differentially. For example, using the AD8334 differential driver to drive the AD9252 provides excellent performance and a flexible ADC interface for baseband applications (see Figure 39). This configuration is commonly used in medical ultrasound systems.

For applications where signal-to-noise ratio is a critical parameter, differential transformer coupling is the recommended input configuration (see Figure 36 and Figure 37) because the noise performance of most amplifiers is not sufficient to match the true performance of the AD9252. Regardless of the configuration, the value of the shunt capacitor C depends on the input frequency and may need to be reduced or removed.

Single-ended input configuration

In cost-sensitive applications, single-ended inputs can provide adequate performance. In this configuration, SFDR and distortion performance degrade due to excessive input common-mode oscillation. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched for optimum performance. When terminating the VIN-x pin, the full-scale input of 2 V pp can still be applied to the ADC's VIN+x pin. Figure 38 details a typical single-ended input configuration.

Clock Input Considerations

For best performance, the AD9252 sample clock inputs (CLK+ and CLK-) should be clocked with differential signals. This signal is usually AC coupled to the CLK+ and CLK- pins through a transformer or capacitor. These pins are internally biased and do not require additional biasing.

Figure 40 shows the preferred method of timing the AD9252. The low-jitter clock source is converted from single-ended to differential through an RF transformer. Back-to-back Schottky diodes across the secondary transformer limit the clock skew to the AD9252 to about 0.8 V pp differential. This helps prevent large voltage fluctuations of the clock through the rest of the AD9252 and maintains the fast rise and fall times of the signal, which are critical for low jitter performance.

Another option is to AC-couple the differential PECL signal to the sample clock input pin, as shown in Figure 41. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers have excellent jitter performance.

In some applications, a single-ended CMOS signal can be used to drive the sample clock input. In this application, CLK+ should be driven directly from the CMOS gate and the CLK pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 43). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the choice of drive logic voltage very flexible.

Clock Duty Cycle Considerations

A typical high-speed ADC uses two clock edges to generate various internal timing signals. Therefore, these ADCs may be sensitive to the clock duty cycle. Typically, a 5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics. The AD9252 includes a duty cycle stabilizer (DCS) that retimes non-sampling edges to provide an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9252. When the DCS is on, the noise and distortion performance is nearly flat over a wide range of duty cycles. However, some applications may need to turn off the DCS function. If so, keep in mind that dynamic range performance may suffer when operating in this mode. See the memory mapping section for details on using this feature.

The duty cycle stabilizer uses a delay locked loop (DLL) to create non-sampling edges. Therefore, any change to the sampling frequency requires about eight clock cycles to allow the DLL to acquire and lock to the new rate.

Clock Jitter Considerations

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. The signal-to-noise attenuation (fA) at a given input frequency due only to aperture jitter (tJ) can be obtained by:

In this equation, rms aperture jitter represents the rms of all jitter sources, including clock input, analog input signal, and ADC aperture jitter specifications. If the undersampling application is particularly sensitive to jitter (see Figure 45). a J

In situations where aperture jitter may affect the dynamic range of the AD9252, the clock input should be treated as an analog signal. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. A low jitter crystal controlled oscillator is the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

See the AN-501 application note and AN-756 application note for more in-depth information on the jitter performance of the ADC.

Power consumption and power-down modes

As shown in Figure 46, the power consumed by the AD9252 is proportional to its sampling rate. The digital power consumption does not vary much as it is mainly determined by the DRVDD supply and the bias current of the LVDS output driver.

By asserting the PDWN pin high, the AD9252 is placed into power-down mode. In this state, the ADC typically dissipates 11mW. During power down, the LVDS output drivers are put into a high impedance state. When the PDWN pin is pulled low, the AD9252 returns to normal operating mode. The voltage tolerance of this pin is 1.8V and 3.3V.

In power-down mode, low power consumption is achieved by turning off the reference, reference buffer, phase-locked loop, and bias network. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when normal operation resumes. Therefore, the wake-up time is related to the time spent in power-down mode: a shorter period reduces the wake-up time proportionally. The recommended 0.1µF and 4.7µF decoupling capacitors are on RFT and ReFB, it takes about 1 second to fully discharge the reference buffer decoupling capacitors and about 375µs to restore full operation.

When using SPI, there are several other options for power down. The user can turn off each channel individually or put the entire device in standby mode. The latter option allows the user to keep the internal PLL powered up when a fast wake-up time (~600 ns) is required. See the memory mapping section for details on using these functions.

Digital output and timing

By default, the AD9252 differential outputs are ANSI-644 LVDS compliant at power-up. This can be changed to a low power, low signal option (similar to the IEEE 1596.3 standard) via SDIO/ODM pins or SPI. The LVDS standard can further reduce the overall power consumption of the device.

36 MW. For more information, see Table 16 in the SDIO/ODM Pins section or the Memory Map section. The LVDS drive current is derived on-chip, and the output current of each output is set to a nominal 3.5ma. A 100Ω differential termination resistor placed at the input of the LVDS receiver results in a nominal 350 mV swing at the receiver.

The AD9252 LVDS output facilitates interfacing with LVDS receivers in custom ASICs and FPGAs for excellent switching performance in noisy environments. A single point-to-point network topology is recommended, with 100Ω termination resistors placed as close as possible to the receiver. Without far-end receiver termination or poor differential traceroute,

May cause timing errors. To avoid this timing error, it is recommended that the track lengths do not exceed 24 inches, and that the differential output tracks should be kept together and of equal length. An example of the FCO and data flow is shown in Figure 47 when the AD9252 is used with a track of appropriate length and position.

Figure 48 shows an example LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram for trace lengths less than 24 inches on standard FR-4 material. Figure 49 shows an example of trace lengths over 24 inches on standard FR-4 material. Note that the tie jitter histogram reflects the reduction in data eye opening as the edge deviates from the ideal position. When the trace length exceeds 24 inches, it is the user's responsibility to determine whether the waveform meets the design time budget. Additional SPI options allow the user to further increase the internal termination (increased current) of all eight outputs to drive longer trace lengths (see Figure 50). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power consumption of the DRVDD supply increases when this option is used. Also, note that the histogram in Figure 50 has been improved.

Register 0x15 allows the user to increase the driver strength by 2× if the driver strength for the DCO± and FCO± outputs needs to be increased due to load mismatch. To do this, first set the appropriate bits in Register 0x05. Note that this function cannot be used with Bits 4 and 5 in Register 0x15. Bits 4 and 5 take precedence over this function. See the memory mapping section for more details.

Figure 50. Data eye for LVDS output in ANSI-644 mode, on standard FR-4, with 100Ω termination open, and trace lengths greater than 24 inches By default, the output data format is offset binary. See Table 8 for examples of output encoding formats. To change the output data format to two's complement, see the memory mapping section.

Data from each ADC is serialized and provided on a separate channel. The data rate of each serial stream is equal to 14 bits of the sampling clock rate, with a maximum of 700 Mbps (14 bits × 50 MSPs = 700 Mbps). The lowest typical conversion rate is 10 ms/sec. However, if a lower sampling rate is required for a particular application, the PLL can be set up via the SPI to allow encoding rates as low as 5 MSPS. See the memory mapping section for information on enabling this feature.

Two output clocks are provided to assist in capturing data from the AD9252. The DCO is used to clock the output data equal to seven times the sampling clock (CLK) rate. Data is clocked out of the AD9252 and must be on the rising and falling edges of the DCO that supports double data rate (DDR) capture. The FCO is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information.

When using SPI, the DCO phase can be adjusted in 60° increments relative to the data edge. This allows the user to optimize the system timing margins if needed. As shown in Figure 2, the default DCO+ and DCO- timing is 90° relative to the output data edge.

8-bit, 10-bit and 12-bit serial streams can also be initiated from SPI. This allows users to implement different serial streams to test device compatibility with low- and high-resolution systems. When changing the resolution to 8-bit, 10-bit or 12-bit serial stream, the data stream is shortened. A 12-bit example is shown in Figure 3.

When using SPI, the data output can be inverted from its nominal state. This should not be confused with reversing the serial stream to LSB first mode. In default mode, as shown in Figure 2, the MSB is the first in the serial stream of data output. However, this can be reversed so that the LSB is first in the data output serial stream (see Figure 4).

There are 12 digital output test mode options that can be initiated via SPI. This feature is useful when validating receiver capture and timing. See Table 9 for available output bit ordering options. Some test patterns have two consecutive ordinal words that alternate in different ways depending on the test pattern selected. Note that some schemas are not eligible for the "Data Format Selection" option. Additionally, customer user-defined test patterns can be assigned in register addresses 0x19, 0x1A, 0x1B, and 0x1C. With the exception of PN Sequence Short and PN Sequence Long, all test mode options can support word lengths from 8 to 14 bits to verify data capture to the receiver.

The PN sequence short pattern produces a pseudorandom bit sequence that repeats every 2-1 or 511 bits. See Section 5.1 of the ITU-T 0.150 (05/96) standard for a description of the PN sequence and how it is generated. The only difference is that the starting value must be a specific value, not all 1s (see Table 10 for initial values).

The PN sequence long mode produces a pseudorandom bit sequence that repeats every 2-1 or 8388607 bits. For a description of PN sequences and how they are generated, see section 5.6 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value must be a specific value instead of all 1s (see Table 10 for initial values), and the AD9252 inverts the bitstream according to the ITU standard.

SDIO/ODM pin

SDIO/ODM pins are used for applications that do not require SPI mode operation. If this pin and the CSB pin are tied to AVDD during device power-up, this pin enables a low power, reduced signal option (similar to the IEEE1596.3 reduced range link output standard). This option should only be used when the digital output trace length is less than 2 inches from the LVDS receiver. With this option, the FCO, DCO, and outputs function normally, but the LVDS signal swing is reduced from 350 mV pp to 200 mV pp for all channels, allowing the user to further power down the DRVDD supply.

For applications that do not use this pin, it should be tied tightly. In this case, the device pin can be left open and the 30 kΩ internal pull-down resistor pulls this pin low. This pin only allows 1.8V. If the application requires this pin to be driven from a 3.3 V logic level, place a 1 kΩ resistor in series with this pin to limit current.

SCLK/DTP pin

The SCLK/DTP pin is used for applications that do not require SPI mode operation. If this pin and the CSB pin are held high during device power-up, a single digital test mode can be enabled. When SCLK/DTP is connected to AVDD, the ADC channel output offset is as follows: 10 0000 0000 0000. The FCO and DCO are functional and all channels are switched out of repeatable test mode. This mode allows the user to perform timing alignment adjustments between the FCO, DCO and output data. For normal operation, this pin should be connected to AGND through a 10 kΩ resistor. The voltage tolerance of this pin is 1.8V and 3.3V.

Other and custom test patterns can also be observed when commands are issued from the SPI port. See the memory mapping section for available options.

CSB pin

For applications that do not require SPI mode operation, the CSB pin should be tied to AVDD. By setting CSB high, all SCLK and SDIO information will be ignored. This pin is 1.8 V and 3.3 tolerant.

RBIAS pin

To set the ADC's internal core bias current, place a nominally 10.0 kΩ resistor between the RBIAS pin and ground. The resistor current is derived on-chip and sets the ADC's AVDD current to a nominal 360 mA at 50 MSPS. Therefore, a tolerance of at least 1% must be used for this resistor to achieve consistent performance.

voltage reference

The AD9252 has a built-in stable and accurate 0.5V voltage reference. This is obtained internally by a factor of 2, setting VREF to 1.0V, which results in a full-scale differential input range of 2V pp. VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0V reference to improve accuracy.

When applying decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to the ADC pins and on the same PCB layer as the AD9252. Recommended capacitor values and configurations for the AD9252 reference pins are shown in Figure 51.

Internal reference operation

A comparator within the AD9252 senses the potential at the sense pin and configures the reference. If the sensor is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 51), setting VREF to 1V.

The REFT and REFB pins determine the input range of their ADC core based on the reference configuration. For an internal or external reference configuration, the ADC's analog input full-scale range is equal to twice the reference pin voltage.

If the AD9252 reference is used to drive multiple reference loads from other converters in order to improve gain matching. Figure 53 depicts the effect of the load on the internal reference voltage.

Xref Operations

An external reference may be required to improve the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 54 shows the typical drift characteristics of the internal reference in 1V mode.

When the sense pin is tied to AVDD, internal references are disabled, allowing external references to be used. The external reference load is equivalent to a 6 kΩ load. Internal reference buffers generate positive and negative full-scale references (REFT and REFB) for the ADC core. Therefore, the external reference voltage must be limited to the nominal voltage range of 1.0V.

Serial Port Interface (SPI)

The AD9252 serial port interface allows the user to configure the converter for a specific function or operation through the structured register space provided within the ADC. This can provide users with additional flexibility and customization, depending on the application. The address is accessed through the serial port and can be written or read through the port. Memory is organized into bytes, which can be further divided into fields, as described in the memory mapping section. Detailed operating information can be found in the AN-877 application note, Connecting to a High Speed ADC via SPI.

Three pins define the SPI: SCLK, SDIO, and CSB pins (see Table 14). The SCLK pin is used to synchronize read and write data displayed to the ADC. The SDIO pin is a dual purpose pin that allows data to be sent to and read from the internal ADC memory mapped registers. The CSB pin is an active low control that enables or disables read and write cycles.

The falling edge of CSB, together with the rising edge of SCLK, determines the start of the frame sequence. In the command phase, a 16-bit command is sent, followed by one or more data bytes, as determined by bit field W0 and bit field W1. Examples of sequence timing and its definitions can be found in Figure 56 and Table 15.

During normal operation, the CSB is used to signal the device that SPI commands are to be received and processed. When CSB is low, the device processes SCLK and SDIO to execute instructions. Normally, CSB is held low until the communication cycle is complete. However, if connected to a slow device, CSB can be adjusted high between bytes, allowing older microcontrollers enough time to transfer data into the shift register. The CSB can be suspended when one, two or three bytes of data are being transferred.

When W0 and W1 are set to 11, the device enters streaming mode and continues to process data (read or write) until CSB is set high to end the communication cycle. This allows memory transfers to be done without the need for additional instructions.

Regardless of the mode used, if the CSB is high during a byte transfer, the SPI state machine will reset and the device will wait for a new instruction.

In addition to the mode of operation, the SPI port configuration affects how the AD9252 operates. For applications that do not require a control port, the CSB wire can be tied and held high. This puts the remaining SPI pins into their secondary mode as defined in the SDIO/ODM pins and SCLK/DTP pins sections. CSB can also be tied low to enable 2-wire mode. SCLK and SDIO are the only pins required for communication when CSB is connected too low. Although the devices are synchronous during power-up, the user should ensure that the serial port is in sync with the CSB line when using this mode. When operating in 2-wire mode, it is recommended to use only 1, 2 or 3 byte transfers. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction stage determines whether the serial frame is a read or write operation, allowing the serial port to be used to program the chip and read the contents of on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pins to change from input to output at the appropriate point in the serial frame. Data can be sent in MSB or LSB first mode. MSB first mode is the default mode at power up and can be changed by adjusting the configuration registers. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

hardware interface

The pins described in Table 14 form the physical interface between the user programming device and the AD9252 serial port. When using SPI, the SCLK and CSB pins are used as inputs. The SDIO pins are bidirectional and act as inputs during the write phase and as outputs during readback.

If multiple SDIO pins share a connection, care should be taken to ensure proper V levels are met. Assuming the same load on each AD9252, Figure 55 shows the number of SDIO pins that can be connected together and the resulting VOH level.

The interface is flexible enough to be controlled by a serial PROM or PIC microcontroller, offering the user an alternative to a full SPI controller to program the ADC (see AN-812 application note).

If the user chooses not to use SPI, these dual function pins provide their auxiliary functions during device power-up when CSB is tied to AVDD. Please refer to the "Theory of Operation" section for details on the pinned pin functionality supported on SPI pins.

memory map

read memory map

Each row in the memory-mapped register table (Table 16) has eight address locations. The memory map is divided into three parts: the chip configuration register map (address 0x00 to address 0x02), the device index and transfer register map (address 0x04, address 0x05 and address 0xFF) and the ADC function register map (address 0x08 to address 0x22).

The leftmost column of the memory map represents the register address number; the default value is shown in the second rightmost column. The 7th bit column is the start of the given default hex value. For example, the default value of address 0x09 (clock register) is 0x01, which means bit 7=0, bit 6=0, bit 5=0, bit 4=0, bit 3=0, bit 2=0, bit 1= 0 and bit 0 = 1 or 0000 0001. This setting is the default setting for the duty cycle stabilizer when it is switched on. The duty cycle stabilizer is turned off by writing 0 to Bit 0 of this address, followed by 0x01 to Register 0xFF (the transfer bit). It is important to follow each write sequence with a transfer bit to update the SPI registers. With the exception of Register 0x00, Register 0x04, Register 0x05, and Register 0xFF, all registers are buffered with master-slave latches and require write transfer bits. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

reserved location

Undefined memory locations should not be written to unless the default values suggested in this datasheet are written. Addresses marked with a value of 0 should be considered reserved and have 0s written to their registers during power-up.

Defaults

When the AD9252 comes out of reset, the critical registers are preloaded with default values. These values are shown in Table 16, where X represents an undefined feature.

logic level

The various registers are explained as follows: "bit is set" is synonymous with "bit is set to logic 1" or "bit is written to logic 1". "Clear bit" is synonymous with "bit is set to", "logic 0" or "write logic 0 for bit".

application information

Design Guidelines

Before beginning the design and layout of the AD9252 as a system, designers are advised to familiarize themselves with these guidelines, which discuss the special circuit connections and layout requirements required for specific pins.

Power and Grounding Recommendations

When connecting power supplies to the AD9252, it is recommended to use two separate 1.8V supplies: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be connected to AVDD first, then tapped and isolated with a ferrite bead or filter choke, and then DRVDD's decoupling capacitor. Users can use several different decoupling capacitors to cover high and low frequencies. These capacitors should be close to the entry point at the PC board level and close to the part with the smallest trace length.

When using the AD9252, a single PC board ground plane should be sufficient. Optimum performance is easily achieved with proper decoupling and intelligent partitioning of the analog, digital, and clock sections of the PC board.

Exposed Blade Hot Slug Recommendations

The exposed switch board on the bottom of the ADC is required to be connected to analog ground (AGND) for optimum electrical and thermal performance of the AD9252. The exposed continuous copper plane on the PCB should match pin 0 of the AD9252 exposed paddle. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation through the bottom of the PCB. These vias should be filled or plugged with solder. To maximize the coverage and adhesion between the ADC and the PCB, the continuous copper plane is divided by covering the silkscreen on the PCB into several uniform sections. This provides multiple connection points between the ADC and the PCB during reflow, whereas using a continuous plane with no partitions guarantees only one connection point. See Figure 57 for an example of a PCB layout. For more information on packaging and PCB layout for chip scale packages, see AN-772 Application Note, Design and Manufacturing Guidelines for Lead Frame Chip Scale Packages (LFCSP).

Evaluation Committee

The AD9252 evaluation board provides all the support circuitry required to operate the ADC in various modes and configurations. The converter can be driven differentially using a transformer (default) or an AD8334 driver. ADCs can also be driven single-ended. A separate power supply pin is provided to isolate the DUT from the AD8334's drive circuitry. Each input configuration can be selected by changing the connection of the different jumpers (see Figure 62 to Figure 66). Figure 58 shows a typical bench characterization setup used to evaluate the ac performance of the AD9252. Signal sources for analog inputs and clocks with very low phase noise (<1ps rms jitter) are key to achieving optimum converter performance. To achieve the specified noise performance, the analog input signal also needs to be properly filtered to remove harmonics and reduce integrated or broadband noise at the input.

See Figure 62 through Figure 72 for complete schematics and layouts that demonstrate routing and grounding techniques that should be applied at the system level.

power supply

This evaluation board has a wall mounted switching power supply that provides 6 V, 2 maximum outputs. Connect the power source to a wall outlet rated for 100 VAC to 240 VAC at a frequency of 47 Hz to 63 Hz. The other end of the power supply is a 2.1mm inner diameter jack that connects to the P701's PCB. Once on the PC board, the 6V power supply is fused and regulated before being connected to three low-dropout linear regulators that provide the proper bias for various parts of the board.

L701 to L704 can be removed to disconnect the switching power supply when operating the evaluation board under non-fault conditions. This allows the user to bias each section of the board individually. Use the P702 to connect a different power source for each section. AVDD U DUT and DRVDD U DUT require at least a 1.8V power supply; however, it is recommended to use separate power supplies for analog and digital signals with a current capacity of 1A each. To operate the evaluation board with the VGA option, a separate 5.0V analog supply (AVDD U 5V) is required. To operate the evaluation board with the SPI and alternate clock options, a separate 3.3 V analog power supply (AVDD U 3.3 V) is required in addition to other power supplies.

input signal

When connecting the clock and analog sources to the evaluation board, use a clean signal generator with low phase noise, such as a Rohde & Schwarz SMA or HP864 4-signal generator or equivalent, and a 1-meter, shielded, RG- 58, 50Ω coaxial cable. Enter the desired frequency and amplitude from the ADC spec sheet. Typically, most analog equipment companies, the evaluation board can accept a sine wave input clock of about 2.8 volts PP or 13 DBM. When connecting an analog input source, a multipole narrowband bandpass filter with 50Ω termination is recommended. TTE, Allen Avonics, and K&L Microwave offer good choices of such bandpass filters. If possible, the filter should be connected directly to the evaluation board.

output signal

The default setup uses the analog device HSC-ADC-FIFO5INTZ to interface with the analog device standard dual channel FIFO data acquisition board (HCS-ADC-EVALCZ). Two of the eight channels can be evaluated simultaneously. For more information on channel settings and optional settings for these boards, visit /FIFO.

Default Action and Jumper Selection Settings

Below is a list of default and optional settings or modes allowed on the AD9252 version. Evaluation Committee.

(1) Power supply: Connect the switching power supply provided with the evaluation kit between a 47 Hz to 63 Hz rated 100 V ac to 240 V ac wall socket and the P701.

(2), AIN: The evaluation board is set up for transformer-coupled analog input with the best 50Ω impedance matching with 150 MHz bandwidth (see Figure 59). For more bandwidth response, the differential capacitors on the analog inputs can be changed or removed. The common mode of the analog input is developed from the center tap of the transformer or AVDD-DUT/2.

(3), VREF: VREF is set to 1.0V by grounding the sensing pin R317. This results in the ADC operating at 2.0 V pp full scale. A separate external reference option using the ADR510 is also included on the evaluation board. Fill in R312 and R313, then remove C307. Correct use of the VREF option is explained in the Voltage Reference section.

(4) RBIA: The default setting of RBIA is 10 kΩ (R301) to ground, which is used to set the ADC core bias current.

Clock: The default clock input circuit comes from a simple transformer coupled circuit that uses a high bandwidth 1:1 impedance ratio transformer (T401) to add very low jitter to the clock path. The clock input is 50Ω and is AC coupled to handle single-ended sine wave type inputs. The transformer converts the single-ended input to a differential signal, which is truncated before entering the ADC clock input.

Differential LVPECL clocks are also available for ADC inputs using the AD9515 (U401). Fill R406 and R407 with 0Ω resistors, then remove R215 and R216 to disconnect the default clock path input. Also, fill C205 and C206 with 0.1µF capacitors and remove C409 and C410 to disconnect the default clock path output. The AD9515 has a number of pin strapping options set as the default operating mode. See the AD9515 data sheet for details on these and other options.

In addition, an on-board oscillator is provided on the OSC401, which can be used as the main clock source. Setup is quick and involves installing R403 and a 0Ω resistor, and setting the enable jumper (J401) to the ON position. If the user wishes to use a different oscillator, two oscillator package options (OSC401) can be used to check the ADC performance.

(1) PDWN: To enable the power-down function, short J301 to the open position (AVDD) of the PDWN pin.

(2), SCLK/DTP: To enable digital test mode on the digital output of ADC, please use J304. Test mode 10 0000 0000 0000 is enabled if J304 is connected to AVDD during device power-up. See the SCLK/DTP Pins section for details.

(3), SDIO/ODM: To enable low power, reduced signal option (similar to IEEE1595.3 reduced range link LVDS output standard), use J303. If J303 is tied to AVDD during device power-up, it will enable the LVDS output in the low-power, reduced-signal option from the default ANSI-644 standard. This option reduces the power of the DRVDD supply by changing the signal swing from 350 mV pp to 200 mV pp. See the SDIO/ODM Pin section for more details.

(4), CSB: To enable SPI information processing on SDIO and SCLK pins, connect J302 to always-on mode. To ignore SDIO and SCLK information, connect J302 to AVDD.

(5) Non-SPI mode: For users who wish to operate the DUT without using SPI, just remove jumpers J302, J303 and J304. This will disconnect the CSB, SCLK/DTP and SDIO/ODM pins from the control bus, allowing the DUT to operate in the simplest mode. Each pin has internal termination and will float to their respective levels.

(6), D+x, Dx: Optional receiver terminals R318 and R320 to R328 can be installed next to the high-speed backplane connectors if the alternative data capture method of the setup shown in Figure 62 is used.

Alternative analog input driver configuration

The following is a brief description of an alternative analog input driver configuration using the AD8334 dual VGA. If this drive option is used, some components may need to be populated, in which case Table 17 lists all required components. For more details on the AD8334 dual VGA, including its operation and optional pin settings, see the AD8334 data sheet.

To configure the analog input to drive VGA instead of the default converter option, the following components need to be removed and/or changed.

(1), remove R102, R115, R128, R141, R161, R162, R163, R164, R202, R208, R218, R225, R234, R241, R252, R259, T101, T102, T103, T104, T201, T202, T203 and T204.

(2) Fill R101, R114, R127, R140, R201, R217, R233 and R251 with 0Ω resistors in the analog input path.

(3), fill R152, R153, R154, R155, R156, R157, R158, R159, R215, R216, R229, R230, R247, R248, R263, R264, C103, C105, C110, C112, C117, C119, C124 , C126, C203, C205, C210, C212, C217, C219, C224, and C226 with 10 kΩ resistors to provide input common-mode levels for the ADC analog inputs.

(4), fill R105, R113, R118, R124, R131, R137, R151, R160, R205, R213, R221, R222, R237, R238, R255 and R256, 0Ω resistors in the ADC analog input path for connection VGA output.

(5), remove R515, R520, R527, R532, R615, R620, R627 and R632 on the AD8334 analog output.

(6), remove R512, R524, R612 and R624, set AD8334 mode and AD8334 HILO pin to low. Some applications may require this to be different. For more information on these features, see the AD8334 data sheet.

In this configuration, L505 to L520 and L605 to L620 are fitted with 0Ω resistors to allow for signal connection and filter use if additional requirements are required.

In this example, a 16MHz two-pole low-pass filter is applied to the AD8334 output. The following parts will need to be removed and/or replaced:

(1), remove the L507, L508, L511, L515, L516, L519, L607, L608, L611, L612, L615, L616, L619 and L620 on the AD8334 analog output.

(2) Fill L507, L508, L511, L512, L515, L516, L519, L607, L608, L611, L612, L615, L616, L619 and L620 with a 680 nH sensor.

(3) Fill C543, C547, C551, C555, C643, C647, C651 and C655 with 68 pF capacitors.

Dimensions