The design difficulties of passive UHF RFID chips revolve around how to improve the read and write distance of the chip and reduce the manufacturing cost of tags. Therefore, improving the efficiency of the power recovery circuit, reducing the power consumption of the overall chip, and working reliably are still the main challenges in the design of RFID tag chips.

UHF Passive RFID Tag (UHF Passive RFID Tag) refers to an RFID tag with an operating frequency between 300M and 3GHz in the UHF frequency band without external power supply. This ultra-high frequency passive RFID tag has become one of the key directions of RFID research due to its high operating frequency, long readable and writable distance, no external power supply, and low manufacturing cost. mainstream product.

For the research on RFID tags in the UHF band, many international research institutes have achieved some excellent results. For example, Atmel Corporation published a UHF passive RFID tag with a minimum RF input power as low as 16.7μW at JSSC. This article has become a classic article in RFID tag design due to its ultra-low input power and has been cited many times. In 2005 , JSSC published a 2.45G RFID tag chip designed by the Swiss Federal Institute of Technology with a minimum input power of only 2.7μW and a read and write distance of up to 12m. In the design of ultra-small and ultra-thin RFID tags, Hitachi Corporation of Japan proposed an RFID tag chip with an area of only 0.15mm×0.15mm and a chip thickness of only .5μm at the 2006 ISSCC conference. Domestic research in the field of RFID tags is still far from the top foreign scientific research achievements, and domestic scientific researchers need to redouble their efforts.

As shown in Figure 1, a complete UHF passive RFID tag consists of an antenna and a tag chip. The tag chip generally includes the following circuits: power recovery circuit, power voltage regulator circuit, backscatter modulation circuit, Demodulation circuit, clock extraction/generating circuit, start signal generating circuit, reference source generating circuit, control unit, memory.

The energy required for the passive RFID tag chip to work completely comes from the energy of the electromagnetic wave generated by the card reader. Therefore, the power recovery circuit needs to convert the ultra-high frequency signal induced by the tag antenna into the DC voltage required for the chip to work. provide energy.

Part 2 of this article will introduce the design of the power recovery circuit. Because the electromagnetic environment in which the RFID tag is located is very complex, the power of the input signal can change hundreds or even thousands of times. Therefore, in order for the chip to work normally in different field strengths, a reliable power supply voltage regulator circuit must be designed. . Part 3 of this article will describe the design of the power supply voltage regulator circuit. The modulation and demodulation circuit is the key circuit for the communication between the tag and the card reader. At present, most of the UHF RFID tags use ASK modulation. This article introduces modulation and demodulation in the fourth part. The control unit of an RFID tag is a digital circuit that processes the instructions. In order to make the digital circuit reset correctly after the tag enters the card reader field to respond to the card reader's command, a reliable start-up signal generating circuit must be designed to provide the reset signal of the digital unit. In Part 5 of this article, the design of the start-up signal generation circuit will be discussed.

Power recovery circuit

The power recovery circuit converts the ultra-high frequency signal received by the RFID tag antenna into a DC voltage through rectification, boosting, etc., to provide energy for the chip to work. The power recovery circuit has various possible circuit structures. As shown in Figure 2, there are several power recovery circuits commonly used at present.

Among these power recovery circuits, there is no ideal circuit structure, and each circuit has its own advantages and disadvantages. Under different load conditions, different input voltage conditions, different output voltage requirements, and available process conditions, different circuits need to be selected for optimum performance. The multi-stage diode voltage doubler circuit shown in Figure 2(a) generally uses Schottky barrier diodes. It has the advantages of high voltage doubling efficiency and small input signal amplitude, and is widely used. However, the common CMOS process of the general foundry does not provide Schottky barrier diodes, which will bring trouble to the designer in the selection of the process. Fig. 2(b) replaces the Schottky diode with a PMOS tube connected in the form of a diode, which avoids the special requirements in the process. The voltage doubling circuit of this structure needs to have a higher input signal amplitude, and has better voltage doubling efficiency when the output voltage is higher. Figure 2(c) is a conventional diode full-wave rectifier circuit. Compared with the Dickson voltage doubler circuit, the voltage doubler effect is better, but more diode elements are introduced, and the power conversion efficiency is generally slightly lower than that of the Dickson voltage doubler circuit. In addition, since its antenna input end is separated from the chip ground, when viewed from the antenna input end to the chip, it is a fully symmetric structure with capacitor blocking, which avoids the interaction between the chip ground and the antenna, and is suitable for use with symmetric antennas (such as even pole antenna) connected. Figure 2(d) is a CMOS tube solution for a full-wave rectifier circuit proposed by many literatures. In the case of limited process, better power conversion efficiency can be obtained, and the requirement on the amplitude of the input signal is relatively low.

In the application of general passive UHF RFID tags, it is hoped that the chip circuit is suitable for the manufacture of ordinary CMOS process due to cost considerations. The requirement of long-distance reading and writing puts forward higher requirements on the power conversion efficiency of the power recovery circuit. To this end, many designers use standard CMOS technology to implement Schottky barrier diodes, which can easily use a multi-stage Dickson voltage doubler circuit structure to improve the performance of power conversion. Figure 3 shows a schematic diagram of the structure of a Schottky diode fabricated in a common CMOS process. In the design, there is no need to change the process steps and mask generation rules, just make some changes in the layout, you can make a Schottky diode.

Figure 4 shows the layout of several Schottky diodes designed in the UMC 0.18um CMOS process. Their DC characteristic test curves are shown in Figure 5. From the test results of DC characteristics, it can be seen that the Schottky diode manufactured by standard CMOS process has typical diode characteristics, and the turn-on voltage is only about 0.2V, which is very suitable for RFID tags.

When the input signal amplitude is high, the power supply voltage regulator circuit must be able to ensure that the output DC power supply voltage does not exceed the highest voltage that the chip can withstand; at the same time, when the input signal is small, the power consumed by the voltage regulator circuit must be As small as possible to reduce the total power consumption of the chip.

From the principle of voltage stabilization, the structure of voltage stabilization circuit can be divided into two types: parallel voltage stabilization circuit and series voltage stabilization circuit. The basic principle of the parallel regulator circuit is shown in Figure 6.

In the RFID tag chip, an energy storage capacitor with a large capacitance value is required to store enough charge for the tag to receive the modulated signal, but still at the moment when the input energy is small (such as the moment when there is no carrier wave in OOK modulation) , to maintain the power supply voltage of the chip. If the input energy is too high and the power supply voltage rises to a certain level, the voltage sensor in the voltage regulator circuit will control the leakage source to release the excess charge on the energy storage capacitor, so as to achieve the purpose of voltage regulation. Figure 7 is one of the parallel regulator circuits. Three series-connected diodes D1, D2, D3 and resistor R1 form a voltage sensor to control the gate voltage of the bleeder tube M1. When the power supply voltage exceeds the sum of the turn-on voltages of the three diodes, the gate voltage of M1 increases, M1 turns on, and begins to discharge the energy storage capacitor C1.

The principle of another type of voltage regulator circuit is to use a series voltage regulator scheme. Its schematic diagram is shown in Figure 8. The reference voltage source is designed to be a reference source independent of the supply voltage. The output power supply voltage is divided by the resistor and compared with the reference voltage, and the difference value is amplified by the operational amplifier to control the gate potential of the M1 tube, so that the output voltage and the reference source basically maintain the same stable state.

This series voltage regulator circuit can output a relatively accurate power supply voltage, but since the M1 tube is connected in series between the unregulated power supply and the regulated power supply, when the load current is large, the voltage drop on the M1 tube will cause a higher voltage drop. power loss. Therefore, this circuit structure is generally used in tag circuits with less power consumption.

Modulation and demodulation circuit
a. Demodulation circuit

In order to reduce the chip area and power consumption, most of the passive RFID tags currently use ASK modulation. For the ASK demodulation circuit of the tag chip, the commonly used demodulation method is the method of envelope detection, as shown in Figure 9.

The envelope detection part is basically the same as the voltage doubler circuit of the power recovery part, but it is not necessary to provide a large load current. A leakage current source is connected in parallel at the final stage of the envelope detection circuit. When the input signal is modulated, the input energy is reduced, and the leakage source reduces the envelope output voltage, so that the following comparator circuit can determine the modulation signal. Due to the large energy variation range of the input RF signal, the current of the leakage source must be dynamically adjusted to adapt to the changes of different field strengths in the near field and far field. For example, if the current of the bleeder power supply is small, it can meet the needs of the comparator when the field strength is weak, but when the tag is in the near field with a strong field strength, the bleeder current will not be enough to make the detected signal A large amplitude change occurs, and the post-stage comparator cannot work normally. To solve this problem, the leakage source structure as shown in Figure 10 can be used.

When the input carrier is not modulated, the gate potential of the bleeder tube M1 is the same as the drain potential, forming a diode-connected NMOS tube to clamp the envelope output near the threshold voltage of M1. The power consumed on M1 is balanced; when the input carrier is modulated, the input energy of the chip decreases. At this time, due to the action of the delay circuits R1 and C1, the gate potential of M1 remains at the original level, and M1 leaks The current of the amplifier remains unchanged, which makes the amplitude of the envelope output signal decrease rapidly; also, after the carrier is recovered, the delay of R1 and C1 makes the envelope output quickly return to the original high level. By adopting this circuit structure and selecting the size of R1, C1 and M1 reasonably, the need for demodulation under different field strengths can be satisfied. The comparator circuit connected behind the envelope output also has a variety of options to choose from, commonly used are hysteresis comparators, operational amplifiers, etc. It can also be simplified to be implemented with inverters.

b. Modulation circuit

Passive UHF RFID tags generally use the modulation method of backscattering, that is, by changing the input impedance of the chip to change the reflection coefficient between the chip and the antenna, so as to achieve the purpose of modulation. Generally, the antenna impedance and the chip input impedance are designed to be close to power matching when not modulated, and to increase the reflection coefficient when modulated. The commonly used backscattering method is to connect a capacitor with a switch in parallel between the two input terminals of the antenna. As shown in Figure 11, the modulation signal determines whether the capacitor is connected to the input terminal of the chip by controlling the opening of the switch. The input impedance of the chip.

Start-up signal generation circuit The function of the power-start reset signal generation circuit in the RFID tag is to provide a reset signal for the start-up of the digital circuit after the power supply is restored. Its design must consider the following issues: if the rise time of the power supply voltage is too long, the high level amplitude of the reset signal will be low, which cannot meet the needs of the digital circuit reset; the start signal generation circuit is more sensitive to the fluctuation of the power supply , it may cause malfunction; static power consumption must be as low as possible.

Usually, after the passive RFID tag enters the field, the time for the power supply voltage to rise is not certain and may be very long. This requires the design of the start-up signal generating circuit to generate the start-up signal when the timing is related to the power supply voltage. Figure 12 shows a common start-up signal generation circuit.

Its basic principle is to use the branch composed of resistor R0 and NMOS tube M1 to generate a relatively fixed voltage Va. When the power supply voltage vdd exceeds the threshold voltage of the NMOS tube, the Va voltage basically remains unchanged. As vdd continues to rise, when the power supply voltage reaches Va+|Vtp|, the PMOS transistor M0 is turned on to increase Vb, and previously, because M0 was turned off, Vb was always at a low level. The main problem with this circuit is the static power dissipation. In addition, because the threshold voltage of the MOS transistor varies greatly with the process under the CMOS process, it is easily affected by process deviation. Therefore, the use of pn junction diodes for start-up voltage generation will greatly reduce process uncertainty, as shown in Figure 13.

When VDD rises to the turn-on voltage of the two pn junction diodes, the gate of the PMOS transistor M0 is equal to the power supply voltage, the PMOS transistor is turned off, and the voltage on the capacitor C1 is at a low level at this time. When VDD rises above the two diode threshold voltages, M0 starts to conduct, while the gate voltage of M1 remains unchanged, the current flowing through M1 remains unchanged, the voltage on capacitor C1 gradually increases, and when it rises to the reverse phase After the device is turned over, a start signal is generated. Therefore, the time for this kind of circuit to generate the start-up signal depends on whether the power supply voltage reaches the threshold voltage of the two diodes. It has high stability and avoids the premature start-up signal when the power supply voltage rises too slowly in general start-up circuits. The problem.

If the rise time of the power supply voltage is too fast, the gate capacitance of the resistor R1 and M0 forms a low-pass delay circuit, which will make the gate voltage of M0 unable to quickly keep up with the change of the power supply voltage and remain at a low level. M0 will charge capacitor C1, causing the circuit to not work correctly. To solve this problem, a capacitor C5 is introduced. If the power supply voltage rises quickly, the coupling effect of the capacitor C5 can keep the gate potential of M0 consistent with the power supply voltage, avoiding the occurrence of the above problems.

The problem of static power consumption still exists in this circuit, the influence of static power consumption can be reduced by increasing the resistance value and selecting the size of the MOS transistor reasonably. To completely solve the problem of static power consumption, it is necessary to design an additional feedback control circuit to turn off this part of the circuit after the start-up signal is generated. However, special attention needs to be paid to the problem of instability caused by the introduction of feedback.

Conclusion Most of the main circuits of some RFID tags introduced in this paper have been verified by tape-out. Figure 14 is an RFID tag chip we designed. The chip area is 0.7mm×1.0mm, and the tag card number can be read out at 6 meters under 36dBm EIRP. Figure 15 is a 2.45GHz RFID tag with an on-chip antenna design. At 42dBm EIRP, the chip can respond at 40cm.

The design difficulties of passive UHF RFID chips revolve around how to improve the read and write distance of the chip and reduce the manufacturing cost of tags. Therefore, improving the efficiency of the power recovery circuit, reducing the power consumption of the overall chip, and working reliably are still the main challenges in the design of RFID tag chips.