feature

2 matched ADCs on microcontroller; 50 MSPS conversion speed; on-board voltage reference; low power (<1W); low input capacitance (10 pF); 65 V power supply; flexible input range.

application

Communication quadrature demodulation; digital oscilloscope; electronic warfare; radar.

General Instructions

The AD9058 combines two independent, high-performance, 8-bit analog-to-digital converters (ADCs) on a monolithic integrated circuit. Combined with an optional on-board voltage reference, the AD9058 provides a cost-effective alternative for systems requiring two or more ADCs.

Dynamic performance (SNR, ENOB) optimized to provide conversion rates up to 50 MSPS. Unique construction reduces input capacitance while maintaining high performance and low power consumption (<0.5w/channel). Digital inputs and outputs are TTL compatible.

Performance is optimized for an analog input of 2 V pp (±1 V; 0 V to 2 V). Using an on-board 2V voltage reference, the AD9058 can be set for unipolar positive operation (0 volts to 2 volts). This internal voltage reference can drive two ADCs.

Commercial (0°C to 70°C) and military (–55°C to + 125 °C) temperature range parts are available. Parts are supplied in sealed 48 lead dipped and 44 lead "J" lead packages.

theory of operation

The AD9058 contains two independent 8-bit analog-to-digital converters (ADCs) on a single silicon die. The two devices can operate independently, with independent analog inputs, voltage references, and clocks.

In conventional flash converters, 256 input comparators are required to achieve parallel conversion with 8-bit resolution. This is in stark contrast to the scheme used in the AD9058, shown in Figure 1.

Unlike traditional "flash" or parallel converters, each of the two ADCs in the AD9058 uses a patented interpolation structure to reduce circuit complexity, die size, and input capacitance. These advantages are cumulative because only half as many input comparator cells are required to complete the conversion compared to conventional flash designs.

In this unit, each of the two independent ADCs uses only 128 (27) comparators for conversion. The conversion of the seven most significant bits (msb) is performed by 128 comparators. The value of the least significant bit (LSB) is determined by interpolation between adjacent comparators in the decode register. A proprietary decoding scheme processes the comparator outputs and provides an 8-bit code to each ADC's output register; this scheme also minimizes error codes.

The analog input range is determined by the voltage applied at the voltage reference inputs (+VREF and –VREF). The AD9058 can operate from 0 V to 2 V using the internal voltage reference, or anywhere from -1 V to +2 V using an external reference. When using an external reference, the input range is limited to 2v p. An internal resistor ladder divides the applied voltage reference into 128 steps, each step representing two 8-bit quantization levels.

The on-board voltage reference +VINT is a bandgap reference with sufficient drive capability for both reference ladders. It provides a 2V reference that can drive the two ADCs in the AD9058 for unipolar positive operation (0V to 2V).

Using AD9058

See Figure 2. As shown, using an internal voltage reference connected to two ADCs reduces the number of external components required to create a complete data acquisition system. In this configuration, the input range of the ADC is positive unipolar, ranging from 0v to 2v. The bipolar input signal is buffered, amplified, and offset to the appropriate input range of the ADC by a good low distortion amplifier such as the AD9617 or AD9618.

The AD9058 offers considerable flexibility in choosing the analog input range of the ADC; the two independent ADCs can even have different input ranges if desired. In Figure 3, the AD9058 is configured for ±1V operation.

"Reference Ladder Offset" shown in the spec sheet is the error between the voltage applied to the reference ladder's +VREF (top) or –VREF (bottom) and the analog input voltage required to achieve a 1111111 or 0000 conversion . This represents the amount of adjustment range that must be designed into the AD9058 reference circuit.

The diode shown between ground and –VS is normally reversed to prevent latch-up. It is recommended for applications where the power supply sequence may allow +VS to be applied before –VS, or where the +VS supply is not current limited. If the negative supply is allowed to float (the +5 V supply is powered up before the -5 V supply), then a lot of the +5 V supply current will try to flow through the substrate (VS power contacts) to ground. If this current is not limited to less than 500 mA, the part may be damaged. Diodes prevent this potentially destructive situation from happening.

opportunity

See the AD9058 timing diagram, Figure 4. The AD9058 provides latched data output with no pipeline delay. To save power, the rise and fall times of the data output are relatively slow. When designing system timing, it is important to observe (1) setup and hold times; and (2) intervals when data changes.

Figure 3 shows the 2 kΩ pull-down resistors on each of the D0–D7 output data bits. At slew rates above 40 MSPS, these resistors help equalize rise and fall times and facilitate latching of output data into an external latch. 74ACT Logic Series devices have short setup and hold times and are the recommended choice for speeds of 40 MSPS or higher.

layout

To ensure optimum performance, a single low impedance ground plane is recommended. The analog and digital grounds should be connected together and to the ground plane of the AD9058 device. Analog and digital supplies should be bypassed to ground with 0.1µF ceramic capacitors as close as possible to the device.

For prototyping or evaluation, Methode Electronics, Inc. (part number 213-0320602) offers a surface mount socket for evaluating the AD9058 surface mount package. To evaluate the AD9058 in a through-hole PCB design, use the AD9058AJD/AKD and separate pin socket (AMP part number 6-330808-0). Alternatively, the surface mount AD9058 unit can be installed in a through-hole socket (Circuit Assembly, Irvine, CA, part number CA-44SPC-T).

AD9058 application

Combining two ADCs in one package is an attractive alternative in a variety of systems when cost, reliability and space are important considerations. Different systems emphasize specific specifications, depending on how the part is used.

In high-density digital radio communications, a pair of high-speed ADCs are used to digitize the in-phase (I) and quadrature (Q) components of a modulated signal. In this type of system, the signal presented to each ADC consists of a message-dependent amplitude that varies at the symbol rate, which is equal to the converter's sampling rate.

Figure 5 shows what the analog input to the AD9058 looks like when viewed relative to the sampling clock. Signal-to-noise ratio (SNR), transient response, and sample rate are all key metrics for a digitized "eye diagram."

Receive sensitivity is limited by the signal-to-noise ratio of the system. For ADCs, the signal-to-noise ratio is measured in the frequency domain and calculated with a Fast Fourier Transform (FFT). The signal-to-noise ratio is equal to the ratio of the fundamental component of the signal (rms amplitude) to the rms level of the noise. Noise is the sum of all other spectral components, including harmonic distortion, but excluding DC.

Although the sampled signal is encoded without a significant conversion rate, the dynamic performance of the ADC and system is still critical. The transient response is the time it takes for the AD9058 to reach full accuracy when a step function input is applied. The overvoltage recovery time is the time interval required for the AD9058 to recover to full accuracy after an overdriven analog input signal has been reduced to its input range.

In a digital oscilloscope, the time-domain performance of the ADC is also very important. When track-/sample and hold is used before the ADC, its operation becomes similar to that of the receiver described above.

The dynamic response of high frequency input can be described by the effective number of bits (ENOB). The effective number of digits is calculated by sine wave curve fitting and is expressed as:

where N is the resolution (number of bits), the measurement error is the actual rms error calculated from the output of the converter, and the input is a pure sine wave.

The maximum slew rate is defined as the code (sample) rate at which the SNR of the lowest frequency analog test signal falls below 3 dB below the guaranteed limit.

Dimensions