feature

Variable analog input bandwidth control; variable SOGIN bandwidth control; automatic clamping level adjustment; 140 MSPS maximum slew rate; 300 MHz analog bandwidth; 0.5 V to 1.0 V analog input range; 500 ps pp PLL clock jitter at 110 msps; 3.3 V Power supply; fully synchronous processing; selectable input filtering; hot-plug synchronization detection; mid-scale clamping;

application

RGB graphics processing; LCD monitors and projectors; plasma displays; scan converters; microdisplays; digital television.

General Instructions

The AD9985A is a complete 8-bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from PCs and workstations. 140 ms per second encoding rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280×1024 at 75 Hz). The AD9985A includes a 140 MHz internal triple ADC 1.25 volt reference, phase locked loop and programmable gain, offset and clamping controls. User only provides 3.3V power supply, analog input, horizontal sync (Hsync) and coast signal. The tri-state CMOS output can be powered from 2.5v to 3.3v.

The on-chip PLL of the AD9985A is input from Hsync. The pixel clock output frequency ranges from 12 MHz to 140 MHz. The PLL clock jitter is 500ps pp, and the typical value is 140msps.

When the glide signal is present, the phase locked loop maintains its output frequency without Hsync. The sampling phase provides adjustments. The data, sync, and clock output phases maintain a relationship. The AD9985A also provides full sync on composite sync and sync on green applications. The clamp signal is generated internally or by the user via the clamp input pin. This interface is fully programmable via a 2-wire serial interface.

The AD9985A is fabricated on an advanced CMOS process in a space-saving 80-lead LQFP surface mount lead-free plastic package and is specified over the -40°C to +85°C temperature range.

Design Guidelines

General Instructions

The AD9985A is a fully integrated solution for capturing and digitizing analog RGB signals for display on a flat panel display or projector. This circuit is ideal for providing a computer interface for high-definition television displays or high-performance video scan converters. Implemented in a high-performance CMOS process, the interface can capture signals at pixel rates up to 110mhz.

The AD9985A includes all necessary input buffering, signal DC recovery (clamping), offset and gain (brightness and contrast) adjustments, pixel clock generation, sampling phase control, and output data formatting. All controls are programmable via a 2-wire serial interface. The full integration of these sensitive analog functions enables straightforward system design with low sensitivity to physical and electrical environments.

The typical power consumption of the device is only 500 MW, and the operating temperature range is 0°C to 70°C (-40°C to +85°C for the AD9985ABST) without special environmental considerations.

digital input

All digital inputs on the AD9985A operate to 3.3V CMOS levels. However, all digital inputs are 5V. Applying 5 volts to them won't cause any damage.

input signal processing

The AD9985A has one high-impedance analog input pin for the red, green, and blue channels. They can accommodate signals from 0.5 V to 1.0 V pp.

The signal is usually brought to the interface board via a DVI-I connector, a 15-pin D connector, or a BNC connector. The AD9985A should be placed as close as possible to the input headers. Signals should be routed to the IC input pins through matched impedance traces (typically 75Ω). At this point, the signal should be resistor terminated (75Ω to the signal ground return) and capacitively coupled to the AD9985A input through a 47 nF capacitor. These capacitors form part of the DC recovery circuit.

When the impedances are perfectly matched, the best performance is obtained over the widest possible signal bandwidth. The ultra-wideband input of the AD9985A (300 MHz) continuously tracks the input signal as it moves from one pixel level to the next and digitizes the pixel over long flat pixel times. In many systems, however, there are mismatches, reflections, and noise, which can cause excessive ringing and distortion of the input waveform. This makes it more difficult to build a sampling stage that provides good image quality. The results show that a small inductor in series with the input can effectively reduce the input bandwidth slightly and provide a high-quality signal over a wide range of conditions. Using a Fair-Rite #2508051217Z0 high-speed signal chip magnetic bead inductor in the circuit of Figure 3 produces good results in most applications.

HSYNC, VSYNC input

The interface also uses a horizontal sync signal to generate the pixel clock and clamp timing. This can be a sync signal directly from the graphics source, or a preprocessed TTL or CMOS level signal.

The Hsync input includes a Schmitt trigger buffer for noise immunity and long rise time signals. In a typical PC-based graphics system, the sync signal is just a TTL-level driver, supplied with an unshielded wire in the monitor cable. Therefore, no termination is required.

Serial control port

The serial control port is designed for 3.3V logic. If there is a 5V driver on the bus, these pins should be protected with 150Ω series resistors placed between the pull-up resistors and the input pins.

output signal processing

The digital outputs are designed and specified to operate from a 3.3V supply (VDD). They also work with V as as low as 2.5v for compatibility with other 2.5v logic.

clamp

RGB clamping

To properly digitize the input signal, the DC offset of the input must be adjusted to fit the range of the onboard ADC. Most graphics systems produce an RGB signal with black at ground and white at about 0.75 V. However, if the sync signal is embedded in the graph, the sync cue is often at ground, black is at 300 mV, and white is about 1 V. Some common RGB line amplifier boxes use emitter follower buffers to separate the signal and increase drive capability. This introduces 700 mV of DC offset to the signal, which must be removed for the AD9985A to capture properly.

The key to clamping is to identify the part (time) of the signal when the graphics system is known to produce black. An offset is then introduced such that the adc produces a black output (code 0x00) when there is a known black input. Then, when other signal levels are processed, the offset remains in place and the entire signal is shifted to remove the offset error.

In most PC graphics systems, black is transmitted between the active video lines. With a CRT display, when the electron beam finishes writing the horizontal lines on the screen (on the right), the electron beam is deflected quickly to the left side of the screen (called the horizontal return), and a black signal is provided to prevent the electron beam from interfering with the image.

In systems with embedded sync, a signal darker than the black signal (Hsync) is briefly generated, signaling the CRT to start backtracking. For obvious reasons, it is important to avoid gripping the tip of the Hsync. Fortunately, after Hsync (called back-porch), there is actually always a time to provide a good black reference. Clamping should be performed at this time.

Simply use the clamp pin at the appropriate time (external clamp = 1) to determine clamping timing. The polarity of this signal is set by the clamp polarity.

A simpler method of clamping timing uses the AD9985A internal clamping timing generator. The clamp placement register is programmed with the number of pixels that should pass after the Hsync trailing edge before clamping begins. The second register (Clamp Duration) sets the duration of the clamp. These are 8-bit values, which provide considerable flexibility in clamp generation. The clamp timing is referenced to the trailing edge of the Hsync because the back porch (black reference) always follows the Hsync, although the Hsync duration varies widely. A good starting point for establishing the clamp is to set the clamp to 0x09 (gives 9 pixel periods for the graphics signal to settle after sync) and the clamp duration to 0x14 (gives 20 pixel periods to re-establish the black reference ).

Clamping is done by placing an appropriate charge on the external input coupling capacitor. The value of this capacitor affects the performance of the clamp. If it is too small, there will be significant amplitude changes within the horizon time (between clamping intervals). If the capacitor is too large, it will take too long for the clamp to recover from large changes in the input signal offset. The recommended value (47nf) results in recovery from a 100 mV step error to within 1/2 LSB of 10 lines on a 60Hz SXGA signal with a clamp duration of 20 pixel periods.

YUV clamping

YUV graphics signals are slightly different from RGB signals in that the dc reference level (the black level in an RGB signal) can be at the midpoint of the graphics signal, rather than at the bottom. For these signals, it may be necessary to clamp to the mid-scale range of the ADC range (0x80) rather than the bottom of the ADC converter range (0x00).

The clamp can be set to midscale instead of ground by setting the clamp select bits in the serial bus register. Each of the three converters has its own select bit so they can be clamped independently on mesoscale or ground. These bits are located in Register 0x10, Bits[2:0]. The midscale reference voltage to which each ADC is clamped is provided by the midscale voltage pin (pin 37). Even if midscale clamping is not required, this pin should be bypassed to ground with a 0.1µF capacitor.

Gain and offset controls

The AD9985A accommodates input signals with an input range of 0.5 V to 1.0 V full scale. The full-scale range is set in three 8-bit registers (red gain, green gain, and blue gain). Note that increasing the gain setting will result in a reduction in the contrast of the image.

The offset control shifts the entire input range, resulting in changes in image brightness. Three 7-bit registers (Red Offset, Green Offset, Blue Offset) provide independent settings for each channel. The offset control provides an adjustment range of ±63 LSB. This range is tied to the full-scale range, so if the input range is doubled (from 0.5 V to 1.0 V), the offset step is also doubled (from 2 mV/step to 4 mV/step).

Figure 4 shows the interaction of gain and offset control. The size of the LSB in the offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. If the offset setting is close to midscale, the change is minimal. When changing the offset, the full-scale range is not affected, but the offset for the full-scale level is the same as the offset for the zero-scale level.

Auto offset

In addition to manual offset adjustment mode (via Registers 0x0B to 0x0D), the AD9985A includes circuitry to automatically calibrate each channel's offset. By monitoring the output of each ADC during the back porch of the input signal, the AD9985A can adjust itself to remove any offset error in its own ADC channel, as well as any offset error present in the incoming graphics or video signal.

To activate auto-offset mode, set Register 0x1D, Bit 7 to 1. Next, the target code registers (0x19 to 0x1B) must be programmed. The value programmed into the target code register should be the output code required by the AD9985A during the back porch reference time. For example, for RGB signals, all three registers are usually programmed to code 1, while for Y Pb Pr signals, the green (Y) channel is usually programmed to code 1, and the blue and red channels (Pb and Pr) are usually set to 128. Any target code value between 1 and 254 can be set, although the offset range of the AD9985A may not reach every value. Expected target code values range from (but are not limited to) 1 to 40 when clamping on the ground and 90 to 170 when clamping at midscale.

The ability to program object code for each channel gives the user a great deal of freedom and flexibility. While in most cases all channels are set to 1 or 128, the flexibility to choose other values allows for intentional skew to be inserted between channels. It also allows the ADC range to be tilted so that voltages outside the normal range can be digitized. For example, setting the target code to 40 allows digitization and evaluation of sync cues that are typically below black levels.

Finally, in auto-offset mode, the manual offset registers (0x0B to 0x0D) have new functionality. The values in these registers are digitally added to the value output by the ADC. The purpose of this is to match the advantages of manual compensation adjustments. Adjusting these registers is an easy way to make brightness adjustments. While this method loses some signal range, it has proven to be a very popular function. To be able to increase and decrease brightness, the values in these registers are signed two's complement in this mode. The digital adder is only used in auto-offset mode. Although it cannot be disabled, setting the offset register to all 0s effectively disables it by always adding 0s.

Sync on Green

The sync on green input operates in two steps. First, it sets the baseline clamp level for a negative peak detector. Second, it sets the sync trigger level to a programmable level (typically 150mV) above the negative peak. The green sync input must be AC coupled to the green analog input through its own capacitor, as shown in Figure 5. The value of the capacitor must be 1 nF±20%. This connection is not required if sync on green is not used. The sync on green signal is always negative.

clock generation

A Phase Locked Loop (PLL) is used to generate the pixel clock. In this phase locked loop, the Hsync input provides the reference frequency. A voltage controlled oscillator (VCO) produces a higher pixel clock frequency. This pixel clock is divided by the PLL divide value (Register 0x01 and Register 0x02) and compared to the Hsync input. Any errors are used to shift the VCO frequency and maintain lock between the two signals.

The stability of this clock is a very important factor in providing the sharpest and most stable images. Within each pixel time, there is a period in which the signal rotates from the old pixel amplitude and settles at its new value. Then, when the input voltage stabilizes, the signal must be converted to a new value (Figure 6). The ratio of slew time to settling time is a function of graphics DAC bandwidth and transmission system bandwidth (cable and termination). It is also a function of the overall pixel rate. Obviously, if the dynamics of the system remain the same, the slew and settling times are also fixed. This time must be subtracted from the total pixel period to preserve stable periods. At higher pixel frequencies, the overall cycle time is shorter, as is the stable pixel time.

Any jitter in the clock reduces the accuracy of determining the sample time and must also be subtracted from the stable pixel time. In the design of the clock generation circuit of the AD9985A, considerable care has been taken to minimize jitter. As shown in Figure 7, the clock jitter of the AD9985A is less than 5% of the total pixel time in all modes of operation, resulting in a negligible reduction in effective sampling time.

PLL characteristics are determined by loop filter design, PLL charge pump current, and VCO range settings. The design of the loop filter is shown in Figure 8. Table 9 lists the recommended settings for the VCO range and charge pump current for VESA standard display modes.

Four programmable registers are provided to optimize the performance of the PLL.

12-bit divisor register

The input Hsync frequency ranges from 15khz to 110khz. The PLL multiplies the frequency of the Hsync signal to produce a pixel clock frequency in the range of 12mhz to 110mhz. The divisor register controls the exact multiplication factor. This register can be set to any value between 221 and 4095. (The actual division ratio used is the programmed division ratio plus 1.)

2-bit VCO Range Register

To improve the noise performance of the AD9985A, the operating frequency range of the VCO is divided into three overlapping regions. The VCO range register sets this operating range. Table 6 shows the frequency ranges for the lowest and highest regions.

3-bit charge pump current register

This register allows the current to drive the low-pass loop filter to vary. Table 7 lists possible current values.

5-bit phase adjustment register

The phase of the generated sampling clock can be shifted to locate the optimal sampling point within the clock cycle. The phase adjustment register provides 32 phase shift steps of 11.25° each. The Hsync signal with the same phase shift is available on the HSOUT pin.

The COAST pin is used to allow the PLL to continue to operate at the same frequency without an incoming Hsync signal or during disturbances in Hsync such as equalization pulses. This can be used during vertical sync or any other time when the Hsync signal is not available. The polarity of the coast signal is set by the coast polarity register. In addition, the polarity of the Hsync signal is set by the Hsync polarity register. If automatic polarity detection is not used, the Hsync and Coast polarity bits should be set to match the respective polarities of the input signal.

power management

The AD9985A uses activity detection circuitry, active interface bits in the serial bus, active interface override bits, and power down bits to determine the correct power state. The three power states are full power, seek mode, and power off. Table 8 summarizes how the AD9985A determines which power mode it should be in and which circuit powers up/down in each of these modes. Power-off commands take precedence over automatic circuits.

opportunity

The timing diagrams in this section show the operation of the AD9985A.

The output data clock signal is generated so that its rising edge always occurs between data transitions and can be used to externally latch the output data.

Before valid data is available, the pipeline in the AD9985A must be flushed. This means that four datasets are displayed before valid data is available.

Sync timing

Hsync is processed in the AD9985A to remove ambiguity in leading edge timing relative to phase delayed pixel clock and data.

The Hsync input is used as a reference to generate the pixel sampling clock. The sampling phase relative to Hsync can be adjusted through a full 360° in 32 steps via the phase adjustment register (to optimize pixel sampling time). Display systems use Hsync to align memory and display write cycles; therefore, it is important to maintain a stable timing relationship between the Hsync output (HSOUT) and the data clock (DATACK).

In the AD9985A, three things happen to horizontal synchronization: First, the polarity of the Hsync input is determined, and therefore has a known output polarity. Known output polarity can be programmed as active high or active low (Register 0x0E, Bit 5). Second, HSOUT is aligned with the packet and data output. Third, the duration of HSOUT (pixel clock) is set via Register 0x07. HSOUT is the sync signal that should be used to drive the rest of the display system.

taxi time

In most computer systems, the Hsync signal is provided continuously over a dedicated line. In these systems, the coasting input and function are unnecessary and should not be used, and the pins should be permanently connected to the inactive state.

However, in some systems, Hsync is disturbed during vertical synchronization (Vsync). In some cases, the Hsync pulse disappears. In other systems, such as those using a composite sync (Csync) signal or embedded sync on green (SOG), Hsync includes equalization pulses or other distortion during Vsync. It is important to ignore these distortions in order to avoid disturbing the clock generator during Vsync. If the pixel clock PLL detects an extraneous pulse, it tries to lock to this new frequency and changes the frequency at the end of the Vsync period. Then it takes a few lines of correct Hsync timing to recover at the start of a new frame, causing the image to tear at the top of the display.

Coast input is provided to eliminate this problem. It is an asynchronous input that disables the PLL input and allows the clock to run freely at its current frequency. The PLL can run several lines freely without significant frequency drift.

2-Wire Serial Register Map

The AD9985A is initialized and controlled by a set of registers that determine the mode of operation. An external controller is used to write and read control registers through the 2-wire serial interface port.

Two-wire serial control register detailed chip identification

00 7–0 Chip Revision

An 8-bit register representing the silicon version.

Crossover Control

01 7–0 PLL divided by MSBs

The 12-bit PLL divides the 8 most significant bits of PLLDIV. (The operating split ratio is PLLDIV+1.)

The PLL derives the master clock from the incoming Hsync signal. The master clock frequency is then divided by the integer value so that the output is locked to Hsync. The PLLDIV value determines the number of pixels per line (pixels plus horizontal blanking overhead). This is typically 20% to 30% more than the number of active pixels in the display.

The 12-bit value of the PLL divider supports division ratios from 2 to 4095. The higher the value loaded in this register, the higher the resulting clock frequency relative to the fixed Hsync frequency.

VESA has established some standard timing specifications to help determine the value of PLLDIV as a function of horizontal and vertical display resolution and frame rate (Table 8).

However, many computer systems do not comply. To be precise, these numbers should only be used as a guide. The display system manufacturer should provide a means to automatically or manually optimize the PLLDIV. An incorrectly set PLLDIV will often produce one or more vertical noise bars on the display. The larger the error, the higher the number of bars produced.

The power-on default for PLLDIV is 1693 (PLLDIVM=0x69, PLLDIVL=0xDx).

The AD9985A only updates the full divide ratio when the LSB is changed. Writing to the MSB alone does not trigger an update.

02 7–4 PLL division ratio lsb

The 12-bit PLL divides the 4 least significant bits of PLLDIV. The operating split ratio is PLLDIV+1.

The power-on default for PLLDIV is 1693 (PLLDIVM=0x69, PLLDIVL=0xDx). The AD9985A only updates the full divide ratio when writing to this register.

Clock Generator Control

03 7–6 VCO range selection

Two bits that determine the operating range of the clock generator.

VCORNGE must be set to the desired operating frequency (input pixel rate).

Phase-locked loops provide the best jitter performance at high jitter frequencies. For this reason, in order to output a low pixel rate and still get good jitter performance, the PLL actually operates at a higher frequency, but then divides the clock rate by . Table 11 shows the pixel rate for each VCO range setting. The PLL output divisor is automatically selected by the VCO range setting.

03 5–3 Current Charge Pump Current

Three bits of current that drive the loop filter are established in the clock generator. The current must be set to correspond to the desired operating frequency (input pixel rate).

04 7–3 Clock Phase Adjustment

A 5-bit value that adjusts the sampling phase in 32 steps within one pixel time. Each step represents an 11.25° displacement of the sampling phase.

The power-up default is 16.

Clamp timing

05 7–0 Fixture Placement

An 8-bit register that sets the position of an internally generated clamp.

When the clamp function (Register 0x0F, Bit 7) = 0, the a clamp signal is generated internally for the position determined by the clamp and for the duration set by the clamp duration. Begin clamping (clamp placement) the pixel period after the trailing edge of Hsync. The clamp position can be programmed to any value between 1 and 255.

The clamp should be placed during the time period when the input signal exhibits a stable black level reference, usually the back porch cycle between Hsync and the picture.

When clamp function = 1, this register is ignored.

06 7–0 Clamping Duration

An 8-bit register that sets the duration of an internally generated clamp.

For best results, the clamp duration should be set to include most of the black reference signal time after the trailing edge of the Hsync signal. Insufficient clamping time produces brightness changes at the top of the screen and slow recovery from large changes in average picture level (APL) or brightness.

When clamp function = 1, this register is ignored.

Sync pulse width

07 7–0 Hsync output pulse width

An 8-bit register that sets the duration of the Hsync output pulse.

The leading edge of the Hsync output is triggered by an internally generated phase-adjusted PLL feedback clock. The AD9985A then counts the number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase adjusted.

input gain

08 7–0 Red channel gain adjustment (red gain)

An 8-bit word that sets the gain of the red channel. The AD9985A accommodates input signals with a full-scale range between 0.5 V and 1.0 V pp. Setting REDGAIN to 255 corresponds to a 1.0 V input range. A gain of 0 in red represents a 0.5 V input range. Increasing the red gain results in less contrast in the image (fewer available converter codes for the input signal). See Figure 4.

09 7–0 Green Channel Gain Adjustment (Green Gain)

An 8-bit word that sets the green channel gain. See Red Gain (08).

0A 7–0 Blue channel gain adjustment (blue gain)

An 8-bit word that sets the gain of the blue channel. See Red Gain (08).

input offset

0B 7–1 Red channel offset adjustment

This offset register and the following registers have two modes of operation. One mode is when the auto offset function is off (manual mode), and the other mode is when the auto offset is on.

When in manual offset adjustment mode (auto offset off), this register behaves exactly like the AD9883A. It is a 7-bit offset binary word that sets the DC offset of the red channel. One LSB of offset adjustment is equal to one LSB change in ADC offset. Therefore, the absolute magnitude of the offset adjustment varies with the channel gain. A nominal setting of 63 would cause the channel to nominally clamp the back porch (during the clamping interval) to code 00. An offset setting of 127 will cause the channel to clamp to code 64 of the ADC. Offset is set to 0 clamp to code –63 (offset from bottom of range). Increasing the value of Red Offset reduces the brightness of the channel.

When in auto-offset mode, the value in this register adds digitally to the red channel ADC output. The purpose of this is to match the operation with manual offset adjustments. Adjusting these registers is an easy way to make brightness adjustments.

While this method loses some signal range, it has proven to be a very popular function. To be able to increase and decrease brightness, in this mode the values in these registers are signed two's complement (compared to manual mode, the values in such registers are binary). The digital adder is only used in auto-offset mode. Although it cannot be disabled, setting this register to all 0s effectively disables it by always adding 0s.

0C 07–1 Green Channel Offset Adjustment

This register works exactly like the red channel offset adjustment register (0x0B), except it is used for the green channel.

0D 7–1 Blue channel offset adjustment

This register works exactly like the red channel offset adjustment register (0x0B), except it is used for the blue channel.

Mode Control 1

0E 7 Hsync input polarity override

This register is used to override the internal circuitry that determines the polarity of the Hsync signal entering the phase locked loop.

The default value for Hsync polarity override is 0 (polarity is determined by the chip).

0E 6 HSPOL Hsync input polarity

A bit that must be set to indicate the polarity of the Hsync signal applied to the PLL Hsync input.

Active low indicates that the leading edge of the Hsync pulse is negative. All timings are based on the leading edge of Hsync, the falling edge. A rising edge has no effect.

Active high is reversed from traditional Hsync, with a positive pulse. This means that the timing is based on the leading edge of Hsync, which is now the rising edge.

If this bit is not set correctly, the device will operate but the internally generated clamp established by clamp placement (Register 0x05) is not placed as expected, which may produce a clamp error.

0E 5 Sync output polarity

This bit determines the polarity of the Hsync output and SOG output. Table 15 shows the effect of this option. SYNC represents the logic state of the sync pulse.

0E 4 Active Hsync Override

This bit is used to override automatic Hsync selection. To override, set this bit to logic 1. On rewrite, the active Hsync is set via Bit 3 in this register.

0E 3 Active Hsync Select

This bit is used in two situations. It is used to select the active Hsync when the override bit (bit 4) is set. Alternatively, it is used to determine the active Hsync when not overriding, but both Hsyncs are detected at the same time.

0E 2 Vsync output inverted

The polarity of the bit-reversed Vsync output Table 18 shows the effect of this option.

0E 1 active Vsync overlay

This bit is used to override automatic Vsync selection. To override, set this bit to logic 1. When rewritten, the active interface is set via Bit 0 in this register.

0E 0 Active Vsync Select

This bit is used to select the active Vsync when the rewrite bit (bit 1) is set.

OF 7 clamp input signal source

This bit determines the source of the clamp timing.

result

Internally generated clamp signal (power on by default), externally provided clamp signal.

0 enables the clamp timing circuit controlled by clamp and clamp duration. The clamping position and duration are calculated from the leading edge of Hsync.

A 1 Enable external clamp input pin. When the clamp signal is activated, the three channels are clamped. The polarity of the clamp is determined by the Clamp Polarity bit (Register 0x0F, Bit 6).

0F 6 clamp input signal polarity

This bit determines the polarity of the externally supplied clamp signal.

A logic 1 means that the circuit clamps when the clamp is low, and the circuit passes the signal to the ADC when the clamp is high.

A logic 0 indicates that the circuit is clamped when the clamp is high, and the circuit passes the signal to the ADC when the clamp is low.

0F 5 Shore Selection

This bit is used to select the active coast source. Selectable COAST input pin or Vsync. If Vsync is selected, an additional decision needs to be made to use the Vsync input pin or the output of the sync splitter (Register 0x0E, Bits 1, 0).

0F 4 Coast Input Polarity Override

This register is used to override the internal circuitry that determines the polarity of the coast signal entering the PLL.

0F 3 Coasting Input Polarity

This bit indicates the polarity of the Coast signal applied to the PLL Coast input.

Active low means that when Coast is low, the clock generator ignores the Hsync input and continues to operate at the same nominal frequency until Coast is high.

Active high means that the clock generator ignores the Hsync input when Coast is high and continues to operate at the same nominal frequency until Coast goes low.

This feature needs to be used in conjunction with the Coast Polarity Override bit (bit 4).

0F 2 Seek Mode Override

This bit is used to enable or disable low power modes. A low power mode (seek mode) occurs when there is no signal on any of the sync inputs.

0F 1 password

This bit is used to completely power down the chip. See the Power Management section for details on which blocks are powered off.

10 7-3 Green Slicer Sync Threshold

This register allows adjustment of the synchronized comparator threshold on the green slicer. This register adjusts it in 10 mV steps, with the minimum setting equal to 10 mV (11111) and the maximum setting equal to 330 mV (00000).

The default setting is 23, corresponding to a threshold of 100 mV; for a threshold of 150 mV, the setting should be 18.

102 red clamp options

This bit determines whether the red channel is fixed to ground or to the midscale. For RGB video, all three channels are referenced to ground. For YCbCr (or YUV), the Y channel is referenced to ground, but the CbCr channel is referenced to the midscale.

Clamping to mid-scale actually clamps to pin 37 .

10 1 Green Clamp Selection

This bit determines whether the green channel is fixed to ground or to the midscale.

10 0 blue clamp options

This bit determines whether the blue channel is fixed to ground or to midscale.

11 7–0 Sync Splitter Threshold

This register is used to set the response of the sync delimiter. It sets the number of internal 5MHz clock cycles that the sync separator must count before switching high or low. It works like a low pass filter, ignoring the Hsync pulses to extract the Vsync signal. This register should be set to some number greater than the maximum HSYNC pulse width. The sync separator threshold uses an internal dedicated clock with a frequency of approximately 5 MHz.

The default value of this register is 32.

12 7–0 Coast Front

This register allows the coast signal to be applied before the Vsync signal. This is necessary in the presence of pre-equalization pulses. The step size of this control is one Hsync cycle.

The default value is 0.

13 7–0 Back Coast

This register allows the coast signal to be applied after the Vsync signal. This is necessary when post-equalization pulses are present. The step size of this control is one Hsync cycle.

The default value is 0.

14 7 Sync detection

This bit is used to indicate when activity is detected on the Hsync input pin (pin 30). If Hsync remains high or low, no activity will be detected.

The synchronization processing block diagram (Figure 14) shows where this function is implemented.

146 Active Synchronization (AHS)

This bit indicates which Hsync input source is being used by the PLL (green for Hsync input or sync). Bits 7 and 1 in the register determine which source is used. If both Hsync and SOG are detected, the user can determine which has priority via Bit 3 in Register 0x0E. The user can pass Bit 4 in Register 0x0E. If the rewrite bit is set to logic 1, this bit is set to the state of Bit 3 in Register 0x0E.

AHS=0 means use Hsync pin input for Hsync.

AHS=1 means use the SOG pin input of Hsync.

The rewrite bit is in Register 0x0E, Bit 4.

14 5 Hsync input polarity status detected

This bit reports the status of the Hsync input polarity detection circuit. It can be used to determine the polarity of the Hsync input. The location of the detection circuit is shown in the synchronization process block diagram (Figure 14).

14 4 Vertical sync detection

This bit is used to indicate when activity is detected on the Vsync input pin (pin 31). If Vsync remains steady high or low, no activity is detected.

The synchronization processing block diagram (Figure 14) shows where this function is implemented.

143 Active Vsync (AVS)

This bit indicates which Vsync source, Vsync input or output of the sync separator is being used. Bit 4 of this register determines which is active. If both Vsync and SOG are detected, the user can determine which has priority via Bit 0 in Register 0x0E. The user can override this function via Bit 1 in Register 0x0E. If the rewrite bit is set to logic 1, this bit is set to the state of Bit 0 in Register 0x0E.

AVS=0 means Vsync input.

AVS=1 means synchronization separator.

The rewrite bit is in Register 0x0E, Bit 1.

14 2 Vsync output polarity status detected

This bit reports the status of the Vsync output polarity detection circuit. It can be used to determine the polarity of the Vsync output. The location of the detection circuit is shown in the synchronization process block diagram (Figure 14).

14 1 Sync on Green Detection

This bit is used to indicate when sync activity is detected on the sync on green input pin (pin 49).

The synchronization processing block diagram (Figure 14) shows where this function is implemented.

14 0 Coastal polarity status detected

This bit reports the status of the coasting input polarity detection circuit. It can be used to determine the polarity of the coast input. The location of the detection circuit is shown in the synchronization process block diagram (Figure 14).

This means that bit 1 of register 5 is the 4:2:2 output mode select bit.

15 1 4:2:2 output mode selection

Configure the bits of the output data in 4:2:2 mode. This mode can be used to reduce the number of data lines from 24 to 16 for applications using YUV, YCbCr or YPbPr graphics signals. The timing diagram for this mode is shown in Figure 11.

Recommended input and output configurations are shown in Table 39 and Table 40.

16 7 additional PLL dividers

One can add an extra divide-by-2 bit to the PLL divide ratio. Enabling this feature at pixel frequencies below 20mhz can improve PLL jitter performance because it allows the VCO to operate at a higher frequency, which reduces jitter.

16 6-5 SOGIN bandwidth

Two bits, can control the bandwidth of the syncon green input (SOGIN). In most applications, the SGIN bandwidth should be set to its maximum value (300 MHz). When there is too much noise on SOGIN, reducing the bandwidth can help suppress the noise.

16 4 analog input bandwidth

This bit controls the bandwidth of the red, green, and blue analog inputs. In most applications, the analog input bandwidth should be set to its maximum value (300 MHz). When there is excessive noise on the analog input, reducing the bandwidth can help suppress the noise.

19 7:0 Red target code

This specifies the target value for the final offset of the red channel when using automatic offset (register 0x1D, bit 7=1). The default value is 4.

1A 7:0 green target code

This specifies the target value for the final offset of the green channel when using automatic offset (Register 0x1D, Bit 7 = 1). The default value is 4.

1B 7:0 blue target code

This specifies the target value for the final offset of the blue channel when using automatic offset (register 0x1D, bit 7=1). The default value is 4.

1 7 Auto Offset Enable

Enable automatic offset circuit. The default value is 0.

1 6 keep auto offset

Save the offset output of the auto offset at the current value. The default value is 0.

1 1:0 update mode

Change the update rate of automatic offsets. The default value is 10.

2-wire serial control port

Provides a 2-wire serial interface control interface. Two AD9985A devices can be connected to the 2-wire serial interface; each device has a unique address.

The 2-wire serial interface includes clock (SCL) and bidirectional data (SDA) pins. The analog tablet interface acts as a slave to receive and transmit data over the serial interface. When the serial interface is inactive, the logic levels on SCL and SDA are pulled high by external pull-up resistors.

Data received or transmitted on the SDA line must remain stable during the SCL positive pulse. Data on SDA can only be changed when SCL is low. If SDA changes state while SCL is high, the serial interface interprets the operation as a start or stop sequence.

Components of serial bus operation include: start signal; slave address byte; base register address byte; read or write data byte; stop signal.

Communication is initiated by sending a start signal when the serial interface is inactive (SCL and SDA high). When SCL is high, the start signal on SDA is a high-to-low transition. This signal alerts all slaves that a data transfer sequence is imminent.

The first 8 bits of data transmitted after enabling signal com-prise a 7-bit slave address (first 7 bits) and an R/W bit (eighth bit). The R/W bit indicates the data transfer direction for reading from (1) or writing (0) the slave device. If the transmitted slave address matches the device address (set by the state of the SA1-0 input pins in Table 45), the AD9985A acknowledges by driving SDA low on the ninth SCL pulse. If the addresses do not match, the AD9985A does not acknowledge.

Table 45. serial port address

Data transfer via serial interface

For each data byte read or written, the MSB is the first bit in the sequence.

If the AD9985A does not acknowledge the master during the write sequence, SDA is held high so that the master can generate a stop signal. If the master device does not acknowledge the AD9985A during the read sequence, the AD9985A interprets this as an end of data. SDA is held high so that the host can generate a stop signal.

Writing data to a specific control register of the AD9985A requires writing the 8-bit address of the control register of interest after the slave address is established. This control register address is the base address for subsequent write operations. After the base address is auto-incremented by one byte of data, the data byte written is expected to be the base address.

Data is read from the AD9985A's control register in a similar fashion. A read requires two data transfer operations:

The base address must be written with the lower R/W bits of the slave address byte to set up sequential read operations.

Reads (high R/W bits of the slave address byte) start from the previously established base address. The address of the read register is automatically incremented after each byte transfer.

To terminate the read/write sequence to the AD9985A, a stop signal must be sent. The stop signal consists of a low-to-high transition of SDA when SCL is high.

Repeated start signals occur when a master device driving a serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the communication mode (read, write) between slave and master without releasing the serial

Serial interface read/write example to write to a control register:

1. Start signal

2. Slave address byte (R/W bit = low)

3. Base address byte

4. Data byte to base address

5. Stop signal

Write four consecutive control registers:

1. Start signal

2. Slave address byte (R/W bit = low)

3. Base address byte

4. Data byte to base address

5. Data byte to (base address + 1)

6. Data byte to (base address + 2)

7. Data byte to (base address + 3)

8. Stop signal

Reading from a control register:

1. Start signal

2. Slave address byte (R/W bit = low)

3. Base address byte

4. Start signal

5. Slave address byte (R/W bit = high)

6. Data byte from base address

7. Stop signal

Read from four consecutive control registers:

1. Start signal

2. Slave address byte (R/W bit = low)

3. Base address byte

4. Start signal

5. Slave address byte (R/W bit = high)

6. Data bytes from base address

7. Data byte slave (base address + 1)

8. Data byte slave (base address + 2)

9. Data byte slave (base address + 3)

10. Stop signal

Sync Slicer

The purpose of the sync slicer is to extract the sync signal from the green graphics channel. The sync signal is not present in all graphics systems, only those that are synced to green. The sync signal is extracted from the green channel in a two-step process. First, clamp the SOG input to its negative peak (typically, 0.3v below black level). Next, the signal goes to a comparator with a variable trigger level, nominally 0.15v above the clamp level. Slice sync is usually a composite sync signal containing Hsync and Vsync.

sync separator

The sync separator extracts the Vsync signal from the composite sync signal. It is implemented by a low-pass filter or integrator-like operation. It works by keeping the Vsync signal active much longer than the Hsync signal, so it rejects anything smaller than a threshold, which is between the Hsync pulse width and the Vsync pulse width.

The sync separator on the AD9985A is just an 8-bit digital counter with a 5 MHz clock. It works independently of the polarity of the composite sync signal. (The polarity is decided elsewhere on the chip) The basic idea is that the counter counts when there is an Hsync pulse. But due to the relatively short width of the Hsync pulse, the counter only reaches the value of N before the end of the pulse. The countdown then begins, eventually reaching 0 before the next Hsync pulse arrives.

The specific value of N varies with the video mode, but is always less than 255. For example, for a 1µs wide Hsync, the counter only reaches 5 (1µs/200 ns = 5). Now, when Vsync appears on composite sync, the counter also counts. However, since the Vsync signal is much longer, it counts to a higher number M. M is at least 255 for most video modes. Therefore, when the counter counts to a value greater than N, Vsync can be detected by detecting the composite sync signal. The specific count for trigger detection (T) can be programmed through the serial register (0x11).

Once Vsync is detected, there is a similar process to detect when it becomes inactive. On detection, the counter first resets to 0, then starts counting when Vsync disappears. Similar to the previous case, it detects the lack of Vsync when the counter reaches the threshold count (T). In this way, it suppresses noise and/or sawtooth pulses. Once the absence of Vsync is detected, the counter will reset to 0 and start the loop again.

PCB Layout Recommendations

The AD9985A is a high-precision, high-speed analog device. So in order to get the maximum performance part, it is important to have a good layout board. This section provides guidelines for designing a board using the AD9985A.

Analog interface input

It is important to use the following layout techniques on the graphics input side.

Minimize trace length into graphics input. This is achieved by placing the AD9985A as close as possible to the graphics VGA interface. Long input trace lengths are undesirable as they will pick up more noise from the board and other external sources.

Place the 75Ω termination resistor (see Figure 1) as close as possible to the AD9985A chip. Any additional track length between the termination resistor and the AD9985A input will increase the magnitude of the reflection, which can damage the graphic signal. Traces were recorded using 75Ω matched impedance. Tracking impedances other than 75Ω also increase the chance of reflections.

The AD9985A has a very high input bandwidth (500 MHz). While this is desirable for acquiring high-resolution PC graphics signals with fast edges, it means it also captures any high-frequency noise present. Therefore, it is important to reduce the amount of noise coupled to the input. Avoid running any digital traces near analog inputs.

Due to the high bandwidth of the AD9985A, low-pass filtering of the analog input can sometimes help reduce noise. (For many applications, filtering is unnecessary.) Experiments have shown that placing a series of ferrite beads before the 75Ω termination resistor helps filter out unwanted noise. Specifically, the part used is #2508051217Z0 from FairRite, but each application can use a different bead value. Also, it is beneficial to place a 100Ω to 120Ω resistor between the 75Ω termination resistor and the input coupling capacitor.

power bypass

A 0.1µF capacitor is recommended to bypass each supply pin. The exception is when two or more power pins are next to each other. For these power/ground groupings, only one bypass capacitor is required. The basic idea is to have a bypass capacitor within 0.5cm of each power pin. Also, avoid placing capacitors on the other side of the AD9985A's PC board, as this will insert resistive vias in the path.

Bypass capacitors should be located between the power plane and the power pins. Current should flow from the power plane to the capacitors and power pins. Do not make power connections between capacitors and power pins. Placing vias under the capacitor pads, all the way to the power plane, is usually the best approach.

It is especially important to maintain low noise and good stability PV (clock generator power). Sudden changes in PV can lead to similar changes in sampling clock phase and frequency. This can be avoided by careful attention to conditioning, filtering and bypassing. It is highly desirable to have separate regulated power supplies for each analog circuit group (V and PV).

Some graphics controllers use very different power levels when active (during active picture time) and idle (during horizontal and vertical sync). This results in a measurable change in the voltage supplied to the analog power regulator, which in turn produces a change in the regulated analog supply voltage. This can be mitigated by adjusting the analog supply or at least the PV from a different clean supply (eg from a 12v supply).

It is recommended to use a single ground plane for the entire board. Experience has shown time and time again that single-surface noise performance is equal or better. Using multiple ground planes can be detrimental because each individual ground plane is smaller and can result in long ground loops.

When a separate ground plane is unavoidable, it is recommended to place at least one separate ground plane under the AD9985A. The location of the split should be at the receiver of the digital output. In this case, it's more important to place components wisely because the current loop is much longer (the path for the current to have the least resistance). Figure 15 shows an example of a current loop.

phase locked loop

Place the PLL loop filter components as close as possible to the filter pins. Do not place any digital or other high frequency traces near these parts. Use a value with a tolerance of 10% or less suggested in the data sheet.

output (data and clock)

Minimize the trace length that the digital output must drive. Longer traces have higher capacitance, which requires more current, which results in more internal digital noise. Shorter trajectories reduce the chance of reflections.

Adding a 22Ω to 100Ω series resistor inside the AD9985A suppresses reflections, reduces EMI, and reduces current spikes. However, if 50Ω traces are used on the PCB, no resistors are required for the data output. The 22Ω resistor at the packet output should provide good impedance matching to reduce reflections. If a series resistor is used, it should be placed as close as possible to the AD9985A pins (but try not to add vias or extra length to the output trace to bring the resistors closer together).

If possible, limit the capacitance driven by each digital output to less than 10 pF. This can easily be achieved by keeping the traces short and connecting the output to only one device. Loading the output with excessive capacitance increases the current transients inside the AD9985A, creating more digital noise on its power supply.

digital input

The digital inputs on the AD9985A are designed for 3.3V signals, but allow 5.0V signals. Therefore, if 5.0V logic is used, no additional components need to be added. Any noise entering the Hsync input tracking will add jitter to the system. Therefore, try to minimize the track length and do not run any digital or other high frequency tracks near it.

voltage reference

Bypass the voltage reference with a 0.1µF capacitor. Place it as close as possible to the AD9985A pins. Keep the ground connection as short as possible.

Dimensions