feature

Single and quad AD8041 AD8044 also available; fully specified at +3 V, +5 V, and ±5 V supplies; outputs within 30 mV of either rail; input voltage range extends to 200 mV below ground; input voltages over No phase reversal at 0.5V; low power at 5.2mA per amplifier; high-speed fast settling at 5V; 160MHz , -3dB bandwidth (G=+1); 200 V/µs slew rate; 39 ns settling time 0.1%; good video specs (RL=150Ω, G=+2); gain flatness 0.1db to 14mhz; 0.02% differential gain error; 0.04° differential phase error; low distortion: -64 dBc maximum at 10 MHz Poor harmonics; 0.5V driven 50mA from the supply rail.

application

Video switches; distribution amplifiers; analog to digital drives; professional cameras; CCD imaging systems; ultrasound equipment (multi-channel).

General Instructions

The AD8042 is a low-power, voltage-feedback, high-speed amplifier designed for use with +3 V, +5 V, or ±5 V supplies. It has true single-supply capability with an extended input voltage range of 200 mV below the negative rail and within 1 V of the positive rail.

The output voltage swing extends to within 30 mV per rail, providing maximum output dynamic range. In addition, it has gain flatness of 0.1dB to 14mhz, while providing differential gain and phase errors of 0.04% and 0.06° on a single 5v supply. The combination of these features makes the AD8042 very useful for professional video electronics such as cameras, video switchers, or any high-speed portable device. The low distortion and fast settling of the AD8042 make it ideal for buffering single-supply, high-speed analog-to-digital converters (ADCs).

The AD8042 provides a low supply current of 12mA maximum and can operate from a single 3.3V supply. These features are ideal for portable and battery-powered applications where size and power are critical.

The wide frequency band of 160mhz and the slew rate of 200v/µs on a single 5v supply make the AD8042 useful in many general purpose, high speed applications where a single supply from +3.3v to +12v and dual supplies up to ±6v are required . The AD8042 is available in 8-lead PDIP and 8-lead SOIC UN packages.

Absolute Maximum Ratings

Stresses listed above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Maximum power consumption

The maximum power that can be safely dissipated by the AD8042 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic packaged devices is determined by the glass transition temperature of the plastic, which is approximately 150°C. Temporarily exceeding this limit results in a change in parametric performance due to changes in the stress the package imposes on the mold.

Junction temperatures in excess of 175°C for extended periods of time can cause device failure.

Although the AD8042 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) will not be exceeded under all conditions. To ensure correct operation, it is necessary to observe the maximum power derating curve.

application information

Circuit Description

The AD8042 is fabricated on Analog Devices, Inc.'s proprietary ultrafast complementary bipolar (XFCB) process, which enables PNP and NPN transistors to have similar fs in the 2 GHz to 4 GHz region. The process is isolated to eliminate parasitic and latch-up issues caused by junction isolation. These features allow the construction of high frequency, low distortion amplifiers with low supply current. This design uses a differential output input stage to maximize bandwidth and headroom (see Figure 35). The smaller signal fluctuations required at the first stage outputs (nodes SIP, SIN) reduce the effects of nonlinear currents due to junction capacitance, improving distortion performance. With this design, on a single 5V supply, with V=2V pp (gain=+2), the harmonic distortion can reach 100Ω at 1MHz, which is better than -77dB.

The rail-to-rail output range of the AD8042 is provided by the complementary common transmitter output stage. High output drive capability is provided by direct injection of pre-flow for all output stages into the bases of output devices Q8 and Q36. Biasing of Q8 and Q36 is done by I8 and I5 and a common mode feedback loop (not shown). This circuit topology allows the AD8042 to drive 40 mA of output current with an output voltage within 0.5 volts of the supply rails.

On the input side, the device can handle voltages ranging from 0.2V below the negative rail to 1.2V from the positive rail. Exceeding these values will not cause phase reversal; however, if the input voltage exceeds the rail by 0.5 V, the input ESD device does begin to conduct.

Driving capacitive loads

The capacitive load drive of the AD8042 can be increased by placing a low value resistor in series with the load. Figure 36 shows the effect of a series resistor on capacitive drive for different voltage gains. The larger phase margin allows for larger capacitive loading and less overshoot as the closed-loop gain increases. Adding a series resistor with lower closed-loop gain can achieve the same effect. For large capacitive loads, the frequency response of the amplifier is primarily determined by the rollover of the series resistive and capacitive loads.

overdrive recovery

Amplifier overdrive occurs when the output and/or input range is exceeded. The amplifier must recover from this overdrive state. As shown in Figure 37, the AD8042 recovers from negative overdrive in 30 ns and from positive overdrive in 25 ns.

Single Supply Composite Video Line Driver

The AD8042's two op amps can be configured as single-supply, two-line drivers for composite video. The wide signal swing of the AD8042 enables this function to be performed without the use of any type of clamping or DC restoration circuitry, which can cause signal distortion.

Figure 38 shows a schematic diagram of a circuit driven by an AC-coupled, level-shifted composite video source and applied to the two non-vertical inputs of two amplifiers.

Each op amp provides a separate 75Ω composite video output. To obtain single-supply operation, AC coupling is used throughout. Large capacitor values are required to ensure that the video signal has minimal skew due to its low frequency (30hz) signal content. The circuit shown has a differential gain of 0.06% and a differential phase of 0.06°.

The input is terminated in 75Ω and is AC coupled through C to a voltage divider that provides a DC bias point for the input. Setting the optimum bias point requires an understanding of the nature of the composite video signal and the video performance of the AD8042.

The bounded peak-to-peak amplitude has a larger dynamic swing when the duty cycle changes than the peak-to-peak amplitude after AC coupling. In the worst case, the dynamic signal swing needs to be close to twice the peak value. Both of these limiting cases apply when the duty cycle is mostly low, but occasionally rises at a small fraction of the duty cycle, and vice versa.

Composite video does not have such high requirements. A limit is for a signal that is mostly black throughout the frame, but has a white (full intensity), minimum width spike at least once per frame.

At the other extreme is a video signal with white everywhere. The blanking interval and sync cue of such a signal have negative drift in accordance with the composite video specification. The combination of horizontal and vertical blanking intervals limits such a signal to the highest level (white) approximately 75% of the time.

Due to the presented duty cycle variation between the two extremes, a 1v pp composite video signal multiplied by a gain of 2 requires a dynamic voltage swing of about 3.2v pp at the output in order for the op amp to pass any duty cycle without distortion composite video signal.

Some circuits use a sync tip clamp and AC coupling to keep the sync tip at a relatively constant level, reducing the amount of dynamic signal swing required. However, these circuits may have artifacts, such as sync tip compression, unless they are driven by sources with very low output impedance.

Not only does the AD8042 have sufficient signal swing capability to handle the required dynamic range without the use of sync-tip clamps, but it also has good video specifications such as differential gain and differential phase when buffering these signals in an AC-coupled configuration.

To test the dynamic range, the differential gain and differential phase of the AD8042 were measured over supply changes. The first effect observed when the lower power supply is raised close to the video signal is that the sync tip is compressed before the differential gain and differential phase are adversely affected. So there must be enough wiggle in the negative direction to pass the sync cue without compression.

When the upper supply is lowered to approach video, the differential gain and differential phase are not significantly affected until the difference between the peak video output and the supply reaches 0.6V. Therefore, the highest video level should be kept at least 0.6V below the positive supply rail.

Therefore, we found that the best bias point for non-vertical inputs is 2.2v dc. At this point, the worst-case differential gain measurement is 0.06% and the volute differential phase is 0.06°.

The AC coupling capacitors used in the circuit look quite large at first glance. Composite video signals have a lower band edge of 30hz. At various points of AC coupling, especially at the output, the resistance is small. To reduce phase shift and baseline tilt, large value capacitors are required. For video system performance that is not of the highest quality, the value of these capacitors can be reduced by up to a factor of 5 with only a slight observable change in image quality.

Single-ended to differential driver

The AD8042 uses a cross-coupled, single-ended differential converter (SEDC) and is a good general-purpose differential line driver. This SEDC can be used for applications such as driving Category 5 (CAT-5) twisted pair cables. Figure 39 shows the configuration of a circuit that performs this function, which can be used for video transmission over a differential pair or for various data communication purposes.

Each op amp of the AD8042 is configured as a unity gain follower by a feedback resistor (R). Each op amp output also drives the other through R as a unity-gain inverter, forming a fully B-symmetric circuit.

If the non-rotating input of AMP2 is grounded and a small positive signal is applied to the non-rotating input of AMP1, the output of AMP1 is driven to saturation in the positive direction and the input of AMP2 is driven to saturation in the negative direction. This is similar to how traditional ops work without any feedback.

If a resistor (R) is connected from the output of AMP2 to the non-rotating input of AMP1, it provides negative feedback, thus closing the loop. An input resistor (R) makes the circuit look like a traditional inverting op amp configuration with differential outputs.

The circuit has a gain of ±R/R from input to output, or 2 × R/R from single-ended to differential, which allows the circuit to adjust its gain by changing a single resistor.

The characteristic impedance of the cable is about 120Ω. Each driver output has a pair of 60.4Ω resistors to make the power supply look like 120Ω. The receiving end is terminated with 121Ω, and a pair of oscilloscope probes are used to measure the signal differentially. Invert one channel on the oscilloscope, then add the signal.

Figure 40 shows the results of the circuit in Figure 39 driving 50 meters of CAT-5 cable.

Single Supply Differential A/D Driver

The single-ended to differential converter circuit can also be used as a video speed differential driver, single-ended differential input adc. Figure 41 is a schematic showing this circuit differentially driving an AD9220, 12-bit, 10 MSPS ADC.

The circuit was tested with an input signal of 1 MHz, clocked at 10 MHz. The FFT response of the digital output is shown in Figure 42.

Pin 5 is biased at 2.5 V by a voltage divider and bypassed.

This skews each output at 2.5 V. V is AC coupled, so V going positive makes VINA positive and VINB negative. The opposite happens for negative-going V.

HDSL Line Driver

High Bit Rate Digital Subscriber Line (HDSL) is a popular way to provide data communication at DS1 rate (1.544Mbps) over medium distance transmission lines over traditional telephone twisted pair wires. In these systems, client transceivers are sometimes routed from the central office via twisted pair. It is sometimes necessary to increase the DC voltage to compensate for long or narrow gauge wires.

Due to the IR drop, it is ideal to keep the power consumption of the customer's transceiver as low as possible. One way to achieve significant power savings is to run the transceiver from a ±5 V supply rather than more conventional ±12 V.

The high output swing and current drive capability of the AD8042 make it ideal for this application. Figure 43 shows the circuit for the analog portion of the HDSL transceiver using the AD8042 as the line driver.

Layout Considerations

The specified high-speed performance of the AD8042 requires attention to board layout and component selection. Proper RF design techniques and low-pass parasitic device selection are necessary. The printed circuit board should have a ground plane covering all unused part of the board component side to provide an impedance path. The ground plane should be taken from the area near the input pins to reduce stray capacitance.

Power supply bypassing should use chip capacitors. One end should be connected to the ground plane and the other within ⅛ inches of each power pin. Another large (0.47µF vs. 10µF) tantalum electrolytic capacitor should go in parallel, but not necessarily so close to the supply current, that the output signal varies greatly. The feedback resistor should be placed close to the inverter input pins to keep stray capacitance at this node to a minimum. Capacitance changes of less than 1pF reverse input significantly affect high-speed performance.

Long signals should use stripline design technology traces (greater than about 1 inch). These should be properly terminated with a design characteristic impedance of 50Ω or 75Ω at each end.

Dimensions