illustrate

The FS7140 or FS7145 are monolithic CMOS clock generator/regenerator integrated circuits designed to minimize cost and component count for various electronic systems. The FS7140/45 can accommodate many clock generation requirements through the I2C bus interface. The length granularity of the reference and feedback dividers and the flexibility of the postscaler make the FS7140/45 the most flexible stand-alone PLL clock generator available.

feature

Extremely flexible, low-jitter phase-locked loop (PLL) frequency synthesis No external loop filter components 150 MHz CMOS or 340 MHz PECL output fully configurable via I2C bus Up to four FS714x3.3 V operation on a single I2C bus Crystal oscillator and external reference input with very low "accumulated" jitter available in lead-free packaging

application

Precise Frequency Synthesis

low frequency clock multiplication

Video Line Lock Clock Generation

Laser beam printer (FS7145)

Keys: AI: analog input; AO=analog output; DI=digital input; DIU=input with in-band pull-up; DID=input with in-band pull-down; DIO=digital input/output; DI-3=three-level digital input ;DO=digital output; P=power/ground; #=active low pin

Table 2. Absolute Maximum Ratings

Stresses exceeding the maximum ratings may damage the device. Maximum ratings are stress ratings only. Functional operation above the recommended operating conditions is not implied. Prolonged exposure to stresses higher than recommended operating conditions may affect device reliability. WARNING: Electrostatic Sensitive Devices If this equipment is subjected to high-energy electrostatic discharge.

Table 3. Operating Conditions

Table 4. DC Electrical Specifications (Note 1)

1. Unless otherwise stated, VDD = 3.3V% 10%, no load on any output, ambient temperature range TA with an asterisk (*) indicates nominal characteristic data and does not create any specific limited entity. Min and max feature data are from typical. Negative current indicates flow out of the device.

Table 5. AC Timing Specifications (Note 2)

2. Unless otherwise stated, VDD = 3.3V% 10%, no load on any output, ambient temperature range TA with an asterisk (*) indicates nominal characteristic data and does not create any specific limited entity. Min and max feature data are from typical.

Table 6. Serial Interface Timing Specifications (Note 3)

3. Unless otherwise stated, VDD = 3.3V% 10%, no load on any output, ambient temperature range TA with an asterisk (*) indicates nominal characteristic data and does not create any specific limited entity. Min and max feature data are from typical.

phase locked loop

A phase locked loop is a standard phase and frequency locked loop architecture. The PLL consists of a reference voltage divider, a phase frequency detector (PFD), charge pump, internal loop filter, a voltage controlled oscillator (VCO), a feedback divider and a postscaler. The reference frequency (either from the on-board crystal oscillator or an external frequency source) is first reduced by the reference divider. The integer value frequency divided by the NR known as the modulo is expressed as the reference divider. This split is then fed into the PFD. The VCO frequency passes through the feedback divider (modulo is denoted by NF). The PFD will drive the VCO frequency up or down until the divided reference frequency and the divided VCO frequency appearing at the input of the PFD are equal. The difference between this reference frequency The input/output relationship VCO frequency is: This basic PLL equation can be rewritten as

The pole divider (actually a series of combined dividers of three poles) follows the final equation of the PLL and the device output frequency is:

reference voltage divider

The reference divider is designed for low phase jitter. This divider accepts either the crystal oscillator output circuit or an external reference frequency. The reference divider is a 12-bit divider that can be used for any modulo from 1 to 4095 (divide by 1, codes before 0108 are not available for dates). Feedback Divider The feedback divider is based on dual-modulus divider (also known as dual-modulus prescaler) technology. It allows division by any integer value between 12 and 16383. Simply program the desired modulus with the binary equivalent of the FBKDIV register. Selected modules below 12 are allowed. Modulo 4, 5, 8, 9 and 10 are also allowed (4 does not have 5 in date codes prior to 0108). Column Dividers The column dividers consist of three individually programmable dividers as shown.

The modes of the individual dividers are denoted NP1, NP2, and NP3, which together constitute the net present value of the array mode. NPX=NP1 x NP2 x NP3 The post-divider performs several useful functions. First, it allows the VCO to be generated when the device needs to generate compared to changes in the output clock speed. Second, the extra integer denominator allows for more flexibility. The cycle programming frequency must be accurately achieved for many applications. Note that the nominal 50/50 duty cycle is always the same (even for selections with odd modulo). See Table 12 for more information. The crystal oscillator FS7140 is equipped with a perforated crystal oscillator. The crystal operates in parallel resonant mode. Provides an internal load capacitor for the crystal. When the recommended load capacitance of the crystal is specified, other standard load capacitances of the crystal can be used for the high accuracy of the reference frequency (100 ppm or less) is not required. Reference Divider Source The frequency source of the MUX reference divider can be selected as the device crystal oscillator or the reference pin REFDSRC bit. When not using a crystal oscillator, it is best to connect XIN to VSS. Do not connect to XOUT. When the REF input is not in use, it is best to leave it floating or connect to VDD. Feedback Divider Source Multiplexer The frequency source of the feedback divider can be selected as the output of the post divider or the output VCO via the FBKDSRC bit.

Typically, for frequency synthesis, the output of the VCO is used. A reference clock is only required for a definite phase relationship between the output clocks (line lock mode, for example). Device Shutdown provides two bits to shut down the device when it is needed: when it is not active. SHUT1 disables most externally observable device functions. Off2 reduces device quiescent current to an absolute minimum. Normally, these two bits should be set or cleared together. Serial communication function is not disabled off 1 or off 2. Differential Output Stage The differential output stage supports both CMOS and Pseudo-ECL (PECL) signals. The desired output interface is selected by programming the registers. If a PECL interface is used, the transmission line is usually terminated with Severin. The output stage can only receive current in PECL mode, and the receiver current is locked by the /IPRG pin. The ratio of output leakage current to IPRG current is 13:1. The source current to the CLKx pin is terminated by a pull-up resistor that is part of Thévenin.

example

Let's say the PECL-style scallop that needs to be connected is right next to the FS7140. Further assumptions: VDD = 3.3 V Desired VHI = 2.4 V Desired VLO = 1.6 V Equivalent Load = 75 Ohms

Then: R1 (from CLKP and CLKN to VDD) = load * VDD/VHI = 75 * 3.3/2.4 times = 103 ohms R2 (from CLKP and CLKN to GND) = load * VDD/(VDD-VHI) = 75 *3.3/(3.3-2.4)=275 ohm Rprgm (from VDD to IPRG pin)=26*(VDD*R load)/(VHI-VLO)/3=26*(3.3*75)/(2.4-1.6 )/3 = 2.68 kΩ

Synchronous circuit

The FS7145 supports almost instant adjustment of the output clock phase of the sync input. Both sides sync direction (positive or negative) is supported. Example (positive sync selected): On the negative edge of the sync input, the sequence starts to stop the CLK output. On the positive edge, CLK resumes operation, synchronizing to the phase of the sync input (plus a determinate delay). This is made up of equipment column dividers. Phase resolution equal to the VCO period can be achieved (down to about 2 nanoseconds). I2C-Bus Control Interface This device is a read/write slave device that complies with all Philips I2C-bus specifications except "General Calls". The bus is clocked SCL by the master device that generates serial data, controls bus access and generates stop conditions that initiate when the device operates as a slave. Both master and slave can work as transmitter or receiver, but the master device decides which mode to activate. A device that sends data to the bus is defined as a transmitter, and a device that receives data as a receiver. I2C - The bus logic levels described here are based on a percentage of the power supply (VDD). A logic one corresponds to the nominal voltage of VDD, while a logic zero corresponds to ground (VSS). Data transfers on the bus status bus can only be done when the bus is not busy. During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. When the clock line is high, changes on the data line will be interpreted by the device as a start or stop condition. The following bus conditions are defined by the I2C bus protocol. Both the data line (SDA) and the clock line (SCL) remain on to indicate that the bus is not busy. A high-low transition of the SDA line at the start of a data transfer SCL indicates a start condition. All command devices must be preceded by a start condition. Stop Data Transfer A high transition of the SDA line from low to high on the SCL input indicates a stop condition. All command devices must obey the stop condition. Data is valid if the SDA line is stable during the high period of SCL on the line after the start condition occurs. Data on SDA can only change the line signal while SCL is low. There is one clock pulse per data bit.

Each data transfer is terminated by a START condition and by a STOP condition. The number of data bytes transferred between start and stop conditions is determined by the master and can continue indefinitely. However, the data overwritten to the device overflows into the first register after the first 8 bytes, then the second, and so on, in the first, first overwrite fashion. Acknowledgment When addressed, the receiving device needs to generate an acknowledgment after each byte is received. The master must generate additional clock pulses to match the acknowledge bit. The acknowledgment device must pull the SDA line low for the acknowledgment clock pulse while the master is high. Setup and hold times must be taken into account. The master must read (clock) from the slave by generating and acknowledging the bits on the last byte. In this case, the slave must hold the SDA line high to enable the master to generate a stop condition. I2C-bus operation All programmable registers can be accessed randomly or through this bidirectional 2-wire digital interface. The crystal oscillator does not have to run for communication to take place. The device accepts the following I2C bus commands: After the slave address generates a start condition, the bus master broadcasts a 7-bit slave address followed by an R/W bit. The address of the device is:

where X is controlled by the logic level of the ADDR pin. The optional ADDR bit allows four different FS7140 devices to exist on the same bus. Note that each device on the I2C bus must have a unique address to avoid possible bus conflicts. Random Register Write Procedure The random write operation allows the host to write directly to any register. To initiate the write process, R/W is logic-low at the seven-bit device address. This indicates to addressing slave devices that the slave device will be followed by a register address to confirm its device address. The registered address is the address pointer written to the slave. Following the slave acknowledgment allows the master to write the eight bits of data in the address register. The final device returns an acknowledgment and the host generates a stop condition. If a Stop or Repeated Start condition occurs during a register write, the transferred data is ignored.

Random Register Read Process The random read operation allows the host to directly read from any register. To perform a read process, the R/W bit is transmitted after the seven-bit address is logic low, during a register write process. This indicates that the register address will follow the addressing of the slave device after the slave device has confirmed its device address. This then register address is written to the slave address pointer. Generate duplicate start conditions under acknowledgment. Repeated START terminates the write process, but sets the slave's address pointer. The slave address is retransmitted, and the R/W bit is set to a logic high position, indicating that the slave reads data. The slave will confirm the device address and then send the octet. The master does not acknowledge the transfer but does generate a stop condition. Sequential Register Write Process Sequential write operations allow the host to write to each register in sequence. The register pointer is automatically incremented after each write. This process is more efficient than random registers if more than one register must be written. To initiate the write process, the R/W bit is transmitted a logic low after the seven-bit device address. This indicates to the addressed slave device that the slave device acknowledges its device address. The registered address is written in the slave address pointer. Upon receipt of the slave, the master can write 8 bytes of data into the address register before the register address pointer overflows back to the starting address. Acknowledgment by the device between each data byte must occur before sending the next data byte. Every time the device sends a compliment to the owner.

Register updates do not wait for a stop condition to occur. Therefore, the registers are updated at different times during sequential register writes. Sequential Register Read Program Sequential read operations allow the host to sequence from each register. The register pointer is automatically incremented by one after each read. This process is more efficient than random registers that must be read. To perform a read process, the R/W bit is transmitted logic low after the seven-bit address, such as a register write process. This represents the address slave device, followed by a register address device to confirm its device address. The register then writes the address into the slave's address pointer. Generate duplicate start conditions under acknowledgment. Repeated START terminates the write process, but sets the slave's address pointer. The slave address is retransmitted, and the R/W bit is set to a logic high position, indicating that the slave reads data. The slave will confirm the device address and then send all 8 data bytes starting from the initial address register. This if the initial register address is greater than zero. The master does not acknowledge the transfer after the last byte of data, but does generate a stop status.