feature

Dual-channel, 256 -bit resolution; 10 kΩ, 50 kΩ, and 100 kΩ nominal termination resistors maintenance of non-volatile memory wiper settings; predefined linear increment/decrement commands; predefined ±6db step logarithmic taper increments Decrement/Decrement commands; SPI compatible serial interface; wiper setting and EEMEM readback; 3 V to 5 V single supply operation; ±2.5 V dual supply operation; 14-byte general-purpose user EEMEM; Data retention period (TA=55°C).

application

Mechanical potentiometer replacement; instrumentation: gain and offset adjustment; programmable voltage-to-current conversion; programmable filters, delays, and time constants; programmable power supplies; low-resolution DAC replacement for sensor calibration.

General Instructions

The AD5232 device provides a nonvolatile dual-channel digitally controlled variable resistor (VR) with 256-bit resolution. The device features the same electronic adjustment as a mechanical potentiometer, with higher resolution, solid-state reliability, and superior low temperature coefficient performance. The multifunctional programming of the AD5232 is implemented through a microcontroller, allowing multiple modes of operation and adjustment.

In direct programming mode, the predetermined settings of the RDAC registers (RDAC1 and RDAC2) can be loaded directly from the microcontroller. Another important mode of operation allows the RDACx registers to be refreshed with settings previously stored in the corresponding EEMEM registers (EEMEM1 and EEMEM2). When changes are made to the RDACx registers to establish a new wiper position, the settings can be saved to the EEMEMx registers by performing an EEMEM save operation. Once the settings are saved in the EEMEMx registers, these values are automatically transferred to the RDACx registers to set the wiper position when the system is powered up. This action is enabled by an internal preset strobe switch. Preset strobes can also be accessed externally.

All internal register contents can be read through the serial data output (SDO). This includes the RDAC1 and RDAC2 registers, the corresponding non-volatile EEMEM1 and EEMEM2 registers, and 14 spare user EEMEM registers that can be used for constant storage.

The basic mode of adjustment is the increment and decrement command instructions that control the wiper position setting registers (RDACx). The internal wiper RDACx registers can move one step up or down the nominal resistance between Terminal A and Terminal B. This step adjustment linearly changes the wiper to the terminal B resistance (R) through one position segment of the device end-to-end resistance (R). For exponential/logarithmic changes in wiper settings, the left/right shift command commands adjust the level in ±6dB steps, which is useful for audio and light alarm applications.

The AD5232 is a thin, 16-lead TSSOP package. All parts are guaranteed to operate over the extended industrial temperature range (from -40°C to +85°C). An evaluation board, the EVAL-AD5232-10EBZ, is available.

theory of operation

The AD5232 digital potentiometer is designed to be a true variable resistor replacement for analog signals that are held at VSS

Scratchpad and EEMEM programming

The Notepad registers (RDACx registers) directly control the position of the digital potentiometer wiper. When the notepad register is loaded with all 0s, the wiper is connected to terminal B of the variable resistor. When the scratchpad register is loaded with the mid-scale code (1/2 of the full-scale position), the wiper is connected to the middle of the variable resistor. When Notepad is loaded with full scale code (all 1s), the wiper is connected to terminal A. Because the Notepad register is a standard logical register, there is no limit to the number of changes allowed. The EEMEMx registers have program erase/write cycle limitations described in the Flash/EEMEM Reliability section.

Basic operation

The basic mode of setting the variable resistor wiper position (by programming the notepad registers) is done by loading the serial data input register with command instruction 11, which includes the desired wiper position data. When the desired wiper position is found, the user loads the serial data input register with command instruction 2, which copies the desired wiper position data into the corresponding non-volatile EEMEMx register. After 25 ms, the wiper position is permanently stored in the corresponding non-volatile EEMEM position. Table 6 provides an application programming example listing the sequence of serial data input (SDI) words and the corresponding serial data output appearing at the serial data output (SDO) pins in hexadecimal format.

When the system is powered up, the scratchpad registers are refreshed with the last value saved in the EEMEMx registers. The factory preset EEMEM value is midscale. The wiper register can be refreshed with the current contents of the non-volatile EEMEMx register under hardware control by pulsing the PR pin.

The application programming example shown in Table 6 lists two digital potentiometers set to independent data values. The wiper position is then saved in the corresponding nonvolatile EEMEMx registers.

Note that when the wipers go to logic 0, the PR pulse first sets the wipers to midscale. Then, on a positive transition to logic high, it reloads the DAC wiper register with the contents of EEMEMx. Many additional advanced programming commands are available to simplify the variable resistor adjustment process.

For example, the wiper position can be changed step by step using software-controlled increment/decrement command instructions. The wiper position can also be changed by 6 dB by using the left/right shift command. After an increment, decrement, or shift instruction is loaded into the shift register, subsequent CS strobes repeat the instruction. This is useful for button control applications (see the Advanced Control Modes section). The SDO pin can be used for daisy chaining and readout of internal register contents. The serial input data register uses a 16-bit instruction/address/data word.

EEMEM protection

The write protect (WP) pin disables any changes to the scratchpad register contents regardless of software commands, except that the EEMEM settings can be refreshed using the instruction command 8 and PR. Therefore, the WP pin provides hardware EEMEM protection. Execute the NOP command (command instruction 0) before returning WP to logic high.

Digital input/output configuration

All digital inputs are ESD protected and the high input impedance can be driven directly from most digital sources. The PR and WP pins are active at logic low and must be biased towards VDD if not used. There are no internal pull-up resistors on any digital input pins.

The SDO and RDY pins are open-drain and are digital outputs when pull-up resistors are required, but only when these functions are used. Resistor values in the 1 kΩ to 10 kΩ range optimize the power and switching speed trade-off.

serial data interface

The AD5232 contains a 4-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK) and uses a 16-bit serial data word that is loaded MSB first. The format of the SPI compatible word is shown in Table 7. The Chip Select (CS) pin must be held low until a complete data word is loaded into the SDI pin. When CS returns high, the serial data word is decoded according to the instructions in Table 8. The command bit (Cx) controls the operation of the digital potentiometer. The address bits (Ax) determine which register is activated. The data bits (Dx) are the values loaded into the decode register. Table 9 provides an address map of EEMEM locations. The last command instruction executed before there is no programming activity shall be the no operation (NOP) command instruction (command instruction 0). This instruction places the internal logic circuits in a state of minimum power consumption.

The AD5232 has an internal counter that counts multiples of 16 bits (per frame) to ensure proper operation. For example, the AD5232 can handle 16-bit or 32-bit words, but not 15-bit or 17-bit words. To prevent mis-locking of data (for example, due to noise), when CS goes high, the counter will reset if the count is not a multiple of 4, but if the count is a multiple of 4, the data remains in the register. Additionally, the AD5232 has a subtle feature that if CS is pulsed without CLK and SDI, the part repeats the previous command (except during power-up). Therefore, care must be taken to ensure that there is no excessive noise in the CLK or CS lines, which could change the number of significant bits.

The equivalent serial data input and output logic is shown in Figure 33. When CS is logic high, open SDO is disabled. The SPI interface can be used in two slave modes: CPHA=1, CPOL=1; CPHA=0, CPOL=0. CPHA and CPOL refer to the control bits that indicate SPI timing in the following microprocessors and MicroConverter® devices: ADuC812 and ADuC824, M68HC11 and MC68HC16R1/916R1.

The protection of digital inputs is shown in Figures 34 and 35.

Daisy Chain Operation

The SDO pin serves two purposes: it can read the wiper settings and the contents of the EEMEM using Command Command 9 and Command Command 10 (see Table 8), or it can be used to concatenate multiple devices. The rest of the commands are valid for tandem multiple devices in simultaneous operation. Daisy chaining minimizes the number of port pins required for the control IC (see Figure 36). The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor if this feature is used. As shown in Figure 36, the user must bind the SDO pin of one package to the SDI pin of the next package. The user may need to increase the clock period because pull-up resistors and capacitive loading at the SDO to SDI interface may require additional time delay between subsequent packets. If two AD5232s are daisy-chained, 32 bits of data are required. The first 16 bits go into U2, and the last 16 bits go into U1 in the same format. The 16 bits are formatted to contain a 4-bit instruction, followed by a 4-bit address, followed by eight bits of data. The CS pin should be held low until all 32 bits are locked in their respective serial registers. Then pull the CS pin high to complete the operation.

The command bit is identified as Cx, the address bit is identified as Ax, and the data bit is identified as Dx. The command instruction codes are shown in Table 8. The SDO output shifts the last eight bits of data out of the serial register for daisy-chaining, with the following exception: After command instruction 9 or command instruction 10, the selected internal register data appears in data byte 0. The command commands following command command 9 and command command 10 must be a complete 16-bit data word that completely punches the contents of the serial register. The RDACx register is a volatile scratchpad register that is refreshed from the corresponding nonvolatile EEMEMx register at power-up. The increment, decrement, and shift command instructions ignore the contents of data byte 0 in the shift register. When the CS strobe returns to logic high, the operations shown in Table 8 are performed. Execution of NOP instructions minimizes power consumption.

Advanced Control Mode

The AD5232 digital potentiometer contains a set of user-programmable functions to address a wide range of applications for these general purpose adjustment devices. Key programming features include:

(1) Independent programmable read and write for all registers

(2) Simultaneously refresh all RDAC wiper registers from the corresponding internal EEMEM registers

(3) Increment and decrement instructions for each RDAC wiper register

(4) Left and right shift bits of all RDAC wiper registers to achieve 6 dB level change

(5), non-volatilely store the current scratchpad RDACx register value into the corresponding EEMEMx register

(6), 14 additional bytes of user-addressable, electrically erasable memory

Increment and decrement commands

The Increment and Decrement Commands (Command 14, Command 15, Command 6, and Command 7) are useful for basic servo tuning applications. These commands simplify microcontroller software coding by eliminating the need to perform a readback of the current wiper position and then use the microcontroller adder to add 1 to the register contents. The microcontroller sends an incremental command command (command command 14) to the digital potentiometer, and the digital potentiometer automatically moves the wiper to the next resistance segment position. The main incremental command command (command command 15) moves all potentiometer wipers one position from the current position to the next resistance segment position. The movement direction refers to terminal B. Therefore, each command instruction 15 moves the wiper tap position away from the terminal B position.

Logarithmic taper mode adjustment

The programming instructions allow control of the decrease and increase of the wiper position by a single potentiometer or a combined potentiometer arrangement, where both wiper positions are changed simultaneously. These settings are activated by the 6db decrement and 6db increment commands (command 4 and 5, command 12 and 13 respectively). For example, starting with the wiper connected to terminal B, nine incremental instructions (command instruction 12) are executed to move the wiper from the R (terminal B) position to 100% of the AD5232 8-bit potentiometer RBA position. The 6db increment instruction doubles the value of the RDACx register contents each time the command is executed. When the wiper position is greater than the mid-scale, the last 6db incremental command command causes the wiper to turn to the full-scale 255 code position. Any additional 6db instructions will not change the full-scale wiper position (RDACx register code = 255).

Figure 37 shows the operation of the 6db shift function on a single RDACx register data bit for the 8-bit AD5232 example. Each row of the following table represents a successive shift operation. Note that the left shift 12 and left shift 13 command instructions have been modified so that if the data in the RDACx register is equal to 0 and left shifted, it is set to code 1.

In addition, the left shift command has been modified so that if the data in the RDAC register is greater than or equal to midscale and shifted left, the data is set to full scale. This makes the left shift function as close as possible to the ideal logarithm.

The Right Shift 4 and Right Shift 5 commands are ideal only when the LSB is 0 (i.e. ideal logarithm, no errors). If the LSB is 1, the right-shift function generates a linear half-LSB error that translates only to a code-dependent logarithmic error for odd codes, as shown in Figure 38. The figure shows errors for odd-numbered codes.

For each right shift 4 and right shift 5 command execution, the actual agreement of the logarithmic curve between the data content in the RDACx register and the wiper position contains only errors for odd codes. Even numbers are ideal, except for zero shifts to the right or left shifts greater than half a scale.

Figure 38 is a plot of logarithmic error, ie 20 x log10 (error/code). For example, code 3 Log_Error=20×log10(0.5/3)=-15.56 dB, which is the worst case. The logarithmic error map is more pronounced at lower encodings.

Use additional internal non-volatile EEMEM

The AD5232 contains an additional internal user memory register (EEMEM) for holding constants and other 8-bit data. Table 9 provides the address map of the internal nonvolatile storage registers shown in the functional block diagram as bytes of EEMEM1, EEMEM2, and user EEMEM.

Note the following about the EEMEM function:

(1) When power is turned on or command instruction 1 and command instruction 8 are executed, the RDAC data stored in the EEMEM location is transferred to the corresponding RDACx register.

(2), USERx refers to the internal non-volatile EEMEM register, which can be used to store and retrieve constants using command instruction 3 and command instruction 9 respectively.

(3), EEMEM position is each byte (8 bits).

(4) Execute the command instruction 1 to make the device in the read mode power consumption state. When the last command instruction 1 is executed, the user should execute a NOP (command instruction 0) to return the device to a low power idle state.

Terminal voltage operating range

The positive VDD and negative VSS supplies of the digital potentiometer define the boundary conditions for proper 3-terminal programmable resistor operation. Signals above VDD or VSS appearing on Terminal A, Terminal B, and Wiper Terminal W are clamped by forward-biased diodes (see Figure 39). The ground pin of the AD5232 device is primarily used as a digital ground reference that needs to be connected to the common ground of the PCB. The digital input logic signals to the AD5242 must be referenced to the ground (GND) pin of the device and meet the minimum input logic high level and the maximum input logic low level defined in the Specifications section. An internal level-shift circuit between the digital interface and the wiper switch control ensures that the common-mode voltage range of the three terminals (terminal A, terminal B, and wiper terminal W) extends from V to VDD.

Detailed potentiometer operation

The actual structure of the RDACx is designed to simulate the performance of a mechanical potentiometer. The RDACx consists of resistor segments connected in multiple strings, with a set of analog switches acting as wiper connections to multiple points along the resistor array. The number of points is equal to the resolution of the device. For example, the AD5232 has 256 connection points and can provide better than 0.5% settable resolution. Figure 40 provides an equivalent diagram of the connections between the three terminals that make up a channel of RDACx. The SW and SWB switches are always on, while only one of the SW(0) to SW(2–1) switches are on at a time, depending on the resistive step decoded from the data bits. The contribution resistance of RW must be considered in the output resistance.

Variable Resistor Programming

Rheostat operation

The nominal resistance values of RDACx between Terminal A and Terminal B are 10 kΩ, 50 kΩ, and 100 kΩ, respectively. The last digit of the part number determines the nominal resistance value, eg 10 kΩ=10; 100 kΩ=100. The nominal resistance (R) of the AD5232 VR has 256 contact points, which are contacted by the wiper terminals W and B. Decodes the 8-bit data word in the RDACx latches to select one of 256 possible settings.

The general transfer equation to determine the digitally programmed output resistance between Wx and Bx is:

where: D is the decimal equivalent of the data contained in the RDACx register. RAB is the nominal resistance between Terminal A and Terminal B. RW is the wiper resistance.

Table 12 lists the RDACx latch codes for displaying the 8-bit 10 kΩ potentiometer.

NOTE: Under zero size conditions, a finite fiber resistance of 50\31; is now the concern should be to limit the current between WX and BX. In this state, a maximum continuous value of 2 marks is allowed to avoid degradation or possible destruction of internal switch metallization. Intermittent current operation to Mach 20 is allowed.

Like the AD5232 mechanical potentiometer that RDACX replaces, the part is completely symmetrical. Resistor Wiper Terminal W and Terminal A also produce a digitally controlled resistor. Figure 41 shows the programmability of the symmetrical various terminal connections.

When using these terminals, terminal B should be tied to the wiper. Setting the resistance value of R starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general transfer equation for this operation is:

where: D is the decimal equivalent of the data contained in the RDAC register. RAB is the nominal resistance between Terminal A and Terminal B. RW is the wiper resistance.

Table 13 lists the RDACx latch codes for displaying the 8-bit 10 kΩ potentiometer.

The multi-channel AD5232 has a typical internal channel-to-channel R matching distribution of ±0.2%. Equipment-to-equipment matching is process batch dependent and exhibits a -40% to +20% variation. The variation of R with temperature has a temperature coefficient of 600 ppm/°C.

Program the Potentiometer Divider

Voltage output operation

Digital potentiometers tend to generate an output voltage proportional to the input voltage applied to a given terminal. For example, connecting terminal A to 5 V and terminal B to GND, the resulting output voltage at the wiper can be anywhere between 0 V and 5 V. The LSB of each voltage is equal to the voltage applied between Terminal A to Terminal B divided by the 2 position resolution of the potentiometer divider. For any given input voltage applied across terminals A to B, the general equation defining the output voltage with respect to ground is:

where RWB(D) can be obtained from Equation 1 and RWA(D) can be obtained from Equation 2. Operation of digital potentiometers in voltage divider mode results in more accurate operation over temperature. Here is the ratio of the output voltage depending on the internal resistance, not the absolute value; therefore, the drift increases to 15 ppm/°C. There is no voltage polarity restriction between terminal A, terminal B and wiper terminal W as long as the terminal voltage (VTERM) remains at VSS

Dual Power Operation

The AD5232 can be operated with dual power supplies, enabling control of a ground-referenced ac signal (see Figure 42 for typical circuit connections).

Internal parasitic capacitance and external capacitive loading control the AC characteristics of the RDAC. When configured as a potentiometer divider, the -3 dB bandwidth of the AD5232BRU10 (10 kΩ resistor) measures 500 kHz at half scale. Figure 14 provides the large-signal BODE plot characteristics for three resistor versions: 10 kΩ, 50 kΩ, and 100 kΩ (see Figure 43 for a parasitic simulation model of the RDAC circuit).

The following code provides a macromodel netlist for a 10 kΩ RDAC:

Application Programming Example

The command sequence examples shown in Table 14 through Table 18 have been developed to illustrate a typical sequence of events for various characteristics of the AD5232 nonvolatile digital potentiometer. Table 14 illustrates setting the two digital potentiometers to separate data values.

Table 15 illustrates active trimming of a potentiometer and then saving to non-volatile memory (PCB calibration).

Table 16 shows changing the circuit gain in 6dB steps using a left shift once.

Table 17 shows the procedure for storing additional data in non-volatile memory.

Table 18 shows the process for reading data from various memory locations.

Device Customer Startup Sequence for PCB Calibration Unit with Protection Settings:

1. For PCB setting, connect WP to GND to prevent the PCB wiper setting position from changing.

2. Set the power supply V and V relative to GND. Due Diligence SS

3. As an optional step, strobing the PR pin ensures that in an unpredictable power sequence environment, the wiper register and EEMEM contents are fully power-up preset.

FLASH/EEMEM reliability

The Flash/EE memory array on the AD5232 is fully compliant with two key Flash/EE memory characteristics: Flash/EE memory cycle endurance and Flash/EE memory data retention.

Persistence quantifies the ability of Flash/EE memory to cycle through many program, read and erase cycles. In fact, an endurance cycle consists of four separate consecutive events. These events are defined as follows:

1. Initial page erase sequence

2. Read/Verify Sequence

3. Byte program sequence

4. Second read/verify sequence

During reliability qualification, the Flash/EE memory cycles from 0x00 to 0xFF until the first fault is recorded, which represents the endurance limit of the on-chip Flash/EE memory.

As shown in the Specifications section, the AD5232 Flash/EE memory has been qualified for endurance over the industrial temperature range of -40°C to +85°C per JEDEC Std.22, Method A117. The results allow for minimum endurance values to be specified over the power supply and temperature range of 100,000 cycles, with a typical cycle life of 700,000 cycles at 25°C.

Preserves the ability of quantized Flash/EE memory to retain its programmed data over time. Likewise, the AD5232 is rated according to the official JEDEC retention life specification (A117) at a specified junction temperature of T=55°C. As part of this rating procedure, the Flash/EE memory was cycled to its specified durability limit, as previously described, before data retention was characterized. This means that each time the Flash/EE memory is reprogrammed, the Flash/EE memory is guaranteed to retain its data for its specified full retention life. It should also be noted that the retention lifetime decreases with T according to the activation energy of 0.6 eV, as shown in Figure 44.

Evaluation Committee

Analog Devices, Inc. offers a user-friendly evaluation kit, the EVAL-AD5232-SDZ, which can be controlled by a personal computer through the printer port. Drivers are self-contained; no programming language or skills are required.

Dimensions