Feature

Single power supply 3.3V operation

Built -in sampling and maintenance

Direct 3 -line interface of most MPU serial port

All MPUs Parallel port

30kHz maximum throughput

Main specifications

minimum guarantee power supply voltage: 2.7V

Resolution: 12 digits

Quick conversion time: up to 24 μs ultra -temperature.

Low power supply current: 1.0ma

Application

Battery power supply instrument

Data recorder

Data collection module

Explanation

LTC #174; 1287 is a 3V data collection component containing a serial I/O approaching the A/D converter one by one. The equipment specifications guarantee that the power supply voltage is 2.7V, and the LTCMOSTM switching capacitor technology is used to achieve a 12 -bit single A/D conversion. Differential input has a sample on the film and keeps (+) input. The serial I/O design is allowed to pass three wires for most MPU serial ports and all MPU parallel ports without external devices to most MPU serial ports. Low -voltage operation capabilities and low -power consumption of this device make it an ideal choice for battery applications. Considering the ease of use, the small packaging size and minimum number of mutual connections can be used for remote sensing applications for I/O. LTC1287 can be used.

For over -pressure protection, the input current is limited to 15mA through the 1N4148 diode to fix the input end to VCC and GND. Elected or other channels (VIN LT; GND or VIN GT; VCC). See the application of overvoltage protection in the application information.

Major value (Note 1 and 2)

Power supply voltage 12 volts

Voltage

Simulation and reference input -0.3v to VCC+0.3 V

Digital input -0.3 volts to 12 volts

Digital output -0.3v to VCC+0.3V

Power consumption 500 MW

Work temperature Range 0 ° C to 70 ° C

Storage temperature range -65 ° C to 150 ° C

Lead temperature (welding, 10 seconds) 300 degrees Celsius

Co -converter The characteristics of the multi -way reuse

indicate the specification

suitable for the entire operating temperature range, otherwise the specification is TA u003d 25 ° C. (Note 3)

Digital DC Electric Router

indicates the specification

It is suitable for the entire working temperature range, otherwise the specifications are TA u003d 25 ° C. (Note 3)

Note 1: The absolute maximum rated value means that the value device that exceeds life may be damaged.

Note 2: All voltage values u200bu200bare related to grounding (unless there are other regulations).

Note 3: VCC u003d 3V, VREF u003d 2.5V, CLK u003d 500KHz, unless there are other regulations.

Note 4: A LSB is equal to VREF division 4096. For example, when VREF u003d 2.5V, 1LSB u003d 2.5V/4096 u003d 0.61MV.

Note 5: The non -linear error definition of integration is defined as a code deviation starting curve from a straight line passing through the actual endpoint of transmission. Display deviation from the center of quantitative belt.

Note 6: Recommended operation conditions. LTC1287B/LTC1287C

Note 7: The diode on the two films is connected to each analog input analog voltage to transmit a diode below GND or a diode drops higher than VCC. When testing at the low VCC level (such as high level analog level), you must be careful to input the diode input, especially when the voltage increases temperature, and causes input errors close to the full standard. This specification allows the positive bias of Ren Pitchus to 50mV. This means that as long as the input voltage does not exceed 50mV of the power supply voltage, the output code will be correct.

Note 8: The channel leakage current is measured after the channel is selected.

Note 9: The increase in leakage currents at high temperatures causes S/H to reduce speed. Therefore, it is recommended that at 85 ° C at 85 ° C, FCLK ≥ 30kHzfCLK ≥ 3KHz, 25 ° C.

Typical performance features

1. Maximum CLK frequency indicates that the CLK frequency at 0.1LSB first detects any code first. Error offset from 500kHz conversion.

2. When the CLK frequency decreases from 1MHz, the minimum CLK frequency ( #8710; error ≤0.1LSB) indicates any code conversion that first detects its 500kHz value.

3. The maximum RFILTER represents the filter resistance value when 0.1LSB is first detected.

pin function

CS (pin 1): chip select input. The logic of this input enables LTC1287.

+in, --in (pin 23): Simulation input. These inputs must have no noise relative to GND.

GND (pin 4): The simulation ground GND should be directly connected to the simulation ground plane.

VREF (pin 5): Reference input. Reference to the range of A/D converters must maintain noise relative to GND.

DOUT (pin 6): digital data output. The A/D conversion results will be moved out of this output.

CLK (pin 7): shift clock. This clock synchronizes serial data transmission.

VCC (pin 8): Positive power supply. This batch of goods must be available for free to eliminate noise and ripple ground plane by directly bypass to the simulation circuit.

LTC1287 is a data acquisition component containing the following function blocks:

1.12 digits approach the capacitance A/D one by one one by one. Converter

2. Simulates multi -way reused

3. Sample and keep (s/h)

4. Synchronous, semi -dual -work serial interface [123 123 ]

5. Control and time logic

Digital considerations

Serial interface

LTC1287 and microprocessors and other external circuits through synchronization, half -dual -workers, and other external circuits, and other external circuits, which are synchronized and half -workers. Three -line serial interface (see the order of operation). This clock (CLK) transmits data transmission with each bit at the edge of the clock. LTC1287 does not need to configure input characters, and there is no DIN needle. It is permanently configured to have a single differential input and run in a single pole mode. A falling CS starts data transmission. The first CLK pulse enables DOUT. After an empty position, the A/D conversion result outputs the DOUT of the first sequence of the MSB after the first sequence of the MSB sequence. DOUT data with a half -work serial interface is from the current conversion. This provides a simple interface to MSB or LSB's first serial port. Bring CS HIGH reset LTC1287 for the next data exchange.

Logic level

The logical level standard of this supply range is not defined. Existing standards are not generally accepted. The trigger point LTC1287 on the logical input is 0.28 × VCC. This makes logic input compatible HC type levels and processors

The specifications are 3.3V. The output DOUT is also with the above standards. The following summary is as follows.

voh (empty) vcc – 0.1V

Volume (empty) 0.1V

voh 0.9 × VCC

[12] [12]3] Volume 0.1 × VCC

VIH 0.7 × VCC

VIL 0.2 × VCC

LTC1287 can be driven with 5V logic, even if the VCC voltage is 3.3V. This is because a unique input protection device can be found on the LTC1287.

Micro -processor interface

LTC1287 can be connected to the most popular microprocessor (MPU) synchronous serial format. If the microprocessor of the serial interface is not used, the MPU's three parallel -end portal can be programmed to form a serial link of the LTC1287. Many popular MPUs can be powered by 3V. The example MC68HC11 is a serial format MPU

(SPI). Similarly, a parallel microprocessor architecture with 8051 type can also work under this voltage. The code of these processors remain unchanged in the LTC1292 data table.

Sharing serial interface

LTC1287 can share the same dual -line serial interface other peripheral components or other LTC1287 (Figure 2). In this case, the CS signal determines that the LTC1287 is processing by the microprocessor

Simulation considerations

ground

LTC1287 should be as good Simulate ground flooring and single -point grounding technology. Do not use wire packaging technology to test and evaluate the equipment. To get the best performance, use the PC board. This grounding needle (pin 4) should be directly connected to the plane with the minimum lead length (low section socket). Inserting 7 (VCC) should bypass the ground floor 22 μF (minimum value) 钽, and the lead is as short as possible as possible. The 0.1 μF ceramic disc should also be handed over to the VCC as much as possible as possible as possible as possible as possible as possible as possible. Figure 3 shows an ideal example of the ground plane design of the LTC1287 double panel. Of course, so many ground planes are not always possible, but users should work hard to approach this ideal possibility.

Wing by

In order to achieve good performance, VCC must have no noise and ripples. Any change in the VCC voltage may cause noise in errors or output code within the conversion cycle. VCC noise and ripples can keep the VCC pins directly bypass to the short -drawing of the simulation plane with at least 22 μF 钽 capacitors. Device from VCC power supply should also be maintained at a minimum output impedance of VCC power supply

For example, from the voltage regulator (such as LT1117). For high -frequency bypass, 0.1 μF ceramic disk is recommended to use at the same time as 22 μFEssence The clues should remain at the minimum. The use of the battery as the LTC1287 will help reduce the need for bypass power VCC pins. The battery can fully bypass the power to attract the feet by only 10 μF near the device. Figure 4 shows the impact of bad VCC bypass. Figure 5 shows the regulation of the LT1117 low -voltage difference with a 22μF bypass power container. The noise and ripples are kept about 0.5mv. Figure 6 shows a lithium battery with a 10μF bypass power container in response. This noise and ripples are controlled below 0.5mV.

Simulation input

Because of the technology used by the capacitor to re -assign A/D conversion, the simulation input of LTC1287

[

[

[

123]

The peak input current input current of the capacitor switch. These current spikes will be solved quickly and will not cause problems. If the ambassador uses the source resistance, or if the operational amplifier is slowly stable and stable to the input, pay attention to ensure that the transition from the transition caused by the current peak is completely stable.

Source resistance

The analog input of LTC1287 looks like 100pf capacitors (CIN) and 1.5K resistors (RON). This RON value is suitable for VCC u003d 2.7V, and the power supply voltage is weakened. For example, in VCC u003d 2.7V and V-u003d-2.7V, RON becomes 500 #8486; Cin enters once in each conversion cycle in (+) and ( -). Large external source resistance and capacitance will slow down. It is important that the entire RC time constant is short enough to allow the simulation input to be completely stable within the allowable time.

""+"" input Set the input capacitor in the sampling phase (TSMPL, see Figure 8A, 8B, 8C). This sampling cycle can be shortened to TWHCS+0.5 CLK cycle or as long as TWHCS+1.5 CLK cycle. This change depends on the relative position of CS to CLK. The voltage on the ""+"" input must be completely stable in the sample period. To minimize RSOURCE+and C1 to shorten the settlement time. If the input source ""+"" ATIO application must use the resistance, it can increase the slowing frequency of the sampling time. The minimum possible sampling time is 6.0 μs, rsource+ lt; 4.0k and C1 LT; 20PF will provide sufficient settlement time. "" -"" Input is set at the end of the sampling phase, the input capacitor switches input "" -"" and starts the conversion (see Figure 8A, 8B, and 8C). During the conversion process, the ""+"" input voltage is

effectively ""holding"" the sample, which will not affect the conversion results Essence The key is "" -"" input voltage during the first CLK, noThere is noise and completely stabilize the conversion cycle. To minimize resources-command and control will shorten the settlement time. If the input source resistance is too large, it must be used by using the slow CLK frequency. When the maximum clock frequency is 500kHz, rsource - lt; 200 #8486; and C2 LT; 20pf will provide sufficient solutions.

Enter the operational amplifier

When the operation amplifier drives analog input, it is important to stabilize the operation amplifier within the allowable time (see Figure 8A, 8B, and 8C). Enter ""+"" and "" -"" sampling time again to extend to the computing amplifier with a slower adaptation as mentioned above. The low -voltage application of the single power supply can perform the LT1797 and LT1677 even at the minimum settlement window of 6 μs (""+"" input) and 2 μs ("" -"" input) in the maximum clock frequency (CLK u003d 500KHz). Figure 9 and 10 show an example of appropriate and poorly computing amplifiers. This LT1077, LT1078 or LT1079 can be used to reduce power consumption. Putting an RC network operation amplifier on the output end will improve the settlement response and reduce broadband noise.

RC input filter

You can use RC network filtering input as shown in Figure 11. For larger CF values u200bu200b(for example, 1 μF), the capacitor input switch current is average to a DC current in one network. The filter should use small resistors and large capacitors to prevent DC voltage from falling over the resistor. The size of the DC current is about IDC u003d 100pf × VIN/TCYC, which is roughly proportional to Vin. Run at the minimum cycle of 33 μs. When entering Vin u003d 2.5V, the current is equal to 7.6μA8 #8486; it will cause 0.1LSB to fully marked error. If a large filter must use resistance, you can reduce the characteristics of the maximum filter resistance and cycle characteristic curve time of the cycle time shown by the typical performance by increasing the resistance.

Input leakage current

Input leakage current will also be too much resistance. For example, the leakage specification source resistance of 1 μA (85 ° C) that flows through A can cause 1MV to drop or 1.6LSB, VREF u003d 2.5V. This error will be reduced at a low temperature, because the leak is reduced rapidly (see typical performance characteristic curve input channel leakage current and temperature).

Sample reservation

Single -end input

LTC1287 provides a built -in sampling and maintenance (s amp; amp; h) single channel+in input function of the collection signal ends at the end Mode (pin ground). Sampling and saving signals that allow LTC1287 to change rapidly (see s amp; amp; h typical performance characteristic curve collection time and source resistance).The input voltage is sampled in TSMPL time, as shown in Figure 8. This sampling interval starts from the rising edge of the CS and continues until the decrease of the CLK. At this decrease edge, S AMP; AMP; H enters the cargo cabin mode and the conversion begins.

Differential input

with differential inputs, A/D no longer converts a single but converts the difference between two voltages. Sample the voltage on the+IN pin and keep changing quickly. The voltage on the input pin must be kept constant without noise and ripple conversion time. Otherwise, the differential operation will not be completed accurately. The conversion time is a 12CLK cycle. Therefore, the interval here may cause conversion errors. The error of the voltage of the sine curve input end is:

where f (–IN) is the frequency of the input voltage, VPEAK is its peak amplitude, and FCLK is Clack. Usually, errors are not important. For the signal of the 60Hz input terminal to generate a 0.25LSB error (150 μV), when the converter runs at CLK u003d 500KHz, its peak must be 16MV. Re -arrange the above -mentioned content equation, the maximum script signal digitization to the formula of a given accuracy is as follows:

For 0.25LSB error (150 μV), the maximum input sine curve 2.5V peak amplitude can be digitized to 0.4Hz.

Reference input

LTC1287 Reference Input -end voltage determines the voltage range of the A/D converter. Because of the switch capacitor conversion technology, refer to the input input with a transient capacitor switch current (see Figure 12). The peak of the capacitance current in the conversion (each CLK cycle) will be generated by A/D on the reference pins, which will quickly stabilize and will not cause problems. If the slow settlement circuit is used to drive reference input, it is important to ensure that the transients are tested due to the conversion of these current peaks.

Figure 13 and 14 show the proper and settlement difference. Using the slower CLK will allow more time to reference settlement. Even at the rate of 500kHz at the highest clock, most references and operational amplifiers can sink it within 2 μs. For example, the LT1790 with a 4.7μF bypass container will be sufficiently settled.

Simplified reference operations

By reducing the input range of the converter, the effective resolution of the LTC1287 can be improved. LTC1287 shows a good linear reference voltage within the following range (the typical performance characteristic curve voltage of linear and benchmark changes). When running at low speed, be careful of the reduced LSB steps and the higher accuracy required converter. Shooting and noise are the factors that must be considered when running at a low VREF value. Reduce the offset of VREF LTC1287.Code reference voltage. The displacement (usually a fixed voltage) becomes a large part of LSB reduced the lowest effective position. The typical performance characteristic curve voltage that does not adjust the offset error and the reference value shows the voltage of VOS typical values u200bu200bin the relationship between the offset and reference value in LSB. For example, 0.1MV, that is, 0.2LSB, the reference voltage is 2.5V0.4LSB, and the reference value is 1.25. If this offset is unacceptable, the receiving system can be used for digital correction or input to the displacement LTC1287.

Reduce the noise of VREF

The total input reference noise of the LTC1287 can be the use of ground plane, good bypass, good layout technology, and minimizing reference input noise. This noise is insignificant under 2.5V reference input, but it has become a larger part of LSB as a decrease in LSB. Typical performance characteristic noise errors and reference voltage relationship curves show the LSB contribution of 200 μV noise. When running at 2.5V reference voltage, 200 μV noise is only 0.32LSB in the peak. Here is the LTC1287 noise that rarely causes uncertain code for output. For references, noise may become an important part of LSB and lead to a jitter output code output code. For example, 1.25 volt reference, the 200μV noise peak is 0.64LSB. This will reduce the range of input voltage with 0.64LSB to obtain a stable output code. The average reading may now be required. These noise data are collected in a very clean test fixture. Any settings caused by settings (noise or ripples or VIN on VREF) increase internal noise. The lower the reference voltage, the higher the noise setting.

Overvoltage protection

The analog input signal to LTC1287 exceeds the positive power supply or lower than the ground will reduce the accuracy of A/D and may cause damage equipment. For example, if the signal is applied to analog input for LTC1287 before power -on. Another example is to input different supply sources of supply, not LTC1287. These conditions should be performed through an appropriate supply order or use of the external circuit sources of preventing restrictions. There are two ways to protect input. In Figure 15, the diode clips from the VCC and GND input terminals are used. The second method is to simulate the input current limit in series. The current of each channel is 15mA. Enter the+receive 1K resistance value, but when the —in input cannot be at the maximum value, it accepts more than 200 #8486; the clock frequency is 500kHz. If the clock of the LTC1287 is in the maximum clock frequency and 200 #8486; it is not enough current to limit the input source and then the clamp diode is recommended (Figure 16 and 17). The reason for the resistance value is that the input of the resistance value of the MSB bit test is affected by the resistance value placed at —In (see the frequency and source of the frequency and source of the maximum CLK performance characteristic curve of simulation input and typical maximum CLK performance characteristicsresistance).If VCC and VREF are not connected together, then VCC should be opened first, and then open VREF.If this sequence cannot be met, it is recommended to connect the diode from VREF to VCC (see Figure 18).Because the unique input protection structure is used for digital input pins, the signal levels on these pins can exceed the device VCC without damaging the device.