feature

20 microseconds maximum conversion time; single-supply +5V operation; 12-bit ADS7812 -compatible pinout; easy-to-use serial interface; 16-pin 0.3" plastic dipping and SOIC; ±2.0LSB max; Use internal or external.

refer to

Multiple input ranges; 35mW maximum power consumption; no missing codes; 50 microwatts power-down mode.

application

Medical equipment; data acquisition system; robotics; industrial control; test equipment; digital signal processing; digital signal processor servo control.

illustrate

The ADS7813 is a low power single +5V supply, 16-bit sampling analog-to-digital converter. It contains a complete 16-bit capacitive SAR A/D sample/hold, clock, reference and serial data interface. The converter can be configured for a variety of input ranges including ± 10V , ±5V, 0V to 10V, and 0.5V to 4.5V. A high impedance 0.3V to 2.8V input range is also available (input impedance >10MΩ). For most input ranges, the input voltage can swing to +16.5V or –16.5V without damaging the converter. A flexible SPI-compatible serial interface allows data to be synchronized to an internal or external clock.

The ADS7813 is specified for a 40kHz sampling rate over the -40°C to +85°C temperature range. It is available in a 16-pin 0.3" plastic dip or 16-lead SOIC package.

Basic operation

Internal data CLK

Figure 1a shows the basic circuit for operating the ADS7813 over a ±10V input range. To start a conversion and serially transfer the results of previous conversions, a falling edge must be supplied to the CONV input. BUSY will go low to indicate that a conversion has started and will remain low until the conversion is complete. During conversions, the results of previous conversions are transferred through the data, and DATACLK provides the synchronous clock for the serial data. The data format is 16 bits, two's complement, MSB first. Each data bit is valid on both the rising and falling edges of DATACLK.

BUSY is low during the entire serial transmission and can be used as a frame synchronization signal.

External data CLK

Figure 1b shows the basic circuit for operating the ADS7813 over a ±10V input range. To start a conversion, a falling edge must be supplied to the CONV input. BUSY will go low to indicate that a conversion has started and will remain low until the conversion is complete. Just before the busy rise at the end of the conversion, the internal working register holding the conversion result will be transferred to the internal shift register.

The internal shift register is clocked by the DATACLK input. The recommended way to read the conversion result is to provide the serial clock after the conversion is complete. See "External Data CLK" under the "Read Data" section of this data sheet for details.

start conversion

If a conversion is not currently in progress, the CONV input puts sample and hold in hold mode and a conversion begins, as shown in Figure 2, with the timing shown in Table II. The CONV input is ignored during conversion. Initiate transitions do not depend on the state of the CS. Conversion is possible every 25 seconds (40kHz maximum conversion rate). There is no minimum conversion rate.

Even if the CONV input is ignored during the conversion, the input should remain static during the conversion. Conversions on this digital input can easily couple to the sensitive analog parts of the converter, adversely affecting the conversion results (see the "Sensitivity to External Digital Signals" section of this datasheet for more information).

Ideally, the CONV input should go low and remain low throughout the conversion. It should return to its highs sometime after a busy day. Also, it should be high for the minimum time period given by t5 before the next conversion starts. This will ensure that the digital conversion CONV input will not affect the signal acquired for the next conversion.

An acceptable alternative is to return CONV input HIGH as soon as the conversion starts. For example, a 100ns wide negative going pulse will produce a good CONV input signal. It is strongly recommended that the CONV input should remain static (high or low) from time t2 after the start of conversion until BUSY rises. During this period, the converter is more sensitive to external noise.

read data

The digital outputs of the ADS7813 are in two's complement (BTC) format. Table 3 shows the relationship between the digital output word and the analog input voltage under ideal conditions.

Figure 3 shows the relationship between the various digital inputs, digital outputs, and internal logic of the ADS7813. Figure 4 shows when the internal shift register of the ADS7813 is updated and how this relates to a single conversion cycle. Together, these two numbers point to a very important aspect of the ADS7813: the conversion result is not available until the conversion is complete. Figure 4. Timing of shift register updates. The following sections discuss the implications of this.

Internal data CLK

When EXT/INT is low-bound, the result of conversion 'n' is serially transmitted during conversion 'n+1', as shown in Figure 5, and the timings are given in Table II. Serial transfer of data occurs only during conversions. When a transfer is not in progress, DATA and DATACLK are low.

During conversions, the results of previous conversions are transferred through the data, and DATACLK provides the synchronous clock for the serial data. The data format is 16 bits, two's complement, MSB first. Each data bit is on the data clock. BUSY is low during the entire serial transmission and can be used as a frame synchronization signal.

External data CLK

When EXT/INT is bound HIGH, the result of transition "n" will be timed after the transition is complete, during the next transition ("n+1"), or a combination of the two. Figure 6 shows how the conversion result is read after conversion is complete. Figure 7 describes the process of reading the result during the next conversion. Figure 8 combines the important aspects of Figures 6 and 7 with regard to reading part of the results after the conversion is complete and reading the remaining results during the next conversion.

Serial transfer of conversion results is initiated by a rising edge on DATACLK. The data format is 16 bits, Figure 6. Serial data timing, external clock, clock after conversion completion (EXT/INT HIGH, CS LOW). Two's complement, and MSB first. Each data bit is valid on the falling edge of DATACLK. The rising edge of the DATACLK signal may be used in some cases. However, the last bit requires an extra clock cycle (not shown in Figures 6, 7, and 8).

The external data CLK signal must be low or CS must be held high before the busy rise (see time t25 in Figure 7 and Figure 8). If this is not observed during this period, the output shift register of the ADS7813 will not be updated with the conversion result. Instead, the previous contents of the shift register will be preserved and the new result will be lost.

Please refer to the "External Digital Signal Sensitivity" section of this data sheet before reading the next three paragraphs. This will explain many questions about how and when to apply the external DATACLK signal.

The preferred method of obtaining conversion results is to provide the DATACLK signal after the conversion is complete and before the next conversion begins, as shown in Figure 6. Note that the DATACLK signal should be static until the next conversion begins. If this is not observed, the DATACLK signal may affect the acquired voltage.

External data clk is active during next conversion

Another way to obtain the conversion result is shown in Figure 7. Since the output shift register is not updated until the end of the conversion, the previous result is still valid during the next conversion. If a fast clock (≥2MHz) can be supplied to the ADS7813, the result can be read during time t2. During this time, noise from the DATACLK signal is unlikely to affect the conversion result.

External data clk is active after conversion and during the next conversion

The method shown in Figure 8 is a hybrid of the first two methods. This method works very well for microcontrollers doing this serially transfer 8 bits at a time for slower microcontrollers. For example, if the fastest serial clock that the microcontroller can generate is 1 μs, the approach shown in Figure 6 will result in lower throughput (26kHz maximum slew rate). The method described in Figure 7 cannot be used without the risk of affecting the conversion result (the clock must be active after time t2). The method in Figure 8 results in improved throughput (33 kHz maximum at 1 kS) and data TACK is inactive after time T2.

Compatible with ADS7812

The only difference between the ADS7812 and ADS7813 is the internal control logic and digital interface. Since the ADS7812 is a 12-bit converter, the width of the internal shift register is 12 bits. Also, during the conversion process, only 12-bit decisions are made. Therefore, the conversion time of the ADS7812 is about 75% of that of the ADS7813.

In internal data clock mode, the ADS7812 generates 12 data clock cycles during conversions instead of 16 for the ADS7813 (see Figure 5). In external data clock mode, the ADS7812 can accept 16 clock cycles on the data clock. At the beginning of the 13th clock cycle, the data output will go low and remain low. Therefore, the associated times in Figures 6, 7, 8, and Table II can also be used for the ADS7812, but the last four bits of the conversion result will be zero.

Chip Select (CS)

The CS input allows disabling the digital outputs of the ADS7812 and strobes the external data CLK signal when EXT/INT is high. See Figure 9 for the timing of the ADS7813 logic block diagram in relation to CS and Figure 3 for enabling and disabling. Digital outputs can be disabled at any time.

Note that the conversion is possible even if CS is high. If the EXT/INT input is low (internal data CLK) and CS is high throughout the conversion, the previous conversion result will be lost (serial transfer occurs, but data and data CLK are disabled).

The ADS7813 offers many input ranges. This is accomplished by connecting three input resistors to the analog input (VIN), ground (GND), or the 2.5V referenced buffer output (BUF). Table 1 shows the input ranges commonly used in most data acquisition applications. These ranges are guaranteed to meet the specifications given in the specification sheet. Table IV contains a complete list of ideal input ranges, relevant input connections, and comments about the ranges.

The input impedance is derived from various connections and internal resistance values (refer to the block diagram on the front page of this data sheet). Internal resistance values are typical and can vary by ±30% due to process variation. However, the ratio matching of the resistors is much better than this. As a result, the input range varies by only a few tenths of a tenth from one section to another, while the input impedance varies by as much as ±30%.

The spec sheet contains the maximum limits for analog input range variation, but only for the range for which the comment field shows offset and gain are guaranteed (this includes all ranges listed in Table I). For other ranges, offset and gain are not tested and cannot be guaranteed.

The five input ranges in Table 4 are not recommended for general use. The upper end of the -2.5V to 175V range and the 2.5V to 22.5V range exceed the absolute maximum analog input voltage. These ranges can still be used as long as the input voltage remains below the absolute maximum, but this will moderately reduce the full-scale range of the converter.

Likewise, the three input ranges involve connections to R2IN being driven below GND. This input has a reverse ESD protection diode to ground. If R2IN is below GND – 0.3V, the diode will forward bias and clamp the negative input at –0.4V to –0.7V, depending on temperature. Since these input ranges have negative full-scale values in excess of –0.4V, their use is not recommended.

Note that Table IV assumes that the reference pin is at 2.5V. 2.5V if using the internal reference or if the external reference is 2.5V. Other reference voltages will change the values in Table IV.

High impedance mode

When R1IN, R2IN, and R3IN are connected to the analog inputs, the input range of the ADS7813 is 0.3125V to 2.8125V, and the input impedance is greater than 10MΩ. This input range can be used to connect the ADS7813 directly to various sensors. Figure 10 shows the impedance of the sensor as a function of the ILE and DLE of the ADS7813. The performance of the ADS7813 can increase the sensor impedance by allowing more acquisition time. For example, for the same IL/DLE performance, an acquisition time of 10 seconds will approximate the two-sensor impedance.

The input impedance and capacitance of the ADS7813 are very stable over temperature. Assuming the same is true for the sensor, the graph shown in Figure 10 will vary by less than a few percent over the guaranteed temperature range of the ADS7813. If the sensor impedance varies significantly with temperature, the worst-case impedance should be used.

Driving the ADS7813 analog input

In general, any "fairly fast", high-quality op or instrumentation amplifier can be used to drive the ADS7813 inputs. When the converter enters acquisition mode, some charge is injected from the converter's input to the amplifier's output. This can result in insufficient settling time for slower amplifiers. Be careful with single-supply amplifiers, especially if their outputs need to be very close to the supply rails.

Also, pay attention to the linearity of the amplifier. The output of single-supply and "rail-to-rail" amplifiers can saturate near the supply rails. Rather than the amplifier's transfer function being a straight line, the curve can become severely 's' shaped. Also, note where the amplifier switches from sourcing to sinking current. For some amplifiers, the transfer function can be significantly discontinuous at this point, resulting in a significant change in output voltage with a much smaller change in input voltage.

Burr Brown manufactures a wide variety of op amps and instrumentation amplifiers that can be used to drive the inputs of the ADS7813. These include the OPA627, OPA132 and INA110.

refer to

The ADS7813 can operate with its internal 2.5V reference or with an external reference. The internal reference voltage is overdriven by applying an external reference voltage to the reference pin. The voltage at the REF input is internally buffered by a unity gain buffer. The output of the buffer appears on the BUF and CAP pins.

referee

The reference pin is the output of the internal 2.5V reference or the input of the external reference. A 1 to 2.2µF tantulum capacitor should be connected between this pin and ground. The capacitors should be placed as close as possible to the ADS7813.

When using an internal reference, the reference pin should not be connected to a payload of any kind. An external load will cause a voltage drop across the internal 4kΩ resistor in series with the internal reference. Even a 40MΩ external load-to-ground results in a full-scale range of the converter of 6 LSBs.

The range of the external reference voltage is 2.3V to 2.7V. The reference voltage determines the full-scale range of the converter and the corresponding LSB size. Increasing the reference voltage will increase the LSB size associated with internal noise sources, which in turn can improve the signal-to-noise ratio of the signal. Likewise, lowering the reference voltage will reduce the LSB size and signal-to-noise ratio.

hat

Cover pins are used to compensate for the internal reference buffer. A 1µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor should be connected between this pin and ground, as close to the ADS7813 as possible. The total capacitance on the cap pins is critical to the best performance of the ADS7813. Values greater than 2.0µF may overcompensate the buffer, while values less than 0.5µF may not provide adequate compensation.

buffer

The voltage on the BUF pin is the output of the internal reference buffer. This pin is used to provide +2.5V for analog inputs or inputs in various input configurations.

The BUF output can supply up to 1 mA to an external load. The load should be constant because a variable load can affect the conversion result by adjusting the BUF voltage. Also note that the BUF output will show obvious glitches at every decision in the conversion process. Between transitions, the BUF output is quiet.

power outage

The ADS7813 has a power-down mode that consists of having CONV low and then PWRD high. This will power down all analog circuits, including the reference, reducing power consumption to less than 50µW.

In power-down mode, CONV is high, then PWRD is low. Note that if PWRD is high when CONV is low.

In power down mode, the voltage across the capacitors connected to CAP and REF will start to leak. The voltage leakage across the capacitor is much faster than the voltage leakage across the reference capacitor (when PWDN is high, the reference input of the ADS7813 becomes high impedance, which does not apply to the capacitor input). When power-down mode is exited, these capacitors must be allowed to charge and settle to 16-bit levels. Figure 11 shows the amount of time it typically takes to get a valid 16-bit result based on the power-off time (at room temperature). This figure assumes a total capacitance of 1.01µF on the cap pins.

Figure 12 provides a circuit that can significantly reduce the power-on time if the power-off time is relatively short (several seconds or less). A low on-resistance MOSFET is used to disconnect the capacitance on the cap pin from the leakage path inside the ADS7813. This allows the capacitor to remain charged for a longer period of time, reducing the time it takes to power up and charge. In this kind of circuit, the power-off time can be extended to tens of milliseconds or hundreds of milliseconds, and the power is turned on almost instantaneously.

layout

The ADS7813 should be considered a precision analog component and should be located entirely on the "analog" portion of the printed circuit board. Ideally, the ground plane should extend below the ADS7813 and below all other analog components. This plane should be separated from the digital ground until they are connected at the power connection. This will help prevent dynamic digital ground currents from modulating the analog ground through the common impedance.

The +5V supply should be clean, well regulated, and separate from the +5V supply in the digital portion of the design. One possibility is to get the +5V supply from a linear regulator near the ADS7813. If sourced from a digital +5V supply, a 5Ω to 10Ω resistor should be placed in series with the power connection of the digital supply. It may also be necessary to add bypass capacitors near the VS pin (additional 100µF or larger capacitors in parallel with the 10µF and 0.1µF capacitors). For designs with a large number of digital components or high-speed digital logic, this simple power supply filtering scheme may not be sufficient.

Sensitivity to external digital signals

A/D converters based on successive approximation registers are sensitive to external noise sources. The reason will be explained in the following paragraphs. For the ADS7813 and similar A/D converters, this noise is usually caused by the conversion of external digital signals. While digital signals running near the converter can be a source of noise, the biggest problem occurs on the digital inputs of the converter itself.

In many cases, the system designer may not be aware of a problem or potential problem. For 12-bit systems, these problems usually occur at least in the significant bits, and only in certain places in the converter transfer function. For a 16-bit converter, this problem is easier to spot.

For example, the timing diagram in Figure 2 shows that for some time period during time t2, the CONV signal should return to HIGH. In fact, the CONV signal can return high at any time during the conversion process. However, after time t2, the transition of the CONV signal has the potential to generate a lot of noise on the ADS7813 chip. If this conversion happens to happen at the wrong time, the conversion result may be affected. In a similar fashion, transitions on the DATACLK input may affect the conversion result.

For the ADS7813, there are 16 individual bit decisions during conversion. The most significant bit decision is made first, continuing with the least significant bit at the end of the conversion. Every bit decision involves an assumption that the bit being tested should be set. This is combined with the results achieved so far. The converter compares this combined result to the actual input voltage. This bit is cleared if the combined result is too high. This bit remains high if the result is equal to or lower than the actual input voltage. This is why the basic architecture is called "successive approximation registers".

If the results so far are very close to the actual input voltage, then the comparison involves two very close voltages. The ADS7813 is designed so that the internal noise source is minimal until the comparator result is locked. However, if the external digital signal is converted at this time, a lot of noise will couple into the sensitive analog parts of the ADS7813. Even if this noise produces a difference of only 2mV between the two voltages, the conversion result will be turned off by 52 counts or the least significant bit (lsb). (Regardless of the input range, the internal LSB size of the ADS7813 is 38µV.)

Once a digital conversion causes the comparator to make a wrong bit decision, that decision cannot be corrected (unless some type of error correction is employed). All subsequent bit decisions will be wrong. Figure 13 shows a faulty successive approximation process. The dotted line indicates what the correct bit decision should be. The solid line represents the actual result of the conversion.

Remember that the time period during which the comparator is most sensitive to noise is fairly small. Furthermore, the peak portion of the noise "event" produced by digital conversion is rather short, since most digital signals convert within a few nanoseconds. Subsequent noise may persist longer than this and may lead to further effects requiring longer settling times. In general, however, events are over within tens of nanoseconds.

For the ADS7813, error correction is performed when the 10th bit is determined. During this bit decision, limited errors that may have occurred during previous bit decisions can be corrected. However, after the 10th bit, such correction is not possible. Note that for the timing diagrams shown in Figures 2, 5, 6, 7, and 8, all external digital signals should be held for a quiet time from 8 microseconds after the start of conversion to the busy rise. The tenth digit decides about 10 seconds to 11 seconds into the transition.

application information

transition noise

If a low noise DC input is applied to the ADS7813 and 1000 conversions are performed, the digital output of the converter will vary slightly in the output code. This is true for all 16-bit SAR converters. The Transition Noise Specification in the Specifications section is a statistic that represents the one-sigma limit for these output codes.

Use a histogram to plot the number of occurrences of each output code, the distribution should be bell-shaped, with the peaks of the curve representing the nominal output code for a given input voltage. The ±1σ, ±2σ, and ±3σ limits around this nominal code should encompass 68.3%, 95.5%, and 99.7% of the conversion results, respectively. As a rough approximation, multiplying the multiplicative transition noise by 6 (±3) will yield the number of unique output codes that should exist in 1000 transitions.

The ADS7813 has a transition noise figure of 0.6LSB and produces about 4 different output codes for 1000 conversions. However, since ±3σ is only 99.7%, it is possible for up to 3 transitions to fall outside this range. Furthermore, the differential linearity error of each code and the quantization performed by the converter cause the histogram to deviate from ideal. Figure 14 shows a histogram of 5000 transitions from the ADS7813.

average value

By averaging the conversion results, the noise of the converter can be reduced. Noise will be doubled by 1/√n, where 'n' is the mean. For example, averaging four transitions will cut the transition noise in half to 0.3lsb. Average can only be used for low frequency signals.

For high frequency signals, digital filters can be used to reduce noise. It works in a similar way to averaging: for every two reductions in the signal bandwidth, the signal-to-noise ratio increases by 3 dB.

QSPI interface

Figure 15 shows a simple interface between the ADS7813 and any queued serial peripheral interface (QSPI) equipped with a microcontroller (available on several Motorola devices). This interface assumes that the conversion pulses do not come from the microcontroller and that the ADS7813 is the only serial peripheral.

Before enabling the QSPI interface, the microcontroller must be configured to monitor the slave select (SS) line. The port can be enabled when a low-to-high transition occurs (indicating the end of the transition). If this is not done, the microcontroller and A/D converter may not be properly synchronized. (The slave select line only enables communication and does not indicate the start or end of a serial transfer.)

Figure 16 shows a QSPI-equipped microcontroller interfacing with three ADS7813s. There are many possible variations of this interface scheme. As shown, the QSPI port generates a common conversion signal that initiates conversion on all three converters. After the conversion is complete, transmit each result in turn. The QSPI port is fully programmable and handles timing and transfers without processor intervention. If the CONV signal is generated in this way, AC and DC measurements should be possible with the ADS7813 because the CONV signal will have low jitter. Note that if the CONV signal is generated by software commands, it will have a lot of jitter and the SPI interface Serial Peripheral Interface (SPI) is directly related to QSPI, both Figure 15 and Figure 16 can be used to connect the ADS7813 to a SPI-equipped micro A guide for the controller. For most microcontrollers, the SPI port can only do 8-bit transfers. In the case of Figure 15, note that the microcontroller may have to be able to fetch the 8 most significant bits before being overwritten by the 8 least significant bits.

DSP56002 interface

The DSP56002 serial interface has an SPI compatibility mode and some enhancements. Figure 17 shows the interface between the ADS7813 and the DSP56002. Just like the QSPI interface of Figure 15, the DSP56002 must be programmed so that a high transition occurs at the SCI. The DSP56002 can also provide the CONV signal as shown in Figure 18. The receive and transmit parts of the interface are separated (asynchronous mode), the transmit part is set to transmit frames per other (frame rate divider set to 2). This should set the prescale modulo to produce transmission frames twice the desired conversion rate.