feature

Non-volatile memory holds wiper settings; 256 -bit LFCSP-10 (3 mm x 3 mm x 0.8 mm) thin package; compact MSOP-10 (3 mm x 4.9 mm x 1.1 mm) package; I2C 174 ; compatible interface; VLogic pins provide increased interface flexibility; end-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ; resistance tolerance stored in EEPROM (0.1% accuracy); power-up EEPROM refresh time < 1 ms; software Write Protect Command; Address Decode Pin AD0 and Pin AD1 Enable; 4 Packets Per Car; 100 Years Typical Data Retention at 55°C; Wide Operating Temperature -40°C to +85°C; 3 V to 5 V Single power supply.

application

LCD panel VCOM adjustment; LCD panel brightness and contrast control; replacement of mechanical potentiometer in new design; programmable power supply; RF amplifier bias; automotive electronics adjustment; gain control and offset adjustment; fiber-to-the-home system; electronic level setting.

General Instructions

The AD5259 provides a compact, nonvolatile LFCSP-10 (3 mm × 3 mm) or MSOP-10 (3 mm × 4.9 mm) package solution for 256 position adjustment applications. These devices perform the same electronic adjustment functions as mechanical potentiometers or variable resistors, but with higher resolution and solid-state reliability. The wiper settings can be controlled via the I2 C-compatible digital interface, which is also used to read the wiper registers and EEPROM contents. Resistance tolerances are also stored in EEPROM, providing 0.1% end-to-end tolerance accuracy. A separate VLogic pin provides increased interface flexibility. For users who need multiple parts on a bus, address bits AD0 and AD1 allow up to four devices on the same bus.

ESD warning

Stresses listed above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Electrostatic discharge sensitive devices. Electrostatic charges of up to 4000 volts can easily build up on the human body and test equipment and can be discharged without detection. Although this product has proprietary ESD protection circuitry, permanent damage may occur on equipment subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

test circuit

Figures 32 to 37 illustrate test circuits that define the test conditions used in the product specification sheet.

theory of operation

The AD5259 is a 256-bit digitally controlled variable resistor (VR) device. The EEPROM is preloaded to mid-scale from the factory, so initial power-up is at mid-scale.

Variable Resistor Programming

Rheostat operation

The nominal resistance (R) of the RDAC between Terminal A and Terminal B is 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ, respectively. The nominal resistance of the VR has 256 contacts accessible through the wiper terminals. Decode the 8-bit data in the RDAC latch to select one of 256 possible settings.

The general formula for determining the digitally programmed output resistance between wiper W and terminal B is:

where: D is loaded in the 8-bit RDAC register. RAB is end-to-end resistance. RW is controlled by each internal switch.

Under zero-scale conditions, there is a relatively low finite wiper resistance value. It should be noted that the current flow between the wiper W and the terminal B is limited to a maximum pulse current of not more than 20 mA in this state. Failure to do so may result in degradation or damage to the internal switch contacts.

Similar to a mechanical potentiometer, the resistance of the RDAC between wiper W and terminal A produces a digitally controlled complementary resistance R. The resistance value of R is set starting at the maximum value of the resistance and decreasing as the value of the data loaded in the latch increases. The general equation for this operation is:

Typical equipment-to-equipment matching is process batch dependent and can vary by as much as ±30%. Therefore, the resistance tolerance is stored in the EEPROM, enabling the user to know that the actual R is within 0.1%.

Program the Potentiometer Divider

Voltage output operation

A digital potentiometer easily creates a voltage divider proportional to the input voltage from terminal a to terminal B at wiper W to terminal B and wiper W to terminal a. Unlike the V to GND polarity, which must be positive, the voltage across terminal a to terminal B, wiper W to terminal a, and wiper W to terminal B can be in either polarity.

If you ignore the effect of wiper resistance on the approximation, connecting terminal A to 5 V and terminal B to ground produces an output voltage at wiper W to terminal B, starting at 0 V to less than 1 volt LSB. For any effective input voltage applied to terminal A, a general equation for the output voltage at V with respect to ground is defined. Terminal B is:

A more precise calculation includes the effect of the wiper resistance V:

Operation of the digital potentiometer in voltage divider mode results in more accurate overtemperature operation. Unlike the rheostat mode, the output voltage is mainly determined by the ratio of the internal resistances R and R, not the absolute value.

I2C Compatible Interface

The master initiates a data transfer by establishing a start condition, a high-to-low transition on the SDA line while SCL is high (see Figure 4). The next byte is the slave address byte, which contains the slave address (the first 7 bits) followed by the R/W bit (see Table 6). When the R/W bit is high, the master device reads data from the slave device. When the R/W bit is low, the master device writes to the slave device.

The slave address of the part is determined by two configurable address pins, pin AD0 and pin AD1. The states of these two pins are registered and decoded into the corresponding IC7 bit addresses at power-up (see Table 5). The slave address corresponding to the transmit address bit responds by pulling the SDA line low during the ninth clock pulse (this is called the slave acknowledge bit). During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial registers. 2

writing

In write mode, the last bit (R/W) of the slave address byte is logic low. The second byte is the instruction byte. The first three bits of the instruction byte are the instruction bits (see Table 6). The user must choose whether to write to the RDAC registers, EEPROM registers, or activate software write protection (see Table 7 to Table 10). The last five digits are all zeros (see Tables 13 to 14). The slave pulls the SDA line low again during the ninth clock pulse.

The last byte is the data byte MSB first. In write-protected mode, no data is stored; instead, a logic high in the LSB enables write protection. Likewise, logic low disables write protection. The slave pulls the SDA line low again during the ninth clock pulse.

save/restore

In this mode, only the address and instruction bytes are necessary. The last bit (R/W) of the address byte is the logic low bit. The first three bits of the instruction byte are the instruction bits (see Table 6). The two options are to transfer data from RDAC to EEPROM (storage), or from EEPROM to RDAC (restore). The last five digits are all zeros.

read

Assuming the register of interest is not directly writeable, it is necessary to write a virtual address and instruction byte. The instruction byte will vary depending on whether the required data is an RDAC register, an EEPROM register, or a tolerance register (see Table 11 and Table 16).

After sending the virtual address and instruction bytes, a repeated start is required. After the repetition starts, another address byte is required, but this time the R/W bit is logic high. This address byte is followed by a readback byte containing the information requested in the instruction byte. The read bit occurs on the negative edge of the clock.

Tolerance registers can be read individually (see or consecutively. See the "Read Modes" section for details on interpreting tolerance bytes.

After all data bits have been read or written, the master will establish a stop condition. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 46). In read mode, the master responds with a no to the ninth clock pulse (ie the SDA line is held high). Then, before the tenth clock pulse, the master pulls the SDA line low and then SDA high to establish a stop condition (see Figure 47).

The Repeat Write feature gives the user the flexibility to update the RDAC output multiple times after addressing and instructing the part once. For example, after the RDAC acknowledges its slave address and instruction byte in write mode, the RDAC output is updated on each successive byte until a stop condition is received. If a different instruction is required, the write/read mode must start over with a new slave address, instruction and data bytes. Likewise, the repeated read function of the RDAC is also allowed.

I2C Compatible Format

The following general purpose, write, read and store/restore controls AD1 and AD0 are the two status address pins.

The registers of the AD5259 are all referenced to the device addresses listed in Table 5; the mode/condition reference keys (S, P, SA, MA, NA, W, R, and X) are shown below.

S = start condition

P = stop condition

SA=Slave Confirmation

MA = Master Confirmation

NA = not admitted

W=Write

R=read

X = don't care

Common interface

AD1 and AD0 are two status address pins.

To activate write-protect mode, the WP bit in Table 10 must be logic high. To deactivate write protection, the command must be sent again unless WP is in a logic zero state. If you cycle power off and on, WP will reset to deactivated mode.

read mode

Read mode is called legacy mode because the first two bytes in all three cases are dummy bytes used to point the pointer to the correct register; this is the reason for the repeated start. In theory, this step can be avoided if the user reads a previously written register. For example, if the EEPROM has just been written, then the user can skip two dummy bytes and go straight to the slave address byte followed by the read back data of the EEPROM.

The AD5259 features patented R-tolerance memory in nonvolatile memory. Tolerances are stored in memory during factory production and can be read by the user at any time. Knowledge of the stored tolerance allows the user to calculate R precisely. This feature is useful for accuracy, rheostat mode, and open loop applications where knowledge of absolute resistance is critical.

The stored tolerance is in read-only memory and is expressed as a percentage. Tolerances are stored in two memory location bytes in symbol-sized binary (see Figure 41).

The two EEPROM address bytes are 11110 (sign + integer) and 11111 (decimal). These two bytes can be accessed independently by two separate commands (see Table 15). Alternatively, the first byte can be read followed by the second byte in one command (see Table 16). In the latter case, the memory pointer will automatically increment from the first EEPROM location to the second EEPROM location (from 11110 to 11111) if there are consecutive reads.

In the first memory location, specify the MSB as the sign (0=+ and 1=-) and the seven lsb as the integer part of the tolerance. In the second memory location, all eight data bits are designated as the fractional part of the tolerance. Note that the fractional part has a limited precision of 0.1%. For example, if the rated R=10 kΩ and the data read from address 11110 shows 0001 1100 and address 11111 shows 0000 1111, the tolerance can be calculated as:

MSB: 0 = +;

next 7 MSB: 001 1100 = 28;

8 least significant bits: 0000 1111=15×2–8=0.06;

Tolerance = +28.06%;

Rounding tolerance = +28.1%, so RAB_actual = 12.810 kΩ.

ESD Protection of Digital Pins and Resistor Terminals

The AD5259 V, V, and GND supplies define the boundary conditions for proper 3-terminal and digital input operation. Supply signals that appear on Terminal A, Terminal B, and Terminal W in excess of V or GND are clamped by internal forward-biased ESD protection diodes (see Figure 42). Digital input SCL and digital input SDA are clamped with respect to V and GND by ESD protection diodes, as shown in Figure 43.

power-on sequence

Since the ESD protection diodes limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 42), it is very important to energize GND/V/V before applying any voltage to Terminal A, Terminal B, and Terminal W. Important; otherwise, the diode is forward biased, so V and V are unintentionally energized, potentially affecting the user circuit. The ideal power-up sequence is as follows: GND, V, V, digital input, then V, VB, V.

Layout and Power Bypass

It is a good practice to use a layout design with compact, minimum lead lengths. Wires to the input should be as direct as possible with minimal wire length. The ground path should have low resistance and low inductance.

Also, for best stability, it is a good practice to bypass the power supply with a high quality capacitor. A 0.01µF to 0.1µF chip or chip ceramic capacitor should be used to bypass the device's power supply lines. A low ESR 1µF to 10µF tantalum or electrolytic capacitor should also be used at the power supply to minimize any transients and low frequency ripple (see Figure 44). The digital ground should also be remotely connected to a point on the analog ground to minimize ground bounce.

Multiple devices on a bus

The AD5259 has two configurable address pins, pin AD0 and pin AD1. The state of these two pins is registered and decoded to the corresponding I2C-compatible 7-bit address at power-up (see Table 5). This allows up to four devices on the bus to write or read independently.

Evaluation Committee

There is an evaluation board that includes all the necessary software to program the AD5259/2000/experience from any PC running Windows® 98. The graphical user interface, shown in Figure 45, is simple to use. More detailed information can be found in the board's user manual.

show application

circuit

A feature of the AD5259 is its unique separation of the V and V supply pins. Separation provides more flexibility in applications where the required supply voltage is not always available. In particular, liquid crystal panels typically require a voltage range of 3V to 5V. A rare exception is the circuit in Figure 46, where the 5V supply powers the digital potentiometer.

In the more common case shown in Figure 47, only the analog 14.4V and digital logic 3.3V supplies are available. By placing discrete resistors above and below the digital potentiometer, it is now possible to tap V from the resistor string itself. Depending on the resistor value chosen, in this case, the voltage at V equals 4.8 V, allowing the wipers to operate safely all the way up to 4.8 V. The current consumption of V does not affect the bias of this node as it is only on the order of microamps. V is tied to the MCU's 3.3v digital power supply, as V will be the 35ma required when drawing to the EEPROM. Trying to power 35mA through a 70kΩ resistor is impractical, so V is not connected to the same node as V.

For this reason, V and V are provided as two separate power pins that can be tied together or handled independently; V provides power for logic/EEPROM, and V biases the A, B, and W terminals for added flexibility .

For more information on this application, see the article "Simple VCOM Adjustment Using Any Logic Supply Voltage" in EDN Magazine, September 30, 2004.

Dimensions