feature

AD5251 : Dual 64-bit resolution; AD5252 : Dual 256 -bit resolution; 1kΩ, 10kΩ, 50kΩ, 100kΩ; nonvolatile memory[1] stores write-protected wiper settings; uses 300 EEMEM set refresh power in microseconds; EEMEM rewrite time = 540 microseconds (typ); resistance tolerance stored in non-volatile memory; 12 extra bytes in EEMEM for user-defined information; I [2] C-compatible serial interface; direct read/write access to RDAC2 and EEMEM registers; predefined linear increment/decrement commands; predefined ±6dB step change commands; synchronous or asynchronous dual-channel updates; wiper Setup readback; 4 MHz bandwidth - 1 kΩ type single supply 2.7 V to 5.5 V; dual supply ±2.25 V to ±2.75 V; 2 slave address decode bits allow 4 device operation; 100 years typical data retention, TA=55 °C operating temperature: –40°C to +105°C.

application

Replacement of mechanical potentiometers; Universal DAC replacement; LCD panel VCOM adjustment White LED brightness adjustment; RF base station power amplifier bias control; Programmable gain and offset control; Programmable voltage current conversion Programmable power sensor calibration.

General Instructions

The AD5251/AD5252 are dual, IC® nonvolatile memory, 64/256-bit digitally controlled potentiometers, respectively. These devices perform the same electronic adjustment functions as mechanical potentiometers, trimmers, and variable resistors. The versatile programmability of the part allows multiple modes of operation, including read/write access in the RDAC and EEMEM registers, increment/decrement of resistance, change of resistance within ±6dB, readback of wiper settings, and Additional EEMEM for storing user-defined information, such as memory data for other components, look-up tables, or system identification information.

The AD5251/AD5252 allow the host IC controller to write a 64/256-step wiper setting in the RDAC register and store it in EEMEM. Once these settings are stored, they are automatically restored to the RDAC registers when the system is powered up; these settings can also be restored dynamically.

The AD5251/AD5252 provide additional increments, decrements, +6 dB step changes, and -6 dB step changes in synchronous or asynchronous channel update mode. Increment and decrement functions allow for stepwise linear adjustments with step changes of ±6 dB, equivalent to doubling or halving the RDAC wiper setting. These functions can be used for steep, non-linear adjustments such as white LED brightness and audio volume control.

The AD5251/AD5252 feature a patented resistance tolerance memory feature that allows the user to access the EEMEM and obtain the absolute end-to-end resistance value of the RDAC for precision applications.

The AD5251/AD5252 are available in TSSOP-14 packages in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are guaranteed to operate over the extended industrial temperature range of -40°C to +105°C.

RDAC/EEMEM write

Setting the wiper position requires an RDAC write operation. A single write operation is shown in Figure 27, and a continuous write operation is shown in Figure 28. In sequential write operations, if RDAC is selected and the address starts at 00001, the first data byte goes to RDAC1 and the second data byte goes to RDAC3. The RDAC addresses are shown in Table 6.

While RDAC wiper settings are controlled by specific RDAC registers, each RDAC register corresponds to a specific EEMEM location that provides non-volatile wiper memory functionality. The addresses are shown in Table 7. Single and sequential writes are also available for EEMEM writes.

There are 12 non-volatile memory locations: EEMEM4 to EEMEM15. Users can store a total of 12 bytes of information, such as memory data for other components, lookup tables, or system identification information.

During a write to the EEMEM register, the device disables the IC interface during an internal write cycle. Confirmation polling is required to determine the completion of a write cycle. See the EEMEM Write Acknowledge Polling section. 2

RDAC/EEMEM read

The AD5251/AD5252 provide two different RDAC or EEMEM read operations. For example, Figure 29 shows how to read the contents of RDAC0 to RDAC3 without specifying an address, assuming that address RDAC0 has been selected in the previous operation. If an RDAC_N address other than RDAC0 was previously selected, the readback starts at address N, then N+1, and so on.

Figure 30 shows a random RDAC or EEMEM read operation. This operation allows the user to specify which RDAC or EEMEM register to read by issuing a dummy write command to change the RDAC address pointer and then continue with an RDAC read operation at the new address location.

RDAC/EEMEM Quick Commands

The AD5251/AD5252 feature 12 quick commands for easy manipulation of RDAC wiper settings and provide RDACto EEMEM store and restore functionality. The command format is shown in Figure 31, and the command description is shown in Table 9.

When using fast commands, the third byte does not need to be issued, but it is allowed. The fast command to reset and store the RDAC to the EEMEM requires an acknowledgement poll to determine if the command has completed execution.

RAB tolerance stored in read-only memory The AD5251/AD5252 have a patented R tolerance stored in nonvolatile memory. Tolerances for each channel are stored in memory during factory production and can be read by the user at any time. The knowledge of the stored tolerance is the average of R across all codes (see Figure 16), enabling the user to accurately predict R. This feature is valuable for accuracy, varistor mode, and open-loop applications where knowledge of absolute resistance is critical.

Stored tolerances are in read-only memory and are expressed as a percentage. Each tolerance is stored in two memory locations (see Table 10). Tolerance data is represented in a symbol-sized binary format, stored in two bytes; an example is shown in Figure 32. For the first byte in register N, specify the MSB as the sign (0=+ and 1=-) and 7lsb as the integer part of the tolerance. For the second byte in register N+1, all 8 data bits are specified as the fractional part of the tolerance. As shown in Table 10 and Figure 32, for example, if the rated R is 10 kΩ and the data read from address 11000 shows 0001 1100 and address 11001 shows 0000 1111, the RDAC0 tolerance can be calculated as:

MSB:0=+

Next 7 MSB: 001 1100=28

8 least significant bits: 0000 1111=15×2=0.06–8

Tolerance = 28.06%, therefore,

R=12.806 kohm actual value

EEMEM write confirmation polling

After each write to the EEMEM register, an internal write cycle begins. The device's IC interface is disabled. To determine if the internal write cycle is complete and if the IC interface is enabled, interface polling can be performed. IC interface polling can be done by sending a start condition followed by the slave address and write bits. If the IC interface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. On the other hand, IC interface polling can be repeated until successful. Command 2 and Command 7 also require confirmation polling.

EEMEM write protection

After EEMEM is programmed, setting the WP pin to logic low protects the memory and RDAC registers from future write operations. In this mode, EEMEM and RDAC read operations work normally.

The first byte of the AD5251/AD5252 is the slave address byte (see Figure 33 and Figure 34). It has a 7-bit slave address and an R/W bit. The 5 MSBs of the slave address are 01011, the next 2 LSBs are determined by the state of the AD1 and AD0 pins. AD1 and AD0 allow the user to place up to four AD5251/AD5252 devices on one bus. The AD5251/AD5252 can be controlled via an I2C compatible serial bus and connected to this bus as a slave device. The two-wire I2C serial bus protocol (see Figure 33 and Figure 34) is as follows:

1. The host initiates a data transfer by establishing a start condition such that while SCL is high, SDA goes from high to low (see Figure 33). The following bytes are the slave address bytes, consisting of the 5 MSBs of the slave address defined as 01011. The next two bits are AD1 and AD0, the IC device address bits. Depending on the state of the AD1 and AD0 bits, four AD5251/AD5252 devices can be addressed on the same bus. The last LSB (R/W bit) determines whether data is read from or written to the slave device.

The slave whose address corresponds to the transmit address responds by pulling the SDA line low during the ninth clock pulse (this is called the acknowledge bit). During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial registers.

2. In write mode (except when restoring EEMEM to the RDAC register), the slave address byte is followed by an instruction byte. The MSB of the instruction byte is marked as CMD/REG. MSB=1 enables CMD, command instruction byte; MSB=0 enables regular register writing. The third MSB marked EE/RDAC in the instruction byte is true when MSB=0 or the device is in regular write mode. EE enables the EEMEM register and REG enables the RDAC register. 5 LSBs, A4 to A0, represent the addresses of the EEMEM and RDAC registers (see Figure 27 and Figure 28). When MSB=1 or the device is in command mode, the four bits following the MSB are C3 to C1, which correspond to the 12 predefined EEMEM controls and quick commands; there are also four factory reserved commands. 3 LSB-A2, A1 and A0 are addresses, but only 001 and 011 are used for RDAC1 and RDAC3 respectively (see Figure 31). After acknowledging the command byte, the last byte in the write mode is the data byte. Data is transferred over the serial bus in a sequence of 9 clock pulses (8 data bits followed by an acknowledgment bit). A transition on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 33).

3. In the current read mode, the RDAC0 data byte follows the acknowledgment of the slave address byte. After confirmation, RDAC1 follows, then RDAC2, and so on. (There is a slight difference in write mode, where the last 8 data bits representing RDAC3 data are followed by a no-acknowledge bit.) Likewise, transitions on the SDA line must occur during the low period of SCL and during the high period of SCL The period remains stable (see Figure 34). Another reading method, the random reading method, is shown in Figure 30.

4. When all data bits have been read or written, the host will establish a stop condition. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during 10 clock pulses to establish a stop condition (see Figure 33). In read mode, the master issues no acknowledgement to the ninth clock pulse, ie the SDA line remains high. The master device drives the SDA line low before 10 clock pulses and then drives the SDA line high to establish a stop condition (see Figure 34).

theory of operation

The AD5251/AD5252 are 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ dual-channel digital potentiometers that allow 64/256 linear resistive step adjustment. The AD5251/AD5252 utilize dual-gate CMOSEEPROM technology that allows resistance settings and user-defined data to be stored in the EEMEM registers. EEMEM is non-volatile, so the settings remain the same when powered down. RDAC wiper settings are restored from non-volatile memory settings during device power-up and can also be restored at any time during operation.

The AD5251/AD5252 resistor wiper position is determined by the contents of the RDAC register. The RDAC register acts like a scratch pad register, allowing infinite changes in resistance settings. The RDAC register contents can be changed using the device's serial IC interface. The format of the data word and the commands to program the RDAC registers are discussed in the IC Interface Details section.

The four RDAC registers have corresponding EEMEM memory locations that provide nonvolatile storage of resistive wiper position settings. The AD5251/AD5252 provide commands to store the RDAC register contents to their respective EEMEM memory locations. On subsequent power-up sequences, the RDAC register is automatically loaded with the stored value.

Whenever an EEMEM write operation is enabled, the device activates the internal charge pump and raises the EEMEM cell gate bias voltage to a higher level; this effectively erases the current contents of the EEMEM register and allows subsequent storage of new content. Saving data to the EEMEM register consumes about 35 mA of current and lasts about 26 ms because of the charge pump operation, all RDAC channels may experience noise coupling during EEMEM write operations.

The EEMEM recovery time during power up or operation is approximately 300 microseconds. Note that the power-on EEMEM refresh time depends on how quickly V reaches its final value. Therefore, any supply voltage decoupling capacitors will limit the recovery time of the EEMEM during power-up. For example, Figure 20 shows a power-on curve with no decoupling capacitors and the applied power is V of a digital signal. The device first resets the measured rdac to midscale before restoring the EEMEM content. By default, EEMEM will load at midscale before loading new values. Omitting decoupling capacitors should only be considered if fast recovery times are absolutely required in the application. Additionally, the user should issue a NOP Command 0 immediately after using Command 1 to restore the EEMEM setting to RDAC to minimize supply current consumption. Reading user data directly from EEMEM does not require a similar NOP command execution.

In addition to moving data between the RDAC and EEMEM registers, the AD5251/AD5252 provide other shortcut commands for easy programming, as shown in Table 11.

Linear Increment/Decrement Commands

The increment and decrement commands (10, 11, 5, and 6) are useful for linear step size adjustment applications. These commands simplify microcontroller software coding by allowing the controller to only send increment or decrement commands to the AD5251/AD5252. Adjustments can be directed to a single RDAC or to all four RDACs.

±6dB adjustment (doubled/halved wiper setting)

The AD5251/AD5252 adjust the RDAC wiper position by ±6 dB by shifting the register contents to the left/right for increment/decrement operations, respectively. Command 3, Command 4, Command 8, and Command 9 can be used to increment or decrement the wiper position by 6 dB synchronously or asynchronously.

A wiper position increase of +6db is actually twice the RDAC register value, while a wiper position decrease of -6db is half the register content. Internally, the AD5251/AD5252 use shift registers to shift bits left and right to achieve ±6dB increments or decrements. The maximum number of adjustments are nine and eight steps, incrementing from zero scale and decrementing from full scale, respectively. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings, where the human visual response is more sensitive to large adjustments than small ones.

Digital input/output configuration

SDA is a digital input/output with an open drain MOSFET that requires a pull-up resistor for proper communication. On the other hand, SCL and WP are digital inputs that have ESD protection diodes when the drive signal is lower than V. SCL and WP are shown in Figure 35 and Figure 36.

If the write protection function is not used. If WP is left floating, the internal current source will pull it low to enable write protection. In applications where the device is infrequently programmed, this allows the part to default to write-protect mode after any one-time factory programming or field calibration, without the need for onboard pull-down resistors. Since all inputs have protection diodes, the signal level must not be greater than V to prevent forward biasing of the diodes.

Multiple devices on a bus

The AD5251/AD5252 have two addressing pins, AD1 and AD0, allowing up to four AD5251/AD5252 devices to be operated on one IC bus. To achieve this result, the state of AD1 and AD0 on each device must first be defined. Examples are shown in Table 12 and Figure 37. In IC programming, each device is issued a different slave address 01011 (AD1) (AD0) to complete the addressing.

Terminal voltage operating range

The AD5251/AD5252 are protected with internal ESD diodes; these diodes also set the boundaries of the terminal operating voltage. Positive signals that appear on Terminal A, Terminal B, or Terminal W in excess of V are clamped by forward-biased diodes. Similarly, negative signals on Terminal A, Terminal B, or Terminal W that are more negative than V are clamped (see Figure 38). In practice, users should not operate V, V, and V above voltages between V and V, but V, V, and V have no polarity restrictions.

Power-Up and Power-Down Sequence

Since the ESD protection diodes limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 38), it is important to turn on the V/V supply before applying any voltage to these terminals. Otherwise, the diode is forward biased so that V/V is inadvertently energized and may affect the user's circuit. Similarly, V/V should be turned off last. The ideal power-up sequence is as follows: GND, V, V, digital input, and V/V/V. The order of V, V, V, and digital inputs does not matter as long as power is applied after V/V.

Layout and Supply Bias

It is always good practice to design a layout with a compact, minimum lead length. Wires to the input should be as direct as possible, with a minimum wire length. The ground path should have low resistance and low inductance.

Also, it is a good practice to bypass the power supply with a good quality capacitor. A low equivalent series resistance (ESR) 1µF to 10µF tantalum or electrolytic capacitor should be used at the power supply to minimize any transients and filter out low frequency ripple. Figure 39 illustrates the basic power supply bypass configuration for the AD5251/AD5252.

The ground pins of the AD5251/AD5252 are primarily used as digital ground references. To minimize digital ground bounce, the AD5251/AD5252 ground terminal should be remotely connected to common ground (see Figure 39).

Digital potentiometer operation

The structure of the RDAC is designed to simulate the performance of a mechanical potentiometer. The RDAC contains a series of resistive segments and a series of analog switches that act as wiper connections to the resistor array. Points are the resolution of the device. For example, the AD5251/AD5252 simulate 64/256 junctions with resistors R equal to 64/256, allowing them to provide better than 1.5%/0.4% resolution.

Figure 40 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC. Switches SW and SW are always open, but only one of switches SW(0) to SW(2) can be open at a time (determined by the settings decoded from the data bits). Because the switch is not ideal, there is a wiper resistance of 75Ω, R. Wiper resistance is a function of supply voltage and temperature: lower supply voltage and higher temperature result in higher wiper resistance. In applications where accurate prediction of output resistance is required, it is important to consider wiper resistance dynamics.

If the W-to-B or W-to-A terminals are used as variable resistors, the unused terminals can be opened or shorted with W; this operation is called varistor mode (see Figure 41). Resistance tolerance can be within ±20%.

The nominal resistance of the AD5251/AD5252 has 64/256 contacts connected through the wiper terminal and the B terminal contact. The 6/8-bit data word in the RDAC register is decoded to select one of the 64/256 settings. The first connection of the wiper starts from the B terminal of data 0x00. The wiper contact resistance R connected to this B terminal is 75Ω, independent of the nominal resistance. The second connection (the AD5251 10 kΩ part) is the first tap point for R=231Ω (R=R/64+R=156Ω+75Ω) of data 0x01, and so on. With each additional LSB data value, the wipers move up the resistor ladder until the last tap point is reached at R=9893Ω. A simplified diagram of the equivalent RDAC circuit is shown in Figure 40.

The general equation for determining the digitally programmed output resistance between W and B is:

where: D is the latch contained in the RDAC. RAB is the nominal end-to-end resistance.

Since digital potentiometers are not ideal, there is a limited wiper resistance of 75Ω, which is easy to see when the device is programmed to zero scale. Due to the delicate geometry and interconnect structure of the device, care should be taken to limit the current conduction between W and B to no more than ±5 mA continuous, 1 kΩ total resistance or ±20 mA pulsed to avoid device degraded or possibly damaged. The maximum dc currents for the AD5251 and AD5252 are shown in Figure 21 and Figure 22, respectively.

Similar to the mechanical potentiometer, the RDAC resistor between wiper W and terminal A also produces a digitally controlled complementary resistor R. When using these terminals, the B terminal can be opened. R starts at a maximum value and decreases as the data value loaded into the latch increases (see Figure 42). The general equation for this operation is:

In a given device, the typical distribution of R across channels is about ±0.15%. On the other hand, equipment-to-equipment matching depends on the process batch, with a tolerance of ±20%.

Programmable potentiometer operation

If all three terminals are used, the operation is called potentiometer mode (see Figure 43); the most common configuration is voltage divider operation.

If the wiper resistance is ignored, the transfer function is:

A more precise calculation includes the wiper drag effect:

where 2 is the number of steps.

Unlike rheostat mode operation, where tolerances are higher, potentiometer mode operation produces almost a ratio function of D/2, with relatively little error due to the R term. Therefore, the tolerance effect is almost canceled. Similarly, the ratio adjustment also reduces the temperature coefficient effect to 50 ppm/°C, except in the low R-dominant code.

Potentiometer mode operation includes other applications such as op amp inputs, feedback resistor networks and other voltage scaling applications. In fact, the A, W, and B terminals can be input or output terminals, as long as |V|, |V|, and |V| do not exceed V to V.

application information

LCD Panel V Adjustment Component Object Model

Large LCD panels typically require an adjustable V voltage centered around 6V to 8V with ±1V swing and small step adjustments. This example represents a common DAC application where the adjustment window is small and centered on any level. High voltage and high resolution DACs can be used, but it is much more cost-effective to use low voltage digital potentiometers with level shifting such as the AD5251 or AD5252 to achieve this.

Assuming a voltage requirement of 6 V ± 1 V, the step adjustment is ±20 mV, as shown in Figure 44. The AD5252 can be configured in voltage divider mode with op amp gain. With the AD5252 allowing ±20% tolerance, the circuit can still adjust from 5 V to 7 V with 8 mV/step in the worst case.

current sense amplifier

The dual-channel, simultaneous update, and channel-to-channel resistance matching features make the AD5251/AD5252 suitable for current sensing applications such as LED brightness control. In the circuit shown in Figure 45, when RDAC1 and RDAC3 are programmed to the same settings, it shows:

Therefore, the current through the sense resistor connected between V and V can be determined.

The circuit can be programmed for systems requiring different sensitivities. If the op amp has very low offset and low bias current, the main error comes from the digital potentiometer channel-to-channel resistance mismatch, typically 0.15%. The circuit accuracy is about 9 bits, which can meet general applications such as LED control.

Adjustable High Power LED Driver

Figure 46 shows a circuit that can drive three or four high-power LEDs. The ADP1610 is an adjustable boost regulator that provides enough headroom and current for the LEDs. Since its FB pin voltage is 1.2v, the digital potentiometer AD5252 and the op amp form an average gain of 12 feedback networks to servo the sense and feedback voltages. The result is that the voltage across R is regulated around 0.1v depending on the AD5252 settings. The adjustable LED current is:

R should be small enough to save power, but large enough to limit the maximum LED current. R3 should be used in parallel with the AD5252 to limit the LED current to within reach.

Dimensions