feature

AC'97 version. 2.1 Compliant; 18-bit resolution A/D and D/A; Exceeds PC98/99 /A+ mixer...89dBA SNR, AA......95 bar SNR; Analog Inputs: 4 Stereo Inputs: Line, CD, Video, AUX; Speaker and PC Beeper Inputs; 2 Separate mic input; direct PC beep pass-through for reduced system cost; analog outputs: stereo line out with volume control; solid line level with volume control; mono output with volume control; 3D stereo enhancement; multiple Codec function; AK4543 can be used as primary or secondary. Supports EAPD (External Amplifier Power Down) Power: Analog 5.0V, Digital 3.3V or 5.0V; low power consumption; 200mW at full load (analog: 5V/digital: 3.3V); 48-pin LQFP package.

General Instructions

The AK4543 is an 18-bit high performance codec that is compatible with Audio Codec '97 version 2.1 requirements. The AC link serial interface allows the AK4543 to be used with digital controllers, as well as custom logic accelerators to meet the full requirements of PC98 and PC99 for PCI audio solutions.

The AK4543 provides two pairs of independent stereo output volume controls as well as mono output, multiple stereo and mono inputs, which combine to create flexible mix, gain and mute functions to provide a complete integrated audio solution for PCs. The AK4543 can be used as a primary AC'97 or secondary codec depending on the codec ID configuration (multiple codec extensions), making the AK4543 suitable for docking applications with multiple codec applications such as 4 speaker outputs or 6 speaker output.

With a sampling frequency of 48kHz, the AK4543 provides excellent audio performance that meets or exceeds all standard requirements. It offers low power consumption and flexible power-down modes for laptops, desktops and aftermarket add-on boards. Like the earlier pin-compatible AK4540 and AK4542, the AK4543 is available in a compact 48-lead LQFP package. The AK4543 is the AK4540 and AK4542, some software changes are required to experience the extra features of the AK4543.

power ups

Note that the AK4543 must be in cold reset at power-up and reset# must be low before the main clock is stable, or reset must be done after the main clock is stable. AVdd or DVD can be powered by an independent power supply.

When using the AK4543 in multi-codec mode, all codecs connected to the AC link will wake up at the same time. A common reset line should be used to ensure clock synchronization after power-up.

Cold reset timing

Note that SDATA_OUT and SYNC must be low on the rising edge of RESET# for a cold reset. The AK4543 initializes all registers, including the power down control register, bit CLK is reactivated, and every analog output is in Hi-Z state, except for the PC beep when the reset pin is low. When the AK4543 is in a cold reset state, the PC beep is sent directly to the L&R line output. This is done to allow system sound to be delivered to the speakers removing redundant internal speakers.

At the rising edge of reset, AK4543 starts the initialization of the analog circuit, the period is 516fs. After that, the mixer of the AK4543 works fine.

When the AK4543 is in a reset cycle ("L") or during initialization, the status bit in slot 0 is "0" (not ready). After the initialization cycle, the status bit changes to '1', indicating a ready state.

When using the AK4543 in a multi-codec configuration and a cold reset is issued, all AK4543s connected to the AC link will perform a cold reset at the same time.

Warm reset

The AK4543 initiates the warm reset process by receiving a single pulse (Pin10) on sync. Then the AK4543 clears the PR4 and PR5 bits in the power-down control register. However, warm reset does not affect PR0~PR3 or PR6,7 bits in the power-down control register (26h). Note that after the AK4543 starts to output the bit clock, the sync signal should be synchronized with the bit clock. If an external clock is used, the external clock should be provided prior to issuing the sync pulse for warm reset.

When the AK4543 is used in a multi-codec configuration, please refer to the power-down/power-up sequence for a multi-codec configuration on a warm reset.

Note:

1. All AC link signals are normally low through the reset trailing edge. Turning SDATAŠu high to the reset rising edge causes the AK4543 AC link output to become high impedance, which is suitable for in-circuit ATE testing. Note that the AK4543 enters the ATE test mode regardless of whether the sync is high or low.

2. Setting SYNC high and SDATA_OUT low to the rising edge of RESET will cause AKM test mode.

3. Once in test mode, the only way to return to normal operation is to issue a "cold reset", a reset with SYNC and SDATA output low.

General Instructions

Connection of AC'97 to Digital AC'97 Controller

The AC'97 communicates with its companion AC'97 controller via a digital serial link "AC link". All digital audio streams and command/status information are communicated over a point-to-point serial interconnect. The diagram below shows the signal branch connecting the two.

AC'97 Digital Interface

The AK4543 integrates a 5-pin digital serial interface to connect it to an AC'97 controller. The AC link is a bidirectional, fixed rate (48kHz) serial PCM digital stream. It handles multiple input and output audio streams, as well as control register access using a time division multiplexing (TDM) scheme. The AC link architecture divides each audio frame into 12 output and 12 input data streams, each with 20-bit sampling resolution. The DAC and ADC resolution of the AK4543 is 18 bits. Data streams currently defined by the AC'97 specification include:

Synchronization, fixed at 48 kHz, is obtained by dividing by the serial bit clock (bit clock). The bit clock, fixed at 12.288MHz, provides the necessary clock granularity to support 12, 20 bit outbound and inbound time slots. AC link serial data is transferred on every rising edge of the bit clock. The receiver for AC link data, the AK4543 for output data, and the AC'97 controller for input data, sample each serial bit on the falling edge of the bit clock.

The AK4543 outputs bit CLK when ID1# and ID0# are assigned to the main codec by codec ID configuration. On the other hand, the AK4543 receives BIT_CLK when assigned as a secondary codec from the master.

The AC link protocol provides a special 16-bit time slot (slot 0), where each bit conveys a valid label for its corresponding time slot within the current audio frame. A "1" in a given bit position of slot 0 indicates that the corresponding slot within the current audio frame has been allocated to the data stream and contains valid data. If a slot is "marked" as invalid, it is the responsibility of the data source (AK4543 for the input stream, AC'97 controller for the output stream) to fill all bit positions with 0s during the active time of that slot.

At the beginning of each audio frame, synchronization is maintained for the total duration of the 16-bit clock. The portion of the audio frame with a high degree of synchronization is defined as the "marker phase". The rest of the audio frame with sync low is defined as the "data phase".

Note that the SDATA_OUT and SDATA_IN data are delayed by one bit clock because the AC'97 controller causes the sync signal to be high on the rising edge of the bit clock in the start frame.

The "output" flow indicates the direction from the AC'97 controller to the AK4543, and the "input" flow indicates the direction from the AK4543 to the AC'97 controller. All sentences in small italics below refer to the AC'97 component specification.

The AC link protocol recognizes 13 data slots per frame. The sync frequency is fixed at 48kHz. Only slot 0 (marking phase) is 16 bits, all other slots are 20 bits long. These slots are explained in later chapters.

AC Link Audio Output Frame (SDATA_-OUT)

a), slot 0

AK4543 checks bit 15 (valid frame bit). Note that when the valid frame bits are '1', at least one of bits 14-6 (slot 19) or bits 1-0 must be valid, bits 5-2 will be '0' and should be ignored.

If bit15 is "0", the AK4543 ignores all the following information in the frame.

The AK4543 then checks the validity of each bit in the marking phase (slot 0).

If each bit is "0", the AK4543 will ignore the slot indicated by "0". On the other hand, if every bit is "1", the slot is valid.

All bits in slot10-12 (bit5-3) are "0" and bit2 is also "0".

The AK4543 monitors bits 1 and 0, which are the codec ID configuration bits used in several codec implementations. These bits are used to identify which codec to send the frame data to.

When Codec ID Configuration bits 1 and 0 set by the Codec ID Configuration 45/46 bundled pins (Codec ID0# and ID1#) are set to zero (00), the frame is for the primary codec. And when the codec ID configuration bits 1 and 0 are set to a non-zero value (01, 10, or 11), the frame is used for the secondary codec.

A new audio output frame begins with a synchronized low-to-high transition. Synchronization is synchronized to the rising edge of the bit clock. On the following falling edge of BIT_CLK, the AK4543 samples the SYNC assertion. This falling edge marks the beginning of both sides of the AC link becoming aware of a new audio frame. On the next bit clock rise, the AC'97 controller transitions the SDATA output to the first bit position of slot 0 (the valid frame bit). Each new bit position is presented to the AC link on the rising edge of the bit clock and subsequently sampled by the AK4543 on the falling edge of the bit clock. This sequence ensures that data transitions and subsequent sampling points of incoming and outgoing data streams are time-aligned.

Data should first be sent to the AC'97 codec with MSB on the pin labeled SDATA.

The table below shows how bits s14 and 13 relate to read/write operations depending on the codec ID configuration.

b), Slot1: command address port

Slot1 gives the address of the command data, which is given in slot 2. The AK4543 has 20 valid registers with 16-bit data. See page 17 (see AC'97 register diagram).

Bit 19: Read/Write Command 1=read, 0=write

Bits 18:12 control register index (see "AC'97 Register Map" for details) Bits 11:0 are reserved ("0")

Bit 18 corresponds to the most significant bit of the index register address.

AK4543 ignores bits from 11th to 0th. These bits are reserved for future enhancements and must be filled with 0s by the AC'97 controller.

c), Slot2: command data port

Bits 19:4 control register write data (if bit 19 of slot 1 is "1", all bits 19:4 should be "0") Bits 3:0 reserved ("0")

If bit19 in slot1 is "0", it is a write command, AC'97 controller must output command data port data in slot 2 of the same frame. If bit19 in slot1 is "1", the AK4543 will ignore any command data port data in slot2.

Bit 19 corresponds to bit D15 of the mixer register value.

d), Slot3 PCM playback left channel (18 bits)

In the case of codec ID1:codec ID0=0:0 or 0:1, the AK4543 uses the playback (DAC) data format in slot3 as the left channel.

The playback data format is 18bits MSB first 2's complement. AC'97 controllers should fill bits 1-0 with "0". If the valid bit in slot 0 (slot3) is invalid ("0"), the AK4543 interprets the data as all "0"s.

Bit19:2 Playback data

Bit 1:0 "0"

e), Slot4 PCM playback right channel (18-bit)

In the case of codec ID1:codec ID0=0:0 or 0:1, the AK4543 uses the playback (DAC) data format in slot4 of the right channel. The playback data format is MSB first. The data format is 18-bit 2's complement. AC'97 controllers should fill bits 1-0 with "0". If a valid bit in slot 0 (slot 4) is invalid ("0"), the AK4543 interprets the data as all "0"s.

Bit19:2 Playback data

Bit 1:0 "0"

f), Slot5 is not used in AK4543

The AK4543 will ignore padding in this slot.

g), Slot6 PCM playback left channel (18 bit)

In the case of codec ID1:codec ID0=1:1, the AK4543 uses the playback (DAC) data in slot 6 of the left channel.

The playback data format is 18bits MSB first 2's complement. The AC'97 controller should fill bits 1-0 with "0". If the valid bit in slot 0 (slot6) is invalid ("0"), the AK4543 interprets the data as all "0"s.

Bit19:2 Playback data

Bit 1:0 "0"

h), Slot7 PCM playback left channel (18 bit)

In the case of codec ID1:codec ID0=1:0, the AK4543 uses the playback (DAC) data in slot7 as the left channel.

The playback data format is 18bits MSB first 2's complement. The AC'97 controller should fill bits 1-0 with "0". If the valid bit in slot 0 (slot7) is invalid ("0"), the AK4543 interprets the data as all "0"s.

Bit19:2 Playback data

Bit 1:0 "0"

i), Slot8 PCM playback right channel (18 bit)

In the case of codec ID1:codec ID0=1:0, the AK4543 uses the playback (DAC) data in slot8 as the right channel.

The playback data format is 18bits MSB first 2's complement. The AC'97 controller should fill bits 1-0 with "0". If the valid bit in slot 0 (slot8) is invalid ("0"), the AK4543 interprets the data as all "0"s.

Bit19:2 Playback data

Bit 1:0 "0"

j), Slot9 PCM playback right channel (18 bit)

In the case of codec ID1:codec ID0=1:1, the AK4543 uses the playback (DAC) data in slot 9 for the right channel.

The playback data format is 18bits MSB first 2's complement. The AC'97 controller should fill bits 1-0 with "0". If the valid bit in slot 0 (slot9) is invalid ("0"), the AK4543 interprets the data as all "0"s.

Bit19:2 Playback data

Bit 1:0 "0"

k), slots 10-12 are not used in AK4543

The AK4543 will ignore data filled in these data slots.

AC Link Input Frame (SDATA_-IN)

Each AC link frame consists of a 16-bit tag phase and 12 20-bit slots for data and control. a) slow

Slot0 is a special frame consisting of 16 bits. Slot0 is also known as the "marking phase". The AK4543 supports bits 15-11 and bits 1-0. Each bit represents "1" = valid (normal operation) or ready, "0" = invalid (abnormal operation) or not ready.

The AK4543 works fine if the first bit in slot 0 is valid. three. AC'97 controllers should ignore the following bits in slot 0 and all other slots. If the 'Codec Ready' bit is invalid, the following bits and the remaining slots are '0'

Bit 14 indicates that the slot 1 (status address) output is valid or invalid. Bit 13 indicates that slot 2 (status data) is valid or invalid.

The table below shows the relationship between bits 14, 13 and each state of the AK4543.

Bit12 indicates that the output of slot 3 (PCM (ADC) on the left) is valid or invalid. Bit 11 indicates that the output of slot 4 (PCM (ADC) on the left) is valid or invalid. Bits 10-0 are filled with "0".

A new audio input frame begins with a synchronized low-to-high transition. Synchronization is synchronized to the rising edge of the bit clock. On the following falling edge of BIT_CLK, the AK4543 samples the SYNC assertion. This falling edge marks the beginning of both sides of the AC link becoming aware of a new audio frame. On the next rise of bit CLK, the AK4543 turns SDATA into the first position of slot 0 ("codec ready" bit). Each new bit position is presented to the AC link on the rising edge of the bit clock and subsequently sampled by the AC'97 controller on the next falling edge of the bit clock. This sequence ensures that data transitions and subsequent sampling points of incoming and outgoing data streams are time-aligned.

b), Slot1 state address port

The stream of audio input frame slot1 echoes the control register index of the data to be returned in slot2 for historical reference. (Assuming that slots1 valid bits and slot2 valid bits in slot0 have been marked as "valid" by AK4543).

When AC'97 is not ready for normal operation, the output bits are not specified in this document and should be considered invalid.

This address shows the register index of the returned data in slot2.

This address port is a copy of slot1 of the output frame, and the index address input to SDATA_OUT is looped back to the AC'97 controller through SDATA_IN. This allows the controller to ensure that the correct data is being received by the AK4543. c) Slot2: The command address of the state data port output stream The state data addressed by the port is output through SDATA_ in the pin. Bit19:4 Control register read data (content of index address in slot 1) Bit3:0 "0"

Note that the address of the status data port data is consistent with the status address port data of slot 1 in the same frame. If the AC'97 controller issues a read operation in frame N, the status data port data is output through SDATA_ in frame N+1. Note that data is only available once in this frame, the following frames are invalid if another read operation is not issued.

d), Slot3: PCM records the left channel

Record (ADC) data format is 18bits MSB first 2's complement. Ignore the lower 2 bits of the frame. If the ADC block is powered down, the slot 3 valid bit in slot 0 is invalid ("0") and the data is the same as all "0"s.

Bit19:2 Audio ADC left channel output

Bit 1:0 "0"

e), Slot4: PCM records the right channel

Record (ADC) data format is 18bits MSB first 2's complement. Ignore the lower 2 bits of the frame. If the ADC block is powered down, the slot 4 valid bit in slot 0 is invalid ("0") and the data is the same as all "0"s.

Bit19:2 Audio ADC right channel output

Bit 1:0 "0"

f), Slot5: modem line codec

The AK4543 does not contain a modem codec, all bits are filled with "0" in this slot.

Bit 19:0 "0"

g), Slot6: microphone recording data

The AK4543 does not contain a third ADC for the microphone, all bits are filled with "0" in this slot.

Bit 19:0 "0"

h), Slots7-12 are reserved for future enhancements

Bit 19:0 "0"

AC'97 Registration Map

Each register is a 16-bit word.

Note: If the controller reads an unused or invalid register address, the AK4543 outputs "valid" 0000h.

reset register (index 00h)

When any value is written to this register, all registers in the AK4543 except register "26h" power down control/status register will be reset to default value. The value of this register has not changed.

Reading this register will return "2D50h", which consists of the ID code of the part, the code of the 3D enhancement type,

18-bit ADC/DAC resolution, and a code for true line-level output.

*Settings D14–D10 "01011" indicate AKM 3D enhancements, registered in the Audio Codec 97 Component Specification (versions 1.03 and 2.1).

*Set D8 "1" for 18-bit ADC resolution and D6 "1" for DAC resolution.

*Setting D4 "1" means that the volume control (index 04h) supports true line level output.

Play master volume register (index 02h, 06h) and LINVL (solid line level output) volume register (index 04h)

The table below shows the relationship between bits and attenuation values in 1.5dB steps. The AK4543 has a range of 0dB to -46.5dB. The AK4543 does not support the optional MX5 bit.

The AK4543 series detects when the MX5 is set and sets all 5 LSBs to 1s. Example: When the driver writes "01xxxxx", the AK4543 interprets it as "0011111". When reading this register, the return value is "0011111".

PC buzzer register (index 0Ah)

The following table shows the relationship between bits and attenuation values. The attenuation step is -3dB and the range is 0 to -45dB. By default, the AK4543's PC beeps are mute off.

When the AK4543 is in reset state (reset to "L"), the PC beep is sent directly to the L&R line output. This way, users can hear the power-on self-test (POST) codes when there is a hardware problem with the computer. After "H" changes to "H" after reset, direct computer beep paging will be turned off.

Power Down Control/Status Register (Index 26h)

Bits sd0 to D3 are read-only status bits. Any write to these bits will not affect the operation of the AK4543. These bits are used as status bits for subsections of the AC'97 codec. "1" indicates that the subsection of the AK4543 is "ready" or capable of executing in normal operation.

Power Management/Low Power Mode

The AK4543 is capable of operating in multiple reduced power modes without requiring activity. The power down state is controlled by the power down register (26h). There are 8 separate power down commands. The different modes are shown in the table below. Since the AK4543 works in static mode, the registers will not lose their value even if the main clock is stopped only at power up.

From normal operation, perform sequential writes to the power down registers to shut down subsections of the AK4543 one at a time. After closing all devices, a final write (PR4) can be performed to close the AC'97 digital interface (AC link). The part will remain in sleep mode with all its registers retaining their static values. To wake up, the AC'97 controller will send a pulse on the sync line to issue a warm reset. This will restart the AK4543 digital (reset PR4 to zero). The AK4543 can also be woken up by cold reset. A cold reset will result in the loss of register values because a cold reset will set the registers to their default state. When a subsection is powered back on, the power down control/status register (index 26h) should be read to verify that the section is ready (i.e. stable) before attempting any operations that require its normal operation.

The figure below shows an example of the process to complete the power-down/power-up of the AK4543.

When the PR3 bit is set to '1', the ADC, DAC, mixer, true line output and VREF will be powered down even if any PRx bit is '0'. When the PR3 bit is reset to "0", the AK4543 restores the previous state by referencing the PRx bit. In this case, the AK4543 outputs "0" (invalid) for the corresponding slot-x valid bit in slot 0 until the corresponding block of the AK4543 operates in normal operation.

Setting the PR4 bit causes the AK4543 to power down mode and the AK4543's AC link to shut down. In this case, when a warm reset is performed, the PR4 bit is cleared and the AC link is reactivated. A cold reset is issued and the AK4543 returns to the operation of the default register settings.

Additionally, setting the PR5 bit causes the AK4543's power-down mode and the AK4543's internal clock to stop. In this case, when the warm reset is complete, the PR5 bit is cleared to 0 and the internal clock and AC link are reactivated. When performing a cold reset, the AK4543 is set to operate with the default register settings, with no active power down mode. The next figure illustrates the state when all mixers should use the static volume settings contained in their associated registers. Use this option when the user is playing a CD (or external line input source) to the speakers via the AC'97 codec, but most systems are in low power mode. This process follows the previous steps, except that the analog mixer is never turned off.

Power-Down/Power-Up Sequence for Multiple Codec Configurations

There can be up to 4 codecs on an extended AC link. Multiple codec AC chaining implementations must run on a common bit clock. The primary codec generates the primary AC link bit clock for the AC'97 digital controller and any secondary codecs. In any system using multiple codecs, the AK4543 can be used as a master or slave.

There is no restriction on setting PR0 (ADC), PR1 (DAC), PR2 (mixer), PR6 (LNLVL_-OUT) and PR7 (EAPD) to "1" or "0" in the case of multiple codecs.

AC link power down (PR "4") and Vref, as recommended in AC'97 specification version 2.1, is not recommended for power down (PR5="1") in multi-codec configuration in order to continue to the secondary codec Provides a bit clock.

overall stability

Activate test mode

AC'97 has two test modes. One for ATE in-circuit testing and the other for vendor specific testing. If the SDATA#u output is sampled high on the trailing edge of reset, the AC'97 enters ATE in circuit test mode regardless of the sync signal (high or low). If AC'97 enters AKM test mode when coming out of reset, SDATA_out is low if sync is high. Under standard operating conditions, these conditions would never occur.

Regardless of the test mode, the AC'97 controller must issue a "cold" reset to restore normal operation of the AC'97 codec.

Test mode function

ATE circuit test mode

When the AC'97 is in ATE test mode, its digital AC link outputs (ie BIT_CLK and SDATA_in) are driven to a high impedance state. This allows ATE in-circuit testing of AC'97 controllers.

1. Ground and power decoupling

AVdd1 and AVdd2 should be connected and derived from the same AVdd. DVdd1 and DVdd2 should also be connected to and derived from the same DVdd. Analog ground and digital ground should be connected close to where the power supply is connected to the printed circuit board. Decoupling capacitors should be placed as close as possible to the AK4543, small value ceramic capacitors are closest, and the most important capacitors are placed on the Vref and AVdd pins.

The AK4543 does not require a specific power sequence.

2. On-chip voltage reference

The on-chip voltage reference is output on VRADDA, and the Vref pin is used for decoupling. An electrolytic capacitor less than 10uF is connected in parallel with a 0.1uf ceramic capacitor to eliminate the effects of high frequency noise. No-load current can be drawn from the VRADDA or Vref pins. All signals, especially the clock, should be kept away from the VRADDA and Vref pins to avoid unnecessary coupling to the delta-sigma modulator.

3. Codec ID configuration pins 45, 46.

4. Log input

Since many analog levels can be as high as 2VRMS, the circuit shown below can be used to attenuate analog inputs by 2VRMS to 1VRMS, which is the maximum voltage allowed on all stereo line level inputs.

5. Select CMOS (48 pins)

When a DVD that supports CMOS levels is 3.3V, pin 48 must be open.

Pin 48 must be DGND, as shown in the picture below, if the DVD's TTL level is 5.0V, this selection must be fixed before powering on the AK4543.

6. PC beeps

If PC beeps are not used, this input pin should be NC (open) or connected to analog ground via a capacitor. In this case, the register of PC Beep (04h, D15) should be set to mute "1". (Note that the default setting for PC_BEEP is to mute off.) Also, when PC_BEEP is connected to analog ground via capacitance, it is recommended that PC_BEEP be separated from other unused input pins.