feature

256 positions; 10 km, 100 km, 1 m; low temperature 30 ppm/C; mid-scale built-in power supply; single supply 2.7 V to 5.5 V or; dual supply 2.7 V for AC or bipolar operation; with readback capability I2C compatible interface; additional programmable logic outputs; independent shutdown function; extended temperature range –40°C to +105°C.

application

Multimedia, Video and Audio; Communications; Mechanical Potentiometer Replacement; Instrumentation: Gain, Offset Adjustment; Programmable Voltage Current Conversion; Line Impedance Matching.

General Instructions

The AD5241 /AD5242 offer single/dual channel, 256-position, digitally controlled variable resistor (VR) devices. These devices perform with potentiometers, trimmers or variable resistors. Each VR offers a fully programmable value of resistance between the A terminal and the wiper, or the B terminal and the wiper. For the AD5242, the fixed A to B terminal resistance is 10 kΩ, 100 kΩ, or 1 MΩ with 1% channel-to-channel matching tolerance. The nominal temperature coefficient for both parts is 30 ppm/degree Celsius.

Wiper position programming defaults to system mid-scale power on. After power up, the VR wiper position is programmed by an I2-compatible 2-wire serial data interface. Both parts have two additional programmable logic outputs enabling users to drive digital loads, logic gates, LED drivers and analog switches in the system.

The AD5241/AD5242 are available in surface mount (SOIC-14/-16) packages, and for ultra-compact solutions, TSSOP-14/-16 packages. All parts are guaranteed over the extended temperature range -40°C to +105°C. For 3-wire, SPI-compatible interface applications, see AD5200, AD5201, AD5203, AD5204, AD5206, AD5231*, AD5232*, AD5235*, AD7376, AD8400, AD8402, and AD8403 products.

operate

The AD5241/AD5242 provide a single/dual channel, 256-bit digitally controlled variable resistor (VR) device. The terms VR, RDAC, and programmable resistor are often used interchangeably to refer to digital potentiometers.

To program the virtual reality setup, see the Digital Interface section. Both parts have a built-in power-up preset that places the wipers in mid-scale when powered up, which simplifies fault recovery when powered up. In addition, closing the SHDN pin of the AD5241/AD5242 puts the RDAC in a near-zero power state with terminal A open and wiper W connected to terminal B, resulting in only leakage current consumption in the VR architecture. During shutdown, when the RDAC is inactive, the VR latch contents are maintained. The stored VR settings are applied to the RDAC when the part is returned from the closed state.

Variable Resistor Rheostat Operation Programming

The nominal resistances of the RDAC between terminals A and B are 10 kΩ, 100 kΩ, and 1 MΩ. The last two or three digits of the part number determine the nominal resistance value, eg 10 kΩ=10; 100 kΩ=100; 1 MΩ=1 M. The nominal resistance (RAB) of the VR has 256 contact points, which are contacted by the wiper terminal and the B terminal. The 8-bit data in the RDAC latch is decoded to select one of 256 possible settings. Assuming 10 kΩ parts are used; with data 00H, the first connection to the wiper starts from the B terminal. Since the wiper contact resistance is 60Ω, this connection creates a minimum resistance of 60Ω between terminals W and B. The second connection is the first tap point of 99Ω (RW B=RAB/256+RW=39+60) corresponding to data 01H. The third connection is the next tap point of 138Ω (39×2+60) representing data 02H, and so on. With each additional LSB data value, the wipers move up the resistor ladder until the last tap point reaches 10021Ω [RAB – 1 LSB+RW]. Figure 4 shows a simplified diagram of an equivalent RDAC circuit where the last resistor string will not be accessible; therefore, the nominal resistance at full scale will be reduced by 1LSB, except for the wiper resistance.

The general equation for determining the digital programming resistance between W and B is:

where: D is the decimal equivalent of the binary code between 0 and 255, loaded in the 8-bit RDAC register. RAB is the nominal end-to-end resistance. RW is the wiper resistance internal switch contributed by the on-resistance.

Likewise, if RAB = 10 kΩ, and the A terminal can open the circuit or be connected to W, the following output resistance of RWB will set the following RDAC latch code.

Note that there is a finite wiper resistance of 60Ω under zero-scale conditions. It should be noted that in this state, the current between W and B is limited to a maximum current of no more than ±20 mA. Failure to do so may result in degradation or damage to the internal switch contacts.

Similar to the mechanical potentiometer, the RDAC resistance between wiper W and terminal A also produces a digitally controlled resistance RWA. When using these terminals, the B terminal can be open or connected to the wiper terminal. Setting the resistance value of RWA starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general equation for this operation is:

If RAB=10 kΩ, the B terminal may be open or connected to W. The following output resistors, RWA, will be set for the following RDAC latch codes.

The nominal resistance RAB of the AD5242 is typically distributed within ±1% from one channel to the other. Equipment-to-equipment matching is process batch dependent and may vary by ±30%. Since the resistive element is processed using thin film technology, the variation of RAB with temperature does not exceed a temperature coefficient of 30ppm/°C.

Program Potentiometer Divider Voltage Output Operation

Digital potentiometers easily produce output voltages at wiper to B and wiper to A proportional to the input voltage at A to B. Unlike the polarity of VDD-VSS (which must be positive), if VSS is powered by a negative supply, the voltages at AB, WA, and WB can be of any polarity.

If you ignore the effect of the wiper resistance on the approximation, connecting the A terminal to 5 V and the B terminal to ground yields a Wito to B output voltage below 0 to 1 LSB, less than 5 V. The voltage of each LSB is equal to the voltage applied on terminal AB divided by the 256 positions of the potentiometer divider. Since the AD5241/AD5242 can be powered by dual supplies, the general equation that defines the output voltage at VW with respect to ground for any valid input voltage applied to terminals A and B is:

can be simplified to:

where D is the decimal equivalent of the binary code between 0 and 255 loaded in the 8-bit RDAC register.

For a more precise calculation including the effect of wiper resistance, VW can be found as:

where RWB(D) and RWA(D) can be obtained from Equations 1 and 2.

Operation of the digital potentiometer in voltage divider mode results in more accurate overtemperature operation. Unlike the varistor mode, the output voltage depends on the ratio of the internal resistors RWA and RWB, not the absolute value; therefore, the temperature drift is reduced to 5ppm/°C.

Digital interface 2-wire serial bus

The AD5241/AD5242 are controlled via an I2C compatible serial bus. The RDAC is connected to this bus as a slave device.

Referring to Figure 2 and Figure 3, the first byte of the AD5241/AD5242 is the slave address byte. It has a 7-bit slave address and an R/W bit. The 5 msb is 01011, the next two bits are determined by the state of the AD0 and AD1 pins of the device. AD0 and AD1 allow the user to use up to four of these devices on a single bus.

The 2-wire I2C serial bus protocol operates as follows:

1. The host initiates data transfer by establishing a START condition, that is, when SCL is high, a high-to-low transition occurs on the SDA line (Figure 2). The following bytes are the slave address byte, frame 1, consisting of 7 bits of the slave address and an R/W bit (this bit determines whether the slave device reads or writes data).

The slave whose address corresponds to the transmit address will respond by pulling the SDA line low during the ninth clock pulse (this is called the acknowledge bit). During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial registers. If the R/W bit is high, the master will read from the slave. If the R/W bit is low, the master will write to the slave.

2. The write operation contains one extra instruction byte than the read operation. The command byte frame 2 in write mode follows the slave address byte. The MSB of the instruction byte marked A/B is the RDAC subaddress selection. "Low" selects RDAC1, and "High" selects RDAC2 of the dual-channel AD5242. Set A/B of AD5241 low. The second MSB, RS, is the midscale reset. A logic high on this bit moves the wiper of the selected RDAC to the center tap, where RWA=RWB. The third MSB, SD, is an off bit. A logic high on SD results in an open circuit of RDAC on terminal A while the wiper is shorted to terminal B. This operation produces almost 0Ω in rheostat mode and almost 0 V in potentiometer mode. This SD bit has the same function as SHDN except that the SHDN Pin responds to active low. The next two are O2 and O1. They are additional programmable logic outputs that the user can use to drive other digital loads, logic gates, LED drivers, analog switches, etc. The three LSBs don't care. See Figure 2.

3. After confirming the command byte, the last byte in the write mode is the data byte, the 3rd frame. Data is transferred over the serial bus in a sequence of 9 clock pulses (8 data bits followed by an acknowledge bit). A transition on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (Figure 2).

4. Unlike the write mode, the data byte follows immediately after the 2nd frame is confirmed from the address byte in read mode. Data is transferred on the serial bus in a sequence of 9 clock pulses (slightly different from write mode with 8 data bits and 1 no-acknowledge logic bit in read mode). Likewise, the transition of the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. See Figure 3.

5. When all data bits have been read or written, the host will establish a stop condition. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 2). In read mode, the master will issue a "no" acknowledgment on the ninth clock pulse (ie, the SDA line is held high). The master will then drive the SDA line low before the tenth clock pulse, which goes high to establish a stop condition (see Figure 3).

The Repeat Write feature gives the user the flexibility to update the RDAC output multiple times after addressing and instructing the part once. During a write cycle, each data byte will update the RDAC output. For example, the RDAC output will be updated after the RDAC acknowledges its slave address and instruction byte. If another byte is written to the RDAC while it is still being addressed to a specific slave with the same instruction, that byte will update the output of the selected slave. If a different command is required, the write mode must start a whole new sequence and transmit the new slave address, command and data bytes again. Likewise, the repeated read function of the RDAC is also allowed.

Read back RDAC value

Specific to the AD5242 dual channel device, the channel of interest is the channel previously selected in write mode. Also, to read two RDAC values consecutively, the user must perform two write-read cycles. For example, the user can first specify the RDAC1 subaddress in write mode (no need to issue a data byte and stop condition), then change to read mode and read the RDAC1 value. To continue reading the RDAC2 value, the user must switch back to write mode and specify the subaddress, then switch to read mode again and read the RDAC2 value. This operation does not require issuing a write mode data byte or a first stop condition. Users should refer to Figure 2 and Figure 3 for programming formats.

Multiple devices on a bus

Figure 5 shows four AD5242 devices on the same serial bus. Due to the different states of the AD0 and AD1 pins, each pin has a different slave address. This allows each RDAC to independently write to or read from each device. The master output bus driver is an open-drain drop-down menu in a fully I2C-compatible interface. Note that the device will only be properly addressed if the bit information for AD0 and AD1 in the slave address byte matches the logic input at the AD0 and AD1 pins for that particular device.

Level Shifting for Bidirectional Interfaces

While most older systems can operate at one voltage, new components can be optimized at another. When they operate on the same signal at two different voltages, a proper method of level shifting is required. For example, a 3.3V E2PROM can be used to interface with a 5V digital potentiometer. To achieve bidirectional communication, a level shifting scheme is required so that the settings of the digital potentiometers can be stored to and retrieved from the E2PROM. Figure 6 shows one of these techniques. M1 and M2 can be N-Ch FETs 2N7002 or low threshold FDV301N if VDD is below 2.5v.

Additional programmable logic outputs

The AD5241/AD5242 have additional programmable logic outputs O1 and O2 that can be used to drive digital loads, analog switches, and logic gates. They can also act as a self-contained shutdown for a preset logic 0 function (explained later). O1 and O2 default to logic 0 during power up. In write mode, the logic states of O1 and O2 can be programmed in frame 2 (see Figure 2). Figure 7 shows the output stage of O1, which employs large P and N channel mosfets in a push-pull configuration. As shown, the outputs will be equal to VDD or VSS, and these logic outputs have enough current drive capability to drive mA loads.

Users can also activate O1 and O2 in three different ways without affecting the wiper settings.

1. Start, from the address byte, confirm, specify the instruction bytes of O1 and O2, confirm, stop.

2. Complete the write cycle, stop, then start, slave address byte, confirm, specify the instruction bytes of O1 and O2, confirm, stop.

3. Do not complete the write cycle by not issuing Stop, thenStart, Slave Address Byte, Acknowledge, the instruction byte specifies O1 and O2, Acknowledge, Stop.

All digital inputs are protected with series input resistors and parallel Zener ESD structures, as shown in Figure 9. This applies to the digital input pins SDA, SCL and SHDN.

Independent shutdown function

Shutdown can be activated by swiping on the SHDN pin or by programming the SD bit in the write mode command byte. Furthermore, shutdown can even be achieved with device digital outputs, as shown in Figure 8. In this configuration, the device will shut down during power up, but the user is allowed to program the device. Therefore, when O1 is programmed high, the device will exit from shutdown mode and respond to the new setting. This self-contained shutdown allows absolute shutdown during power-up, which is critical in hazardous environments, without adding additional components.

test circuit

Test circuits 1 through 9 define the test conditions used in the product specification sheet.