feature

330msps throughput; three 8-bit DACs; RS-343A-/RS-170 compatible outputs; complementary outputs; DAC output current range: 2.0 mA to 26.5 mA; TTL compatible inputs; internal reference ( 1.235 V); Single-supply +5 V/+3.3 V operation; 48-lead LQFP and LFCSP; low power consumption (30 mW min at 3V); low power standby mode (6MW typical at 3V); industrial temperature range (-40°C to + 85°C); RoHS compliant software package; suitable for automotive applications.

application

Digital video systems; high-resolution color graphics; digital radio modulation; image processing; instrumentation; video signal reconstruction; automotive infotainment units.

General Instructions

The ADV7125 (ADV) is a triple high-speed, digital-to-analog converter-on-a-chip (DAC). It consists of a three-part high-speed 8-bit video DAC standard TTL input interface with complementary outputs and a high-impedance analog output current source.

The ADV7125 has three independent 8-bit wide input ports. A single +5V/+3.3V supply and clock are required for proper operation of the device. The ADV7125 has additional video control signals, composite sync and blank, and a power saving mode.

The ADV7125 is fabricated on a 5V CMOS process. Its monolithic CMOS structure ensures greater functionality and lower power consumption. The ADV7125 is available in 48-lead LQFP and 48-lead LFCSP packages.

Product Highlights

1. 330msps (3.3v only) throughput.

2. Guaranteed to be monotonic to 8 bits.

3. Compatible with a variety of high-resolution color graphics systems, including RS-343A and RS-170.

the term

Blanking level

The level that separates the sync portion of the waveform from the video portion. Often called the front porch or back porch. At 0 IRE units, is the level at which the picture tube is turned off, resulting in the darkest image possible.

Color video (RGB)

This refers to the technique of combining the three primary colors of red, green and blue to produce a color picture in the usual spectral range. In an RGB monitor, three DACs are required, one for each color.

Sync signal (Sync)

The position of the composite video signal that synchronizes the scanning process.

grayscale

The discrete levels of a video signal between a reference black level and a reference white level. The 8-bit DAC contains 256 different levels.

Raster scan

The most basic method of scanning a CRT one line at a time to generate and display an image.

reference black level

The maximum negative polarity amplitude of the video signal.

reference white level

Maximum positive polarity amplitude of the video signal.

Sync level

The peak level of the sync signal.

video signal

The portion of the composite video signal that varies in gray level between reference white and reference black. Also known as the image signal, this is the part that can be visually observed.

Circuit Description and Operation

The ADV7125 contains three 8-bit DACs with three input channels, each containing an 8-bit register. The device also integrates a reference amplifier. CRT control functions, blank and sync, are integrated on the ADV7125.

digital input

There are 24 bits of pixel data (color information), R0 to R7, G0 to G7, B0 to B7, latched into the device on the rising edge of each clock cycle. This data is presented to three 8-bit DACs, which are then converted into three analog (RGB) output waveforms (see Figure 6).

The ADV7125 has two additional control signals that are locked to the analog video output in a similar fashion. Blank and sync are latched on the rising edge of the clock to maintain synchronization with the pixel data stream.

The Blank and Sync function allows these video sync signals to be encoded onto the RGB video output. This is achieved by adding appropriately weighted current sources to the analog outputs, determined by the logic levels on the blank and sync digital inputs.

Figure 7 shows the analog output RGB video waveform of the ADV7125. The effect of sync and blank on analog video waveforms is illustrated.

Table 8 details the resulting effect on the analog output

blank and sync.

All of these digital inputs are designated to accept TTL logic levels.

clock input

The clock input to the ADV7125 is typically the pixel clock rate of the system. It is also called point rate. The dot rate and required clock frequency are determined by the screen resolution according to the following equation:

The horizontal plane is the number of pixels per row.

Vertical resolution is the number of lines per frame.

The refresh rate is the horizontal scan rate. This is the rate at which the screen must be refreshed, typically 60 Hz for non-interlaced systems and 30 Hz for interlaced systems. The backtracking factor is the total blank time factor. This allows for display blanks for some fraction (eg, 0.8) of the total duration of each frame. Therefore, for a graphics system with a resolution of 1024 × 1024, a refresh rate of 60 Hz, and a backtracking factor of 0.8, Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz, and the required clock frequency is 78.6 MHz. All video data and control inputs are latched into the ADV7125 on the rising edge of the clock, as described earlier in the Digital Inputs section. It is recommended that the clock input of the ADV7125 be driven by a TTL buffer such as a 74F244.

Video synchronization and control

The ADV7125 has a composite synchronization (sync) input control. Many graphics processors and CRT controllers can generate horizontal sync (HSYNC), vertical sync (VSYNC), and composite sync.

In graphics systems that do not automatically generate composite sync signals, some additional logic is included to generate composite sync signals. The sync current is internally connected directly to the IOG output, thereby encoding video sync information onto the green video channel. If the synchronization information does not need to be encoded onto the ADV7125, the synchronization input should be tied to logic low.

reference input

The ADV7125 contains an on-board voltage reference. The VREF pin connections should be as shown in Figure 12.

A resistor RSET, connected between the RSET pin and GND, determines the amplitude of the output video level according to Equation 1 and Equation 2 of the ADV7125.

Equation 1 applies only to the ADV7125 and is used when synchronization is in progress. Equation 1 is similar to Equation 2 if the sync is not encoded on the green channel.

The analog output video level can be precisely adjusted using a variable RSET value. Using a fixed 560Ω RSET resistor produces the analog output levels referenced in the Specifications chapter. These values typically correspond to RS-343A video waveform values, as shown in Figure 7.

data acquisition card

The ADV7125 contains three matched 8-bit DACs. The DAC adopts an advanced, high-speed, segmented structure design. The bit current corresponding to each digital input is routed through a complex decoding scheme to either the analog output (bit=1) or GND (bit=0). Because all of these circuits are on a monolithic device, the matching between the three DACs is optimized. In addition to matching, using the same current source in a monolithic design also guarantees monotonicity and low faults. On-board op amps stabilize full-scale output current against temperature and power supply variations.

Analog output

The ADV7125 has three analog outputs, one for the red, green, and blue video signals.

The red, green, and blue analog outputs of the ADV7125 are high impedance current sources. Each of the three RGB current outputs is capable of directly driving a 37.5Ω load, such as a double-ended 75Ω coaxial cable. Figure 8 shows the desired configuration for each of the three RGB outputs connected to a double-terminated 75Ω load. This unit produces RS-343A video output voltage levels on a 75Ω display.

A suggested method for driving RS-170 video levels into a 75Ω monitor is shown in Figure 9. The output current level of the DACs remains the same, but the source resistance Z on the 3 DACs increases from 75Ω to 150Ω.

For more details on load termination for various output configurations, including RS-343A and RS-170, see AN-205 Application Note, Video Formats and Required Load Termination.

Figure 7 shows Figure 8 with the three RGB outputs driving a double-terminated 75Ω load. As well as grayscale levels (from black to white levels), Figure 7 also shows that SYNC and ADV7125 are empty. These control inputs add appropriately weighted currents to the analog outputs, resulting in the specific output level requirements of the video application.

Table 8 details how the sync and blank inputs modify the output level.

Grayscale operation

The ADV7125 can be used in standalone, grayscale (monochrome) or composite video applications (ie, only one channel is used for video information). Any of the three channels, red, green or blue, can be used to input digital video data. The two unused video data channels should be tied to logic 0. Unused analog outputs should be loaded with the same load as the channel used, i.e., if the red channel is used, IOR is terminated with a double-ended 75Ω load (37.5Ω), and IOB and IOG are terminated with 37.5Ω resistors (see Figure 10).

video output buffer

The ADV7125 is specified for driving transmission line loads. The analog output configuration to drive this load is described in the Analog Outputs section and illustrated in Figure 11. However, in some applications it may be necessary to drive long transmission line cable lengths. Cable lengths longer than 10 meters will attenuate and distort high frequency analog output pulses. The addition of an output buffer compensates for some cable distortion. A buffer with a large full power bandwidth and gain between 2 and 4 is required. These buffers also need to be able to supply sufficient current across the entire output voltage swing. Analog devices produce a range of op amps suitable for this type of application. These include the AD843, AD844, AD847, and AD848 families of monolithic op amps. In very high frequency applications (80 MHz), the AD8061 is recommended. For more information on the line driver buffer circuit, see the relevant op amp data sheet.

In addition to RS-343A and RS-170, other video standards can be implemented using buffer amplifiers. Any desired video level can be obtained by changing the gain component of the buffer circuit.

PCB Layout Considerations

The ADV7125 is optimized to minimize radiated and conducted noise performance. To complement the excellent noise performance of the ADV7125, great attention must be paid to the PCB layout. Figure 12 shows the recommended connection diagram for the ADV7125.

On the ADV7125 power and ground lines, the layout should be optimized to minimize noise. This can be achieved by shielding the digital inputs and providing good decoupling. Shorten the lead length between the V and GND pin groups to minimize induced ringing.

A 4-layer printed circuit board with a single ground plane is recommended. Ground and power planes should separate the signal trace and solder side planes. Noise on the analog power plane can be further reduced by using multiple decoupling capacitors (see Figure 12). Best performance is obtained with 0.1µF and 0.01µF ceramic capacitors. Each V pin is individually separated from ground by placing the capacitors as close as possible to the device and keeping the capacitor leads as short as possible to minimize lead inductance. It is worth noting that although the ADV7125 includes circuitry to suppress power supply noise, this suppression decreases with frequency. If a high frequency switching power supply is used, close attention should be paid to reducing power supply noise. A DC power filter (Murata BNX002) provides EMI suppression between the switching power supply and the main PCB. Alternatively, consider using a 3-terminal voltage regulator.

digital signal interconnection

As much as possible, isolate the digital signal lines of the ADV7125 from the analog outputs and other analog circuits. Digital signal lines should not overlap analog power planes.

Due to the high clock frequencies used, long clock lines to the ADV7125 should be avoided to minimize noise pickup.

Connect any active pull-up termination resistors for the digital inputs to the regular PCB power plane (V), not the analog power plane.

Analog Signal Interconnect

Place the ADV7125 as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatches.

The video output signal should overlay the ground plane instead of the analog power plane to maximize high frequency power supply rejection.

For best performance, the analog output should have a resistance to ground of 75Ω (double-terminated 75Ω configuration). The termination resistors should be as close as possible to the ADV7125 to minimize reflections.

For additional information on PCB design, see AN-333 Application Note, Design and Layout of Video Graphics Systems to Reduce EMI.

Dimensions

automotive products

The ADV7125W model offers controlled manufacturing to support automotive quality and reliability demanding applications. Note that the specifications of these models may differ from commercial models; therefore, designers should carefully review the Specifications section of this data sheet. Only the automotive grade products shown are available for automotive applications. For specific product ordering information, please contact your local Analog Devices account representative and obtain specific vehicle reliability reports for these models.