feature

SNR = 57 dB @ 39 MHz analog input (-0.5 dBFS); low power; 190 mW at 65 MSPS; 285 mW at 105 MSPS; 30 mW power-down mode; 300 MHz analog bandwidth; on-chip reference and track/hold; 1 V pp or 2 V pp analog input range options; single 3.3 V supply operation (2.7 V-3.6 V); twos complement or offset data format options.

application

Battery-powered instruments; handheld hero telescopes; low-cost digital oscilloscopes; ultrasonic equipment; reverse path cables; broadband wireless; residential power line networks.

Product Description

The AD9214 is a 10-bit monolithic sampling analog-to-digital converter (ADC) with on-chip track-and-hold circuitry and optimized for low cost, low power, small size, and ease of use. The product has a slew rate of up to 105msps with excellent dynamic performance over the entire operating range. The ADC requires only a 3.3 V (2.7 V to 3.6 V) supply to provide an encoding clock for full performance operation. Not many systems require external reference or driver component applications. Digital outputs are TTL/CMOS compatible. A separate output power pin supports interfacing with 3.3V or 2.5V logic. The clock input is TTL/CMOS compatible. During a power outage, the power is reduced to 30 MW. Gain options allow support for 1 V pp or 2 V pp analog signal input swings. Manufactured on an advanced CMOS process, the AD9214 is offered in a 28-lead surface mount plastic package (28-SSOP) specified over the industrial temperature range (–40°C to +85°C).

Product Highlights

High performance Excellent AC performance from 65 ms to 105 MSPS. The signal-to-noise ratio is greater than 55 decibels by 58 decibels.

The low-power AD9214 consumes the power available in existing high-speed monolithic solutions at 285 MW. In sleep mode, the power is reduced to 30 MW.

The single-supply AD9214 simplifies system power design by using a single 3V supply. It also has a separate digital output driver power line to accommodate 2.5V logic families. Small Package The AD9214 is packaged in a 28-lead small surface mount plastic package (28-SSOP).

term analog bandwidth

Simulate the input frequency at which the spectral power of the fundamental frequency (determined by FFT analysis) is reduced by 3db.

Aperture delay

The delay between the 50% point of the rising edge of the encoded command and the instant the analog input is sampled.

Aperture uncertainty (jitter)

Sample-to-sample variation of aperture delay.

Differential analog input resistance

Input Capacitance and Differential Analog Input Impedance The actual and complex impedance measured at each analog input port. Measure resistance statically, measure capacitance and differential input impedance with a network analyzer.

Differential analog input voltage range

The peak-to-peak differential voltage that must be applied to the converter to produce a full-scale response. The peak differential voltage is calculated by looking at the voltage on one pin and then subtracting the voltage from the other pin, which is 180 degrees out of phase. The peak-to-peak difference is calculated by rotating the input phase by 180 degrees and taking the peak measurement again. The difference between the two peak measurements is then calculated.

Differential nonlinearity

Deviation of any code width from the ideal 1lsb step size.

significant digits

The effective number of bits (ENOB) is calculated from the measured SNR according to the following equation:

Code Pulse Width/Duty Cycle

Pulse width high is the minimum amount of time an encoded pulse remains in a logic "1" state to achieve rated performance; pulse width low is the minimum amount of time an encoded pulse remains in a low state. See the time meaning of changing tENCH in the text. These specifications define acceptable encoding duty cycles at a given clock rate.

Full-scale input power

Expressed in dBm. Calculate using the following formula:

gain error

Gain error is the difference between the ADC's measurement and the ideal full-scale input voltage range.

Harmonic Distortion, sec

The ratio of the rms signal amplitude to the rms value of the second harmonic component, expressed in dBc.

Harmonic Distortion, 3rd

The ratio of the rms signal amplitude to the rms value of the third harmonic component, expressed in dBc.

Integral nonlinearity

Deviation of the transfer function from the reference line measured in fractions of 1 lsb as determined by a least squares curve fit to the "best straight line".

Minimum conversion rate

The signal-to-noise ratio of the lowest analog signal frequency is below the guaranteed limit not exceeding the code rate of 3db.

maximum conversion rate

The encoding rate when performing the parametric test.

output propagation delay

The delay between the encoded and encoded differential crossing and the time when all output data bits are within valid logic levels.

Noise (applies to any range within the ADC)

where Z is the input impedance, FS is the device full scale at that frequency, SNR is the value for a particular input level, and Signal is the signal level within the ADC reported in dB below full scale. This value includes thermal noise and quantization noise.

power supply rejection ratio

Ratio of input offset voltage change to supply voltage change.

Signal to Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set to 0.5 dB below full scale) to the rms value of the sum of all other spectral components (including harmonics but excluding DC).

Signal-to-noise ratio (no harmonics)

The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and DC.

Spurious Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral components. Peak spurious components may or may not be harmonics. Can be reported in dBc (that is, decreases as signal level decreases) or dBFS (always relative to converter full scale).

Two-tone intermodulation distortion suppression

Ratio of the rms value of the input tone to the rms value of the worst third-order intermodulation product; expressed in dBc.

Two-tone SFDR

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be intermodulation distortion products. Can be reported in dBc (that is, decreases as signal level decreases) or dBFS (always relative to converter full scale).

worst other stimulus

The ratio of the rms signal amplitude to the rms value of the worst spurious components (excluding second and third harmonics) reported in dBc.

Transient response time

Transient response is defined as the time it takes for the ADC to regain the analog input after a transient from 10% above negative full scale to 10% below positive full scale.

Out of range recovery time

The out-of-range recovery time is the time it takes for the ADC to regain the analog input after transitioning from 10% above positive full scale to 10% above negative full scale or from 10% below negative full scale to 10% below positive full scale.

Equivalent Circuit

theory of operation

The AD9214 architecture is a bit/stage pipelined converter using switched capacitor technology. These stages determine 7 msbs and drive 3 bits of flash. Each stage provides sufficient overlap and error correction to optimize comparator accuracy. The input buffers are differential and both inputs are internally biased. This allows the most flexibility to use AC or DC and differential or single-ended input modes. The output scratch block aligns the data, performs error correction and feeds the data to the output buffer. The output buffers are powered by separate power supplies, allowing different logic families to be supported. During power down, the output goes into a high impedance state.

Apply AD9214 to encode AD9214

Any high-speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. The track/hold circuit is essentially a mixer. Any noise, distortion or timing jitter on the clock will combine with the desired signal at the A/D output. Therefore, great care has been taken in designing the coded input to the AD9214, and the user is advised to give corresponding consideration to the clock source. The encoded input is fully TTL/CMOS compatible and should normally be driven directly from a low jitter, crystal controlled TTL/CMOS oscillator.

The code input is internally biased, allowing the user to AC-couple in the clock signal. The cleanest clock source is usually a crystal oscillator that produces a pure sine wave. Figure 7 illustrates AC coupling of such a source to the encoded input.

Reference circuit

The reference circuit for the AD9214 is configured by REFSENSE (pin 3). By connecting REFSENSE externally to AGND, the ADC is configured to use the internal reference (~1.25v), and the REF pin connection (pin 4) is configured as the output of the internal reference voltage.

If REFSENSE is connected externally to AVDD, the ADC is configured to use the external reference. In this mode, the REF pin is configured as a reference input and must be driven by an external 1.25 V reference.

In either configuration, the analog input voltage range (1v pp or 2v pp as determined by DFS/Gain) will linearly track the reference voltage, and an external bypass capacitor should be connected between REF and AGND to reduce noise on the reference. In practice, there is no noticeable drop in performance when the external benchmark is adjusted to ±5%.

DFS/Gain

The DFS/Gain (Data Format Select/Gain) input (Pin 2) controls the ADC's output data format and gain (analog input voltage range). The following table describes its operation.

drive analog input

The analog input of the AD9214 is a differential buffer. As shown in the equivalent circuit, each differential input is internally DC biased at ~AVDD/3 to allow AC coupling of the analog input signal. Analog signals can also be DC coupled. In this case, the DC load will be equivalent to ~10 kΩ to AVDD/3, and the DC common-mode level of the analog signal should be within the range of AVDD/3 ±200 mV. For best dynamic performance, the impedances of AIN and AIN should be matched.

Driving the analog input differentially optimizes AC performance, minimizes even-order harmonics, and utilizes common-mode noise rejection. The differential signal can be transformer coupled, as shown in Figure 8, or driven by a high performance differential amplifier such as the AD8138 shown in Figure 9.

Special care was taken when designing the analog input section of the AD9214 to prevent data corruption and corruption when the input is too large. The optimal input range is 1.0v pp, but the AD9214 can support a 2.0vp-p input range with some performance degradation (see DFS/GAIN pin description above).

power supply

The AD9214 has two power supplies, AVDD and DrVDD. AVDD and AGND power all analog circuits, inputs, and internal timing and digital error correction circuits. The AVDD supply current will vary slightly with the encoding rate, as described in the Typical Performance Characteristics section.

DrVDD and DGND provide CMOS digital outputs only, allowing the user to adjust voltage levels to match downstream logic.

DrVDD current will vary depending on voltage level, external load capacitance and encoding frequency. A design that minimizes external load capacitance will reduce power consumption and reduce power supply noise that can affect ADC performance. The maximum DRVDD current can be calculated as:

where N is the number of output bits, 10 in the case of the AD9214. This maximum current is a condition of switching each output bit on every clock cycle, and it can only occur at the Nyquist frequency, a full-scale square wave of FunCu code/2. In practice, IDrV will be the average number of output bit swaps, which will be determined by the encoding rate and the characteristics of the analog input signal. The Performance Curves section provides a reference for IDrV versus code rate for a 10.3MHz sine wave driving the analog input.

The two power connections should be separated from ground using high quality ceramic chip capacitors at or near the package connection. A single ground plane is recommended for all ground (AGND and DGND) connections.

When the AD9214 is logic high, the PWRDN control pin configures it for sleep mode. During normal operation, pwrnd will float logic low. In sleep mode, the ADC is not active and consumes less power. When switching from sleep mode to normal operation, the ADC takes approximately 15 clock cycles to restore valid output data.

digital output

Care must be taken when designing a data receiver for the AD9214. It is recommended that the digital output drive a series resistor (eg 100Ω) followed by a gate like the 74LCX821. To minimize capacitive loading, there should only be one gate on each output pin. As shown in the schematic diagram of the evaluation board in Figure 10. The series resistor should be placed as close as possible to the AD9214 to limit the amount of current flowing into the output stage. These switch currents are limited between ground (DGND) and the DrVDD pin. Standard TTL gates should be avoided as they can significantly increase the dynamic switching current of the AD9214.

It should also be noted that additional capacitive loading will increase the output timing and invalidate the timing specification. The 10 pF load guarantees digital output timing.

layout information

The schematic of the evaluation board (Figure 10) represents a typical implementation of the AD9214. Multilayer boards are recommended for best results. High-quality ceramic chip capacitors are strongly recommended, with each power pin disconnected to ground directly on the device. The pins of the AD9214 facilitate high-frequency, high-resolution design practices. All digital outputs and their power and ground pin connections are isolated to one side of the package, while the inputs are on the other side for isolation.

Care should be taken when routing digital output traces. To prevent coupling into the analog portion of the AD9214 through the digital outputs, minimal capacitive loading should be placed on these outputs. It is recommended that all AD9214 digital outputs use only one gate fanout.

The layout of the encoding circuit is equally important. Any noise received on this circuit will cause damage during digitization and overall performance degradation. The encoding clock must be isolated from the digital output and analog input.

Evaluation Committee

The AD9214 evaluation board provides designers with an easy way to evaluate device performance. The user must provide the analog input signal, encoded clock reference and power supply. The digital outputs of the AD9214 latch onto the evaluation board and provide a data-ready signal at the 40-pin edge connector. See the evaluation board schematic, layout diagram, and bill of materials.

power connection

Power is supplied to the board through three removable 4-pin power strips (U4, U9, and U10). These 12 pins should be driven as listed in Table II.

Note that the +5 V and -5 V supplies are optional and only required if the user adds the differential op-amp Z1 to the board.

Reference circuit

The evaluation board is assembled configured to use the AD9214's on-board reference. To provide an external reference, the user must connect the REFSENSE pin to VCC by removing the jumper block connecting E25 and E26 and placing it between E19 and E24. In this configuration, the external 1.25 V reference must be connected to jumper connection E23. Jumper headers E19–E21, E24, and resistors R13–R14 are omitted from assembly and are not used in the evaluation of the AD9214.

Gain/Data Format

The evaluation board is equipped with a grounded DFS/gain pin; this configures the AD9214 for a 1v pp analog input range and offset binary data format. The user can remove this jumper and replace it with one of the connections described in the table below to configure the AD9214 for different gain and output data format options.

power outage

Configure the EV kit at assembly so that the PWRDN input floats low under normal operating conditions. The user can add a jumper between option holes E5 and E6 to connect PWRDN to AVCC to configure the AD9214 in power down mode.

Coded Signals and Distribution

The encoded input signal should drive the SMB connector J5, which has on-board 50Ω termination. A standard CMOS compatible pulse source is recommended. Alternatively, the user can adjust the dc level of the ac-coupled clock source by adding resistor R11, which is usually omitted. J5 drives the AD9214 encode input and one gate of U12, which buffers and distributes the clock signal to the on-board latch (U3), reconstruction DAC (U11), and output data connector (U2). The board is assembled with timing options optimized for DAC and latch; the user can reverse pin 37 of edge connector U2 by removing the jumper block between E34 and E35 and reinstalling between E35 and E36 DR signal at .

analog input

The analog input signal is connected to the evaluation board through SMB connector J1. As configured at assembly, the signal is AC coupled by capacitor C10 to transformer T1. This 1:1 transformer provides 50Ω termination to header J1 through 25Ω resistors R1 and R4. T1 also converts the signal at J1 to a differential signal for the analog input of the AD9214. Resistor R3 (usually omitted) can be used to terminate J1 if the transformer is removed.

The user can reconfigure the board to drive the AD9214 by removing the jumper block between E1 and E3 and replacing the jumper block between E3 and E2. In this configuration, capacitor C2 stabilizes the self-bias of AIN, and resistor R2 provides matching impedance for J1 of the 50Ω supply.

Transformer T1 can be bypassed by normally moving the jumper between E40 and E38 to connect E40 and E37, and normally moving the jumper between E39 and E10 to connect E7 and E10. In this configuration, the analog input of the AD9214 is single-ended driven directly from J1; R3 (usually omitted) should be installed to terminate any cable connected to J1.

Using AD8138

An optional driver circuit for the analog input, based on the AD8138 differential amplifier, is included in the layout of the AD9214 evaluation board. This part of the evaluation circuit is not populated when the board is manufactured, but can easily be added by the user. Resistors R5, R16, R18, and R25 are the feedback network that sets the gain of the AD8138. Resistors R23 and R24 set the common-mode voltage of the op amp output. Resistors R27 and R28 and capacitor C15 form a low-pass filter at the output of the AD8138, limiting its noise contribution to the AD9214.

Once the driver circuit is populated, the user should normally remove the jumper block between E40 and E38 and place it between E40 and E41. This will AC couple the analog input signal from the SMB header J1 to the AD8138 driver circuit. The user will also need to remove the jumper blocks that normally connect E39 to E10 and E1 to E3 in order to remove transformer T1 from the circuit.

DAC reconstruction circuit

The data available on output connector U2 is also reconstructed by DAC U11, AD9752. This 12-bit high-speed digital-to-analog converter is a tool for building and debugging evaluation boards. It should not be used to measure the performance of the AD9214 because its performance does not accurately reflect the performance of the ADC. The output of the DAC (available at J2) will drive 50Ω. The user can add a jumper block between E8 and E9 to activate the sleep function of the DAC.

Dimensions

Dimensions are in inches and (mm).

28 Lead Shrink Small Outline Packaging (RS-28)