1. Introduction Active clamp forward (ACF) controllers are popular in high frequency dc-dc modules: near-zero voltage switching, reduced size magnetics, and energy-efficient designs are the hallmarks of ACF. If designing a power stage requires attention to any high-power design, the control-output transfer function of the converter provides a good understanding of the compensation strategy to meet design goals such as crossover and phase margin. This article will first discuss the ACF transfer function and then give a typical compensation example.
2. Power stage operation

Figure 1 shows a simplified circuit diagram of an ACF whose operation details can be found in Reference [1]. Normally, transistor Q1 operates in a classic forward converter, but when it is turned off, its demagnetization process involves a resonant period between the clamping capacitor Cclp and the primary inductor Lmag. A portion of the energy stored in the magnetizing inductance diverts the lumped capacitance at the drain connection, while VDS(t) rises until a path is found through the body diode of Q2. The latter is then short-circuited by turning on Q2 under zero voltage switching (ZVS) conditions: now, the drain of Q1 is clamped to Vclp, which is Vin plus Cclp. Considering the resonant period between Lmag and Cclp, the circulating current will eventually reverse and flow through Q2 (on state) and the magnetizing inductance Lmag.
Figure 1: Active-clamp forward converters can operate at high switching frequencies

At some point, the controller will instruct Q2 to turn on, forcing current out of the grid including Cclp, naturally flowing through the input source Vin and the drain lumped capacitance: the drain node starts to drop until a new switching cycle, This reduces conduction losses.
Figure 2: Near ZVS operation when dead time is well tuned

As shown in Figure 2, a dead time is inserted between MOSFET transitions, providing time to generate the drain-source resonant cycle, which now involves Clump's Lmag, to reach a valley. Under certain operating conditions (small output currents), the leakage wave touches ground resulting in zero conduction losses.
3. Transfer function

Before compensating the converter or any system, you need the control-output transfer function of the power stage. In other words, if you want to excite the control input with a sine wave, in this case a pulse width modulator (PWM), how do you transmit information through the power stage and produce a response in the output? The mathematical relationship linking the response to the stimulus is the transfer function H we need.
Equation (1) derives the control-output transfer function of the ACF in voltage mode, describing the converter by a fourth-order polynomial:

The equation consists of two parts: on the left is the classical forward converter term, where:

The second term in equation (1) represents the addition of an active clamp and the effect of building a resonant network around Cclp and Lmag:

In these expressions, rL and rC represent the output inductor (Lout) and capacitor (Cout) equivalent series resistance (ESR), respectively, ron1 represents the main switching transistor rDS(on), and ron2 represents the active clamp transistor rDS(on) , N represents the transformer turns ratio, and D0 represents the static duty cycle.
From this expression, we can obtain Bode plots of the magnitude and phase responses in the 10-Hz to 100-kHz frequency range (shown in Figure 3). The value for each device is that of a 3.3-V/30-A dc-dc module powered by ON Semiconductor's NCP1566 reference [2]. The active clamp section is intentionally undamped and assumes that Q2 is a low rDS(on) MOSFET.

Figure 3: The control-output transfer function shows a resonance notch, emphasizing the phase where the double zero occurs

When the frequency reaches the resonance described by Equation (3), you can observe an amplitude glitch affected by severe phase distortion. The drop in amplitude is attributed to the sudden increase in the primary side resonant current, which causes a voltage drop across the primary side power MOSFET Q1. As shown by the right-hand term in equation (1), this voltage drop is subtracted from the input voltage Vin and creates an observable response notch. As suggested in References [3] and [4], it is wise to choose a crossover point before the minimum resonant frequency of Lmag-Cclp, since there is a severe phase lag. However, the crossover can be extended if proper damping is applied in the active clamp circuit. As shown in Reference [5], the effect of this decision on the peak drain-source voltage of the main MOSFET must be carefully studied under transient conditions. Figure 4 shows the same transfer function, now suppressed by the 2.5-Ω rDS(on) of Q2: the magnitude and phase responses are very close to those of a classical forward converter and can be selected outside the resonance notch fc.

Figure 4: When damped, the glitch effect of resonance is reduced and you can push the crossover out of resonance.

4. Pulse Width Modulator The expression given in Equation (1) does not include the effect of the PWM module. In an isolated dc-dc converter, the regulation loop is on the secondary side, and the optocoupler biases the controller feedback pin to control the duty cycle. One scheme common in high power converters is the shunt regulator: instead of pulling the pin down to ground through a common emitter configuration, the optocoupler connects the controller through the emitter and injects current. This current is mirrored internally and can pull down an internal node loaded by a 50kΩ resistor. This voltage-biased PWM comparator ensures regulation. This technique minimizes the Miller effect due to the quasi-constant VCE voltage when the input dynamic resistive voltage drop is small: the optocoupler poles are pushed to higher frequencies, avoiding problems when closing the loop. Dynamic resistance rd = 400 Ω, but has no effect on frequency analysis. It will have an effect if you connect the capacitive feedback pin to ground. However, other than this configuration, the impedance needs to be ac because a separate optocoupler can regulate the input current. This current is divided by 10 (divided in units) and is pulled high to adjust the internal operating point.

On the inverting pin, the timing capacitor Cramp is charged by a current that depends on the input voltage. Therefore, the slope of the analog sawtooth wave will be related to the input voltage, dynamically changing the gain as Vin changes. This configuration implements what we call a feedforward operation. Reference [6] may show that the small-signal gain of this modulation unit is equal to:

Figure 5: The optocoupler injects current in the feedback pin to adjust the controller duty cycle

In equation (1), you can see that Vin appears on the right side of the equation, indicating that the DC gain of the transfer function (s=0) will vary with the input voltage. Therefore, both the crossover frequency and stability may be affected. With the PWM transfer function (Equation (4)), Vin in the denominator cancels out the effect of the input voltage, stabilizing the loop gain and crossover frequency over the input range.
5. Type 3 Compensator To design the loop gain of the ACF converter, we need a transfer function that relates the PWM mode excitation factor D(s) to the observed variable Vout(s) response. We will apply selected design strategies through pole-zero locations to ensure robustness and good transient response of the converter.

Figure 6 shows a typical architecture with a Type3 compensator isolated with an optocoupler. The optocoupler itself is affected by the current transfer ratio (CTR) and the pole, whose location depends on the load resistance. In this application, the shunt regulation feedback input reads the optocoupler current. The load resistance is rd and is fairly small, which means that we have to describe a rather high frequency optocoupler pole in order to neutralize it later Ref. [7]. Note here that the LED is connected to a quiet Vcc point (or auxiliary voltage Vaux) on the secondary side, fully AC coupled to Vout. This needs to be taken care of, otherwise a fast channel will be created, distorting the frequency response of the compensator reference [7]. The AC current in an LED (ignoring its dynamic resistance) is given by:

where Vop is the AC output voltage of the op amp. Assuming this is a perfect op amp, the voltage is defined as:
Zf and Zi are the impedances circled in FIG. 6 . From these two networks, we can use a quick analysis of the circuit technical reference [8] to infer the location of our desired transfer function zeros. With Vout excited, what combination of Zf and Zi impedances are required to make the output VFB zero?

Figure 6: Using a voltage-mode active-clamp forward converter closed-loop requires a Type 3 compensator.
In this example, Rpullup is 50kΩ, RLED is arbitrarily fixed at 1kΩ, and R1 is 1662Ω.
There are two conditions:
When Vout is tuned at sz, the Zi amplitude is infinite, then VFB(sz) = 0 V. Zi consists of a numerator and a denominator D(s). When D(sz) = 0, this impedance is infinite. Therefore, the poles of this first-order network are the zeros we want. The time constant affecting Zi is obtained by temporarily disconnecting C3 and "observing" the resistance provided through its connecting terminal. In our minds, the time constant is just the network poles or transfer function zeros.
When R2 and C1 are connected in series to form a conversion short circuit, the output is also zero. This impedance is defined as . You can define a second zero position by getting the zero point. Next, we can update Equation (7) according to the formula.

Now consider R3 << R1 and C2 << C1.
Substituting the formula into the formula yields the LED current:

The output voltage VFB is the optocoupler emitter current divided by the current mirror divider ratio div.

The emitter current is the LED current affected by CTR:

Combining all these expressions with Equation (9), we get the desired complete transfer function:

It can be represented in the following low-entropy format, with an anti-zero point in the molecule:

in:

Now that we have the compensator transfer function, we need a way to adjust the desired gain or attenuation at the crossover point. This can be done by choosing the correct value of R2, taking into account other device values fixed by the design or imposed by the manufacturer (for example, Rpullup in the circuit). The magnitude of equation (12) is determined by:

From this you can extract the correct value of R2, which is known to represent the desired gain or attenuation at the chosen crossover frequency fc:
Once the value of R2 is known, the remaining compensation elements can be calculated using equations (15) through (18).
6. Compensation Strategy With the full Type3 transfer function at hand, we can come up with a compensation strategy based on the power stage response of the converter we want to stabilize. We have several options for obtaining this response. We can calculate it with Mathcad® and the analytical expression (1) we give, or it can be calculated on the workbench. For the latter option, we need a working hardware. Another viable option is the SIMPLIS® simulation circuit shown in Figure 7.

Figure 7: This simple closed-loop ACF template uses the demo version elements

SIMPLIS® is a piecewise linear (PWM) simulator that allows you to extract small signal responses from switching converters. Considering a simple analog circuit, the control-output response may be available in a few seconds from the demo version Element (https:///). Figure 8 shows the phase and magnitude plots. This response corresponds to that of a converter outputting 3.3V/30A from a 36-72-V input line. The main controller is ON Semiconductor's NCP1566, which operates at a switching frequency of 500kHz. The transformer turns ratio is 6:1 and the secondary inductance is 0.5µH. The glitches generated by the active clamp resonant network are well controlled and can be safely crossed over. In this example we will choose a crossover frequency fc of 30 kHz.

The following information can be extracted from these plots: the amplitude attenuation at 30kHz is about 11.8dB, and the phase lag at this frequency reaches 133°. With this data, the compensation strategy is as follows:
Place the double zero just below the output filter resonance calculated at 8.7 kHz. Typically, if the converter is switching in DCM, you can place one zero at resonance and the other at a lower frequency. This ensures good phase margin under light load conditions. In this example, the self-driven synchronous rectifier will ensure operation with CCM even at no load.

Figure 8: The switching waveform determines the operating point, while the small signal response gives the information needed for the stabilization process

2. Place the pole at half the switching frequency or 250kHz.
3. Considering the 60° phase margin target reference [6], evaluate the necessary phase boost.
This value confirms the need for a Type3 compensator, as 90° is the maximum limit for Type2.
4. The compensator will cascade two zeros and two poles. If you ignore the poles contributed by the origin, the phase boost produced by these pole/zero pairs is:

Double zero and second pole fp2 have been determined. The angles of interest to determine the position of fp1 are:
Therefore, we need to position the second pole so that the phase boost is equal to 105°:
5. Normalized device values calculated from Mathcad® sheet reference [2] yield the following results: R2 is 390 8486 ; (CTR = 1), C1 = 100 nF, C2 = 22 nF, R3 = 27 Ω, C3 = 22nF.
Crossing over at around 30 kHz indicates a fast op amp, and its own response will not affect the waveform of the Type3 you want to build. Reference [9] explains how a poorly chosen op amp affects the performance of the final compensator, severely degrading the phase margin. In this example, we chose a TLV271 , and the initial Type3 phase and magnitude response was not affected by this circuit. Also, note the effect of the optocoupler on the compensator response. PS2801 is a classic dc-dc converter. As mentioned earlier, the parallel-based feedback path applies reasonable collector current and regulates the emitter voltage, modeled on a cascade-like architecture: considering a near-constant Vce voltage, the Miller effect is greatly reduced, naturally placing the optocoupler pole Go to a higher frequency. However, at the crossover frequency of 30 kHz, it still achieves the expected phase margin, which we have compensated for by placing a simple capacitor in parallel with the RLED, as shown in Figure 6.
We can now plot the loop gain T(s) and check the margin. Figure 9 shows the loop gain plotted with Mathcad®. The theoretical 30 kHz crossover frequency was verified, along with the desired 60° phase margin.

Figure 9: Loop Gain Verifies Selected Crossover Frequency and Correct Phase Margin
7. The final circuit diagram 10 shows the primary side schematic and the secondary side schematic is shown in Figure 11. The NCP1566 integrates all necessary features to build a robust and energy efficient active clamp converter.

Figure 10: The primary side uses a controller designed for the active clamp converter NCP1566

The device integrates various protections and adaptive dead-time to improve the circuit's light-load energy efficiency. On-board high voltage current source ensures start-up sequence and Dynamic Self-Powering (DSS): If the auxiliary winding needs time to supply the controller, DSS supplies energy to the IC until the auxiliary voltage builds up and turns off the current source. When skipping cycles under light or no-load conditions, the auxiliary winding can be damaged due to very narrow pulses. DSS will automatically activate in this mode, self-powering the controller.

Figure 11: Two op amps and a voltage reference are applied on the secondary side. The power stage uses Payton's planar transformer with input and output inductors through a pair of self-driven synchronous rectifiers. Active-clamp forward converters are well suited to directly drive these transistors due to the extended demagnetization period on the primary side: the drive voltage on the secondary side is 100% present during turn-off and ensures smooth operation of these voltage-controlled rectifiers. This is not classical forward, which is when the main inductor is demagnetized, the NVin voltage disappears from the secondary side.

The loop is built around two op amps. The first U4 is used for the Type3 compensator, while the U5 drives the LEDs, well suppressing current interaction with Vout (no fast channel issues). Note that the compensation value is slightly different from the calculated value, which is the difficulty associated with these dc-dc modules. Our calculations only deal with small signal responses, and when the component values are plugged into the converter, the loop is stable as expected. However, there is a problem with these converters, namely how Vout rises at power up. The rise must be monotonic, with no double slope. This is a large signal run until Vout settles to its regulation value. During this time, it is difficult to predict how the individual capacitors will charge and how they will affect the output voltage rise. One way to apply a monotonic start is to soft start the secondary side reference voltage U3 via R14 and C6. Once the converter starts up, the auxiliary voltage across C37 rises rapidly (C37 needs to be a small capacitor), and with the low voltage on C6, it applies op-amp U4 to first force Vout to follow the exponential charge of C6. In this case, the primary soft-start duration is reduced to limit the stress on the semiconductor, but must be limited to this effect, otherwise the two soft-start processes (primary and secondary) can oppose and distort the output voltage rise. Some adjustments are necessary.

8. Loop Measurement The circuit in Figure 11 shows a 10-Ω resistor (R2) in series with the upper resistor of the voltage sense divider. This resistor keeps the loop closed during normal operation and does not affect regulation because of its low value. By connecting a transformer to this resistor, as shown in Figure 12, the open-loop transfer function of the converter can be obtained without physically opening the loop. This technique was pioneered by Dr. Middlebrook in the 1970s and is described in detail in Ref. [10].

Figure 12: 10Ω resistor lets you scan converters and get transfer function selection

I recommend adding this resistor at the prototyping stage, using two simple wires to connect the probe. When you're dealing with a multi-layer printed circuit board full of small components, the board is assembled back and you can't make any further changes. Cutting wires to insert small resistors and then attaching probes to them is complicated and dangerous. These extra pads can be attached more easily and easily during the layout stage.

To measure the loop, I tested a CS328A instrument made by CleverScope New Zealand (https://cleverscope.com/). The device includes a 2-channel 14-bit oscilloscope and a frequency response analyzer (FRA) at a very competitive price. There is no need to plug in an isolation transformer because the CS328A is a solid state injector and you just need to connect the probe to the power supply. The instrument first performs a rough sweep and fine-tunes the injection level to maintain an appropriate signal/noise ratio without affecting linearity. When the instrument persistently displays the observed waveform, you can immediately check whether saturation has occurred during the sweep. And has a nice feature that avoids connecting another oscilloscope to monitor work in parallel with the FRA. The result of the sweep is shown in Figure 13, showing the correct crossover frequency and slight phase distortion. Further analysis showed that the front-end EMI filter resonated around this point and needed adequate damping. Once done, the glitch disappeared as expected.

Figure 13: Measurements verify 30 kHz crossover with adequate phase margin and show glitches caused by front-end EMI filters.
9. Summary This paper presents a compensation strategy for voltage-mode controlled active-clamp forward converters. Combining tools such as simulation and mathematical solvers is the best way to design and understand the role of each element. The compensation strategy can be viewed as compensating for the variability of the device, which is then verified by bench measurements. Once the model is deemed to behave consistently in hardware, these influences must be cleaned up in the simulation environment to ensure that they are fully neutralized by the compensation scheme employed.