feature

Contains internal oscillator and reference voltage; no adjustment required; half-bridge interface, 4-wire LV DT; DC output proportional to position; 20 Hz to 20 kHz frequency range; unipolar or bipolar output; also decodes AC signals; excellent Linearity: 0.05%; Output Voltage: 611V ; Gain Drift: 20 ppm/8C (typ.); Offset Drift: 5 ppm/8C (typ.).

Product Description

The AD698 is a complete monolithic linear variable differential transformer (LVDT) signal conditioning subsystem. It is used in conjunction with LVDTs to convert the mechanical position of the sensor to a unipolar or bipolar DC voltage with high accuracy and repeatability. All circuit functions are contained in the chip. By adding some external passive components to set the frequency and gain, the AD698 converts the raw LVDT output to a scaled DC signal. The device will operate using half-bridge LVDTs, LVDTs and RVDTs connected in a series split configuration (4-wire).

The AD698 contains a low distortion sine wave oscillator to drive the LVDT main circuit. The two synchronous demodulation channels of the AD698 are used to detect the primary and secondary amplitudes. This part divides the secondary output by the amplitude of the primary output, multiplied by the scale factor. This eliminates scaling factor errors due to main drive amplitude drift, improving temperature performance and stability.

The AD698 employs a unique ratiometric structure that eliminates some of the disadvantages associated with traditional LVDT interface methods. The advantages of this new circuit are: no adjustment required; improved temperature stability; improved sensor interchangeability.

The AD698 is available in two performance grades:

Product Highlights

1. AD698 provides a single-chip solution to the problem of LVDT signal conditioning. All active circuits are on the microcontroller, and only passive components can complete the conversion from mechanical position to DC voltage.

2. AD698 can be used for many different types of position sensors. This circuit is optimized for use with any LVDT, including half-bridge and series-opposed (4-wire) configurations. The AD698 accommodates a wide variety of input and output voltages and frequencies.

3. The excitation frequency from 20Hz to 20kHz is determined by a single external capacitor. The AD698 provides up to 24 volts rms of differentially driven LVDT mains, and the AD698 meets its specifications with input levels as low as 100 millivolts rms.

4. The change of oscillator amplitude with temperature will not affect the overall performance of the circuit. The AD698 calculates the ratio of the secondary voltage to the primary voltage to determine position and orientation. No adjustment is required.

5. As long as the power consumption limit is not exceeded, multiple lvdts can be driven by a single AD698, which can be plug-in or parallel. The excitation output is thermally protected.

6. AD698 can be used as loop integrator in simple electromechanical servo loop design.

7. The sum of the secondary voltage of the sensor does not need to be constant.

Typical Characteristics (at +25C and VS=15V, unless otherwise noted) °

theory of operation

Figure 5 below shows the block diagram of the AD698 and the LVDT (Linear Variable Differential Transformer) connected to its inputs. LVDT is an electromechanical transducer whose input is the mechanical displacement of the magnetic core and the output is an AC voltage proportional to the position of the magnetic core. Two popular types of LVDTs are the half-bridge type and the series opposite or four-wire LVDT. In both types, a movable magnetic core couples the magnetic flux between the windings. A series reverse connected LVDT sensor consists of a primary winding excited by an external sine wave reference source and two secondary windings connected in a series reverse configuration. When the core is moved away from the center, the output voltage on the secondary side of the series increases. The direction of motion is detected by measuring the phase of the output. Half-bridge LVDTs have a single coil with a center tap and work like an autotransformer. The excitation voltage is applied across the coil; the voltage at the center tap is proportional to position. The device works like a resistive voltage divider.

The AD698 energizes the LVDT coil, senses the LVDT output voltage, and produces a DC output voltage proportional to the core position. The AD698 has a sine wave oscillator and power amplifier to drive the LVDT. Two synchronous demodulation stages are available for decoding the primary and secondary voltages. The decoder determines the ratio of the output signal voltage to the input drive voltage (A/B). Filter stages and output amplifiers are used to scale the resulting output.

The oscillator includes a multivibrator that produces a three-wave output. The three waves drive a sine shaper, producing a low distortion sine wave. Frequency and amplitude are determined by a single resistor and capacitor. The output frequency range is 20 Hz to 20 kHz and the amplitude is 2 volts to 24 volts rms. Total harmonic distortion is typically -50dB.

The AD698 decodes LVDTs by synchronously demodulating the AM input (secondary) and the fixed input reference (primary or the sum of the secondary or fixed inputs). A common problem with early solutions is that any drift in the amplitude of the drive oscillator corresponds directly to gain error in the output. The AD698 removes these errors by calculating the ratio of the LVDT output to the input excitation to remove any drift effects. This device differs from the AD598 LVDT signal conditioner in that it implements a different circuit transfer function and does not require the LVDT secondary element (a+B) to have a constant sum and stroke length.

The AD698 block diagram is shown below. The input consists of two independent synchronous demodulation channels. The B channel is designed to monitor the drive excitation of the LVDT. The full-wave rectified output is sent to the calculation circuit after being filtered by C2. Channel A is the same except that the comparators are fixed separately. Since the A channel can reach 0v output when the LVDT is zero, the A channel demodulator is usually triggered by the main voltage (B channel). Additionally, a phase compensation network may need to add phase lead or lag to the a-channel to compensate for the LVDT primary to secondary phase shift. For a half-bridge circuit, the phase shift is non-critical and the A channel voltage is large enough to trigger the demodulator.

Once both channels have been demodulated and filtered, the a/B ratio is calculated using a division circuit implemented with a duty cycle multiplier. The output of the divider is a duty cycle. When A/B is equal to 1, the duty cycle is equal to 100%. (This signal can be used if a pulse width modulated output is desired.) The duty cycle drives a circuit that modulates and filters a reference current proportional to the duty cycle. The output amplifier converts the reference current of 500 microamps into a voltage. Therefore, the output transfer function is:

Connect AD698

As shown in Figures 7, 8, and 13, the AD698 can be easily connected for dual-supply or single-supply operation. The following general design procedure demonstrates how to select external component values and can be used with any LVDT that meets the AD698 input/output criteria. The connections for the A and B channels and the A channel comparator will depend on the sensor used. In general, follow the guidelines below.

Parameters set with external passive components include: excitation frequency and amplitude, AD698 input signal frequency and scale factor (V/inch). In addition, there are optional functions: offset zero adjustment, filtering and signal integration, which can be achieved by adding external components.

Designer Dual Power Operation

Figure 7 shows the connection method for half-bridge LVDTs. Figure 8 shows the connection of 3-wire and 4-wire LVDTs connected in a series reverse configuration. Both examples use dual ±15V supplies.

A. Determine the oscillator frequency

The frequency is usually determined by the bandwidth required by the system. However, in some systems, the frequency is set to match the manufacturer's recommended LVDT zero-phase frequency; in this case, skip to step 4.

1. Determine the mechanical bandwidth required by the LVD position measurement subsystem F subsystem. For this example, assume fSUBSYSTEM=250 Hz.

2. Select the minimum LVDT excitation frequency approximately 10×FS subsystem. Therefore, let the excitation frequency = 2.5 kHz.

3. Choose a suitable LVDT, it will work at the excitation frequency of 2.5khz. For example, the Schaevitz E100 will operate in the 50 Hz to 10 kHz range and is a good candidate for this example.

4. Select the excitation frequency determination component C1.

B. Determining Oscillator Amplitude

Set the amplitude so that the primary signal is in the 1.0V to 3.5v rms range and the secondary signal is in the 0.25v to 3.5v rms range when the LVDT is in the mechanical full-scale position. This optimizes linearity and minimizes noise sensitivity. Since this part is scaled, the exact value of the excitation is relatively unimportant.

5. Determine the optimal LVDT excitation voltage VEXC. For a 4-wire LVDT, the voltage conversion ratio VTR of the LVDT is determined at its mechanical full scale. VTR=LVDT sensitivity×maximum run length is NULL.

LVDT sensitivity is listed in the LVDT manufacturer's catalog, and the input voltage output unit is volts per inch of displacement. The sensitivity of the E100 is 2.4 mV/V/mil. If the LVDT sensitivity is not given by the manufacturer, it can be calculated. See the section on Determining LVDT Sensitivity.

Multiply the primary excitation voltage by the voltage transformer to obtain the expected secondary voltage at mechanical full scale. For example, for an LVDT with a sensitivity of 2.4 mV/V/mil and a full scale of ±0.1 inches, VTR=0.0024 V/V/mil×100 mil=0.24. Assuming a maximum excitation of 3.5 V rms, the maximum secondary voltage will be 3.5 V rms × 0.24 = 0.84 V rms, which is within the acceptable range.

Instead, VTR can be measured explicitly. When the LVDT is powered up at its typical drive level VPRI, as indicated by the manufacturer, set the core displacement to its mechanical full-scale position and measure the output VSEC of the secondary device. Calculate the LVDT voltage conversion ratio VTR. VTR=VSEC//VPRI. For E100, VSEC=0.72 V, for VPRI=3 V. VTR=0.24.

For cases where the LVDT sensitivity is low, or where the mechanical FS is a small fraction of the total stroke length, input excitation greater than 3.5v rms may be required. In this case, a voltage divider network can be placed on the primary side of the LVDT to provide smaller voltages to the +BIN and –BIN inputs. For example, if a net is added to divide the B channel input by 1/2, the VTR should also be reduced by 1/2 for component selection purposes.

Check the supply voltage to verify that the peaks of VA and VB are at least 2.5 volts lower than the voltages at +VS and –VS.

6. Referring to Figure 9, for VS=±15v, select the value of the amplitude determination component R1 shown in the curve in Figure 9.

7. C2, C3, and C4 are functions of the bandwidth required by the AD698 position measurement subsystem. They should be nominally equal.

C2 = C3 = C4 = 10–4 Farad Hz/f5UBSYSTEM (Hz), if the desired system bandwidth is 250 Hz, then C2 = C3 = C4 = 10-4 Farad Hz/250 Hz = 0.4 μF, for AD698 bandwidth and See Figures 14, 15, and 16 for more information on phase characteristics.

D. Set the full-scale output voltage

8. To calculate R2 and set the AD698 gain or full-scale output range, several pieces of information are required:

a.LVDT sensitivity

b. The displacement of the full-scale core from the zero position, d: S×d=VTR, is also equal to the ratio A/B scale when the machine is fully loaded. The VCR should be converted to V/V units.

For a full-scale displacement of d inches, the voltage beyond the AD698 is calculated as:

VOUT is measured relative to the signal reference, pin 21, as shown in Figure 7. Solving for R2,

For VOUT = ±10 V full scale (20 V scale) and d = ±0.1 inch full scale displacement (0.2 inch scale):

Figure 10 shows VOUT as a function of displacement in the above example.

E. Optional offset for output voltage swing

9. Selection of R3 and R4 allows positive or negative output voltage offset adjustment.

For no offset adjustment, R3 and R4 should be left open.

To design a circuit that produces a 0 V to +10 V output with a displacement of +0.1 inches, set VOUT to +10 V, d=0.2 inches, and solve the equation for R2.

This will produce the response shown in Figure 11.

In equation (2), set VOS to 5v and solve for R3 and R4. Because a positive offset is required, leave R4 open. Rearrange the solution of equation (2) and R3:

Note that VOS should be chosen so that R3 cannot have negative values.

Figure 12 shows the desired response.

design program

Single supply operation

Figure 13 shows the single-supply connection method.

For single-supply operation, repeat steps 1 through 10 of the dual-supply operation design procedure. R5, R6 and C5 are additional component values to be determined. VOUT is measured against the signal reference.

10. Calculate the maximum value of R5 and R6 based on the relationship:

11. The voltage drop on R5 must be greater than:

therefore

Based on the constraints of R5+R6 (step 10) and R5 (step 11), choose an intermediate value R6.

12. The load current through RL returns to the junction of R5 and R6 and flows back to VPS. At maximum load conditions, make sure to define the voltage drop across R5 in step 11.

As a final check of the supply voltage, verify that the peaks of VA and VB are at least 2.5 volts lower than the voltage between +VS and –VS.

13. C5 is a bypass capacitor in the range of 0.1 to 1 μF.

Gain-Phase Characteristics

To use LVDTs in closed-loop mechanical servo applications, it is necessary to understand the dynamics of the sensor and interface components. The sensor itself responds very quickly once the core is moved. The kinetics mainly come from interface electronics. Figures 14, 15, and 16 show the frequency response of the AD698 LVDT signal conditioner. Note that Figure 15 and Figure 16 are basically the same; the difference is the frequency range covered. Figure 15 shows a wider range of mechanical input frequencies at the expense of accuracy.

Figure 16 shows a more limited frequency range and improved accuracy. These numbers are transfer functions, the input is seen as a sinusoidally varying mechanical position and the output is seen as a voltage from the AD698; the unit of the transfer function is volts per inch. The values of C2, C3 and C4 in Figure 7 are all equal and specified as parameters in the figure. The response is approximately that of two real poles. However, there is significant overphase at higher frequencies. An additional filter pole can be passed through R2 through a parallel capacitor, as shown in Figure 7; this also increases the phase lag.

There are tradeoffs when choosing the values of C2, C3, and C4 to set the bandwidth of the system. There is a ripple in the output voltage at the "DC" position, the magnitude of which is determined by the filter capacitor. In general, smaller capacitors will provide higher system bandwidth and more ripple. Figures 17 and 18 show the magnitude of the ripple as a function of C2, C3 and C4, again all equal in value. Also note that the shunt capacitor on R2 in Figure 7 is shown as a parameter. The R2 value used was 81 kΩ, Schaevitz E100 LVDT.

Determination of LVDT sensitivity

LVDT sensitivity can be determined by measuring the LVDT secondary voltage as a function of primary driver and core position, and performing simple calculations.

Power up the LVDT at its recommended main drive level VPRI (3v rms for the E100). Set the core displacement to its mechanical full-scale position and measure the secondary voltages VA and VB.

As can be seen from Figure 19,

Thermal Shutdown and Loading Considerations

The AD698 is protected by thermal overload circuitry. When the mold temperature reaches 165°C, the excitation amplitude of the sine wave gradually decreases, thereby reducing the internal power consumption and temperature.

Due to the ratiometric operation of the decoder circuit, only a small error comes from the reduction of the excitation amplitude. Under these conditions, the signal processing portion of the AD698 continues to meet its output specifications.

The thermal load depends on the voltage and current delivered to the load and the supply voltage. The LVDT primary winding will create an inductive load on the sine wave excitation. The phase angle between the excitation voltage and current must also be considered, complicating thermal calculations.

application

Most applications for the AD598 can also be implemented with the AD698. See the application written for the AD598 for detailed instructions.

See AD598 datasheet:

– Test Ring Scale

– Synchronous operation of multiple LVDTs

– High resolution position-frequency circuit

– Low cost setpoint controller

– Mechanical follow-up servo loop

– Differential measurement and precision differential measurement

AC Bridge Signal Conditioner

Bridge circuits using DC excitation are often plagued by errors caused by thermocouple effects, 1/f noise, DC drift in electronics, and line noise pickup. One way to solve these problems is to excite the bridge with an AC waveform, amplify the output of the bridge with an AC amplifier, and synchronously demodulate the resulting signal. At the output of the synchronous demodulator, the AC phase and amplitude information from the bridge is restored to a DC signal. Low-frequency system noise, DC drift, and demodulator noise all mix into the carrier frequency and can be removed by a low-pass filter.

The AD698 plus a simple AC gain stage can be used to implement an AC bridge. Figure 20 shows the connections for such a system. The AD698 oscillator provides the AC excitation for the bridge. The low-level bridge signal is amplified by the gain stage created by A1, A2 to provide a differential input to the a-channel of the AD698. Then, the signal is detected by channel synchronization. Channel B is used to detect the bridge excitation level. The A/B ratio is then calculated and converted to the output voltage via R2. An optional phase lag/lead network can be added in front of the comparator to adjust the phase delay through the bridge and amplifier, or if the phase delay is small, it can be ignored or compensated by gain adjustment.

This circuit can be used in resistive bridges, such as strain gages, or inductive or capacitive bridges, typically used in pressure or flow sensors. The low-level signal outputs of these sensors are susceptible to noise and interference and are good candidates for AC signal processing techniques.

Component selection

Amplifiers A1, A2 will be selected according to the type of bridge being adjusted. A low bias current amplifier should be used for the capacitive bridge; a large bleed resistor is required from the amplifier input to ground to provide a path for the DC bias current. Resistive and inductive bridges can use more general purpose amplifiers. The DC performance of A1 and A2 is not as important as the AC performance. DC errors such as voltage offsets will be truncated by the AD698 due to being out of sync with the carrier frequency.

The oscillator amplitude and span resistance of the AD698 can be selected by first calculating the transfer function or sensitivity of the bridge and AC amplifier. This ratio will correspond to the A/B term in the AD698 transfer function. For example, consider a resistive strain gage with a full-scale sensitivity of 2 mV/V. Choose an arbitrary target value for a(b) close to its maximum value, such as a = 0.8. Then choose a gain for the AC amplifier such that the strain gage transfer function from excitation to output is also equal to 0.8. Therefore, the desired amplifier gain will be [A/B]/S; or 0.8/0.002 V/V=400. Then choose values for RS and RG. For the gain stage:

Solve for VOUT/VIN=400 and set RG=100Ω, then:

Choose an oscillator amplitude in the range of 1V to 3.5V rms. For an input excitation level of 3 V rms, the output signal of the amplifier gain stage will be 3.5 V rms × 0.8 V or 2.4 V rms, which is within the acceptable range.

Since A/B is known, the value of R2, the output FS resistance can be selected by the following formula:

For a 10v output at FS, a/B is 0.8; solve for R2.

This will result in an output voltage of 10 V for the full-scale signal from the bridge. The other components C1, C2, C3, C4 can be selected by following the general equipment operating guidelines mentioned earlier.

If gain trimming is required, a trimming resistor can be used to adjust R2 or RG. The bridge offset should be adjusted through trimming networks on the AD698 offset 1 and offset 2 pins.

Dimensions

Dimensions are in inches and (mm)