feature

Nonvolatile memory holds wiper settings; 64-bit digital potentiometer; compact MSOP-10 (3mm x 4.9mm) I2C compatible interface; VLogic pins provide added interface flexibility; end-to-end resistance 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ; resistance tolerance stored in EEPROM (0.1% accuracy); power-up EEPROM refresh time <1 ms software write protect command; address decode pins AD0 and address decode pins AD1 allow each bus Available in four packs; 100-year typical data retention at 55°C; wide operating temperature -40°C to +85°C 3 V to 5 V single supply.

application

LCD panel VCOM adjustment; LCD panel brightness and contrast control; replacement of mechanical potentiometer in new design; programmable power supply RF amplifier bias; automotive electronics adjustment; gain control and offset adjustment; fiber to the home system; electronic level setting.

General Instructions

The AD5258 provides a compact, non-volatile 3 mm × 4.9 mm package solution for 64-bit trim applications. These devices perform the same electronic adjustment functions as mechanical potentiometers or variable resistors, but with enhanced resolution and solid-state reliability.

The wiper settings can be controlled via an IC-compatible digital interface, which is also used to read the wiper registers and EEPROM contents. In addition, resistance tolerances are stored in EEPROM, providing end-to-end tolerance accuracy of 0.1%. There is also a software write protection feature that ensures that data cannot be written to the EEPROM registers.

A separate VLogic pin provides increased interface flexibility. For users who need multiple parts on one bus, address bits AD0 and AD1 allow up to four devices on the same bus.

1. The terms digital potentiometer, variable resistor, and RDAC are used interchangeably.

theory of operation

The AD5258 is a 64-bit digitally controlled variable resistor (VR) device. The wiper defaults before programming the EEPROM are mid-scale.

Variable Resistor Programming

Rheostat operation

The nominal resistance (RAB) of the RDAC between Terminal A and Terminal B is 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance of the VR has 64 contacts accessible through the wiper terminals. The 6-bit data in the RDAC latch is decoded to select one of 64 possible settings.

The general formula for determining the digitally programmed output resistance between wiper W and terminal B is:

where: D is loaded in the 6-bit RDAC register. RAB is end-to-end resistance. RW is controlled by each internal switch.

Note that there is a relatively low finite wiper resistance value at zero scale conditions. It should be noted that the current flow between the wiper W and the terminal B is limited to a maximum pulse current of not more than 20 mA in this state. Failure to do so may result in degradation or damage to the internal switch contacts.

Similar to a mechanical potentiometer, the resistance of the RDAC between wiper W and terminal A produces a digitally controlled complementary resistance R. The resistance value of the RWA is set starting at the maximum value of the resistance and decreasing as the value of the data loaded in the latch increases. The general equation for this operation is:

Typical equipment-to-equipment matching is process batch dependent and can vary by as much as ±30%. Therefore, the resistance tolerance is stored in the EEPROM so the user will know that the actual RAB is within 0.1%.

Program the Potentiometer Divider

Voltage output operation

A digital potentiometer easily creates a voltage divider proportional to the input voltage at a to terminal B at wiper W to terminal B and wiper W to terminal a. Unlike the polarity of VDD to GND (which must be positive), the voltage goes through terminal a to terminal B, wiper W to terminal a, and wiper W to terminal B can be in either polarity.

If you ignore the effect of the wiper resistance on the approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper WB terminal, from 0 V to 1 LSB, less than 5 V. For any effective input voltage applied to terminal A, define a general equation for the output voltage at V with respect to ground. Terminal B is:

A more precise calculation includes the effect of wiper resistance (VW):

Operation of the digital potentiometer in voltage divider mode results in more accurate overtemperature operation. Unlike the varistor mode, the output voltage is mainly determined by the ratio of the internal resistances (RWA and RWB), not the absolute value.

IC interface

Note that the wiper defaults to mid-scale before programming the EEPROM.

When a high-to-low transition occurs on the SDA line while SCL is high, the master initiates a data transfer by establishing a start condition (see Figure 3). The next byte is the slave address byte, which consists of the slave address (the first seven bits) and an R/W bit. When the R/W bit is high, the master device reads the slave device. When the R/W bit is low, the master device writes to the slave device.

The slave address of the part is determined by two configurable address pins, AD0 and AD1. The states of these two pins are registered and decoded into the corresponding IC7 bit addresses at power-up (see Table 5). The slave address corresponding to the transmit address bit responds by pulling the SDA line low during the ninth clock pulse (this is called the slave acknowledge bit).

During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial registers.

writing

In write mode, the last bit (R/W) of the slave address byte is logic low. The second byte is the instruction byte. The first three bits of the instruction byte are the instruction bits (see Table 6). The user must choose whether to write to the RDAC or EEPROM registers or activate software write protection (see Table 7 to Table 10). The last five digits are all zeros (see Table 13 and Table 14). The slave pulls the SDA line low again during the ninth clock pulse.

The last byte is the data byte MSB first. It doesn't matter if it can be high or low. In the case of write-protected mode, no data is stored; instead, a high logic in the LSB enables write protection. Likewise, logic low disables write protection. The slave pulls the SDA line low again during the ninth clock pulse.

save/restore

In this mode, only the address and instruction bytes are required. The last bit (R/W) of the address byte is the logic low bit. The first three bits of the instruction byte are the instruction bits (see Table 6). The two options are to transfer data from RDAC to EEPROM (storage) or from EEPROM to RDAC (restore). The last five digits are all zeros (see Table 13 and Table 14). Additionally, the user should issue a NOP command immediately after restoring the EEMEM setting to RDAC to minimize supply current consumption.

read

Assuming the register of interest is not directly writeable, it is necessary to write a virtual address and instruction byte. The instruction byte will vary depending on whether the desired data is an RDAC register, an EEPROM register, or a tolerance register.

After sending the virtual address and instruction bytes, a repeated start is required. After repeated start, another address byte is required, but this time the R/W bit is logic high. This address byte is followed by a readback byte containing the information requested in the instruction byte. The read bit occurs on the negative edge of the clock. Don't care if it might be high or low.

Tolerance registers can be read individually (see Table 15) or consecutively (see Table 16). See the "Read Modes" section for details on interpreting tolerance bytes.

After all data bits have been read or written, the master will establish a stop condition. A stop condition is defined as a low-to-high transition on the SDA line when SCL is high. In write mode, the master pulls the SDA line high during 10 clock pulses to establish a stop condition (see Table 8). In read mode, the master responds with a no to the ninth clock pulse (ie the SDA line is held high). The master then drives the SDA line low before 10 clock pulses and drives SDA high to establish a stop condition (see Table 11).

The Repeat Write feature provides the user with the flexibility to update the RDAC output multiple times after addressing and instructing the part only once. For example, after the RDAC acknowledges its slave address and instruction byte in write mode, the RDAC output is updated on each successive byte until a stop condition is received. If a different command is required, the write/read mode must be restarted with the new slave address, command and data bytes. Likewise, the repeated read function of the RDAC is also allowed.

Below is the generic, write, read and store/restore control table 5. The device address lookup registers of the AD5258 refer to the device addresses listed in Table 5, and below are the mode/condition reference keys.

S = start condition

P = stop condition

SA=Slave Confirmation

MA = Master Confirmation

NA=No Confirmation

W=Write

R=read

X = don't care

AD1 and AD0 are two status address pins.

Common interface

Before programming the EEPROM, the default value of the wiper is mid-scale.

To activate write-protect mode, the WP bit in Table 10 must be logic high. To disable write protection, the command must be resent unless WP is in a logic-zero state.

read mode

Read mode is called legacy mode because the first two bytes in all three cases are dummy bytes used to point the pointer to the correct register. That's why repeat starts. In theory, if the user table 11. Traditional readback of RDAC register values is of interest to read registers that were previously written. For example, if the EEPROM has just been written to, the user can skip two dummy bytes and go straight to the slave address byte followed by the read back data of the EEPROM.

The AD5258 features patented RAB tolerance memory in nonvolatile memory. Tolerances are stored in memory during factory production and can be read by the user at any time. Knowledge of the stored tolerance allows the user to calculate R precisely. This feature is useful for accuracy, rheostat mode, and open loop applications where knowledge of absolute resistance is critical. AB Company

The stored tolerance is in read-only memory and is expressed as a percentage. Tolerances are stored in two memory location bytes in symbol-sized binary (see Figure 39). The two EEPROM address bytes are 11110 (sign + integer) and 11111 (decimal). These two bytes can be accessed independently by two separate commands (see Table 15). Alternatively, the first byte can be read followed by the second byte in one command (see Table 16). In the latter case, the memory pointer is automatically incremented from the first EEPROM location to the second EEPROM location (from 11110 to 11111) if there are consecutive reads.

In the first memory location, specify the MSB as the sign (0=+ and 1=-) and the seven lsb as the integer part of the tolerance. In the second memory location, all eight data bits are designated as the fractional part of the tolerance. Note that the fractional part only has a limited precision of 0.1%. For example, if the rated R=10 kΩ, the data read from address 11110 shows 0001 1100 and the data read from address 11111 shows:

0000 1111, the tolerance can be calculated as:

MSB:0=+

Next 7 MSB: 001 1100=28

8 least significant bits: 0000 1111=15×2=0.06–8

Tolerance=28.06%

Rounding tolerance = 28.1%, so

Rab actual value = 12.810 kΩ

ESD Protection of Digital Pins and Resistor Terminals

The AD5258 VDD, VLOGIC, and GND supplies define the boundary conditions for proper 3-terminal and digital input operation. Supply signals that appear on Terminal A, Terminal B, and Terminal W above VDD or GND are clamped by internal forward-biased ESD protection diodes (see Figure 40). Digital input SCL and digital input SDA are clamped to VLOGIC and GND by ESD protection diodes, as shown in Figure 41.

power-on sequence

Because the ESD protection diodes limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 40), GND/VDD/VLOGIC must be powered up before any voltage is applied to Terminal A, Terminal B, and Terminal W; Otherwise, the diodes are forward biased, energizing VDD and VLOGIC inadvertently, and potentially affecting user circuits. The ideal power-up sequence is as follows: GND, VDD, VLOGIC, digital input, then VA, VB, VW. The relative order of powering VA, VB, VW, and the digital inputs does not matter, as long as they are powered after GND, VDD, and VLOGIC.

Layout and Power Bypass

A compact, minimal lead length layout design is best. Wires to the input should be as direct as possible with minimal wire length. The ground path should have low resistance and low inductance. Also, for best stability, it is a good practice to bypass the power supply with a high quality capacitor. A 0.01µF to 0.1µF chip or chip ceramic capacitor should be used to bypass the device's power supply lines. Additionally, low ESR 1µF to 10µF tantalum or electrolytic capacitors should be used at the power supply to minimize any transients and low frequency fluctuations (see Figure 42). Additionally, the digital ground should be remotely connected to a point on the analog ground to minimize ground bounce.

Multiple devices on a bus

The AD5258 has two configurable address pins, AD0 and AD1. The state of these two pins is registered at power-up and decoded into the corresponding IC-compatible 7-bit address (see Table 5). This allows up to four devices on the bus to write or read independently. 2

show application

circuit

A feature of the AD5258 is its unique separation of the VLOGIC and VDD supply pins. The reason for this is to provide more flexibility in applications where the required supply voltage is not always available.

In particular, LCD panels usually require a VCOM voltage between 3V and 5V. A rare exception is the circuit in Figure 43, where the 5V supply powers the digital potentiometer.

Typically, only analog 14.4V and digital logic 3.3V supplies are available (see Figure 44). VDD can be tapped from the resistor string itself by placing discrete resistors above and below the digital potentiometer. Depending on the resistor value chosen, in this case, the voltage at VDD is equal to 4.8 V, allowing the wiper to operate safely to 4.8V. The current consumption of VDD does not affect the bias of this node, as it is only in the microamp range. The VLOGIC is connected to the 3.3v digital power supply of the microcontroller (MCU) because the VLOGIC will draw the required 35ma when writing to the EEPROM. Trying to power 35mA through a 70kΩ resistor is impractical; therefore, VLOGIC is not connected to the same node as VDD.

For this reason, VLogic and VDD are provided as two separate power pins that can be tied together or handled independently; VLogic provides power to the logic/EEPROM, and VDD biases the A, B, and W terminals for added flexibility sex.

For more information on this application, see the article "Simple VCOM Adjustment Using Any Logic Supply Voltage" in EDN Magazine, September 30, 2004.

Dimensions