feature

Maximum sample rate: 70MSPS; 12-bit resolution; no missing codes; total power consumption: internal reference: 1W; external reference: 937mW; CMOS process; simultaneous sample and hold; 5MHz IF 71dBFS SNR; 3.3V digital/analog Power supply; serialized LVDS output; integrated frame and bit patterns; dual LVDS clock output current options; four current modes for LVDS; pin and format compatible series; TQFP-80 PowerPAD 8482 ; components.

application

Portable Ultrasound Systems; Test Equipment; Military.

illustrate

The ADS5273 is a high performance CMOS, 70MSPS, 8-channel analog-to-digital converter (ADC). Internal references are provided to simplify system design requirements. Low power consumption allows the highest system integration density. Serial LVDS (Low Voltage Differential Signaling) outputs reduce the number of interface lines and package size.

An integrated phase-locked loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high frequency LVDS clock is used for the data serialization and transfer process. The word output of each internal ADC is serialized and transmitted MSB or LSB first. In addition to the eight data outputs, a bit clock and a word clock are sent. The bit clock is 6 times faster than the sample clock, and the word clock is the same speed as the sample clock.

The ADS5273 provides an internal reference, or can optionally use an external reference driver. The best performance is achieved with the internal reference mode.

The device is available in a PowerPAD TQFP-80 package and is specified over an operating range of -40°C to +85°C.

canonical definition

analog bandwidth

Simulate the input frequency at which the spectral power of the fundamental frequency (determined by FFT analysis) is reduced by 3dB.

Aperture delay

Enter the time delay between the rising edge of the sample clock and the actual time the sampling occurs.

Aperture uncertainty (jitter)

Sample-to-sample variation of aperture delay.

clock duty cycle

Pulse width high is the minimum amount of time that an ADCLK pulse remains in a logic "1" state to achieve rated performance. Pulse width low is the minimum time that an ADCLK pulse should remain low (logic "0"). These specifications define acceptable clock duty cycles for a given clock rate.

Differential Nonlinearity (DNL)

An ideal ADC shows code transitions that are exactly 1 LSB apart. DNL is the deviation of any single LSB transition at the digital output from the analog input processing in 1lsb steps. If the device claims to have no missing codes, it means that all possible codes ( 4096 codes for a 12-bit converter) are present over the entire working range.

Effective Number of Bits (ENOB)

ENOB is a measure of converter performance compared to theoretical limits based on quantization noise.

Integral Nonlinearity (INL)

INL is the deviation of the transfer function from a reference line measured in fractions of 1 lsb using the best straight line or best fit determined by least squares curve fit. INL is independent of the effects of offset, gain or quantization errors.

Maximum conversion rate

Minimum conversion rate

This is the minimum sample rate at which the ADC will still work.

Signal to Noise and Distortion (SINAD)

SINAD is the ratio of the fundamental power (PS) to the power (but not dc) of all other spectral components including noise (PN) and distortion (PD).

When the absolute power of the fundamental is used as a reference, SINAD is given in dBc (dB to carrier); when the power of the fundamental is extrapolated to the full-scale range of the converter, SINAD is given in dBFS (dB to full-scale) ) is given in units.

signal to noise ratio

SNR is the ratio of fundamental power (PS) to noise floor power (PN), excluding DC power and the first eight harmonics.

When the absolute power of the fundamental is used as a reference, the signal-to-noise ratio is given in dBc (decibels to carrier); when the power of the fundamental is extrapolated to the full-scale range of the converter, the signal-to-noise ratio is given in dBFS (decibels). for full scale) are given in units.

Spurious free dynamic range

The ratio of fundamental power to the other highest spectral components (spurious or harmonics). SFDR is usually given in dBc (dB to carrier).

Two-tone third-order intermodulation distortion

Two-tone IMD3 is the ratio of the power of the fundamental frequency (at frequencies f1 and f2) to the power of the worst spectral component of third-order intermodulation distortion at frequencies 2f1-f2 or 2f2-f1. IMD3 is given in dBc (dB to carrier), when the absolute power of the fundamental is used as a reference, IMD3 is given in dBc; when the power of the fundamental is extrapolated to the full-scale range of the converter, IMD3 is given in dBFS (dB to full scale) is given in units.

The encoding rate when performing the parametric test. This is the maximum sample rate for a given operation.

theory of operation

Overview

The ADS5273 is an 8-channel high-speed CMOS ADC. It consists of a high-performance sample-and-hold circuit and a 12-bit ADC. The 12 bits given by each channel are serialized and sent on a pair of pins in LVDS format. All eight channels of the ADS5273 run from a clock called ADCLK. The sample clock for each of the eight channels is generated from the input clock, using a matched clock buffer tree. The 12x clock required by the serializer is generated internally from ADCLK using a phase locked loop (PLL). A 6x and a 1x clock are also output in LVDS format, along with the data, for easy data capture. The ADS5273 operates an internally generated reference voltage trim to improve performance to accuracy. This feature eliminates the need for external routing of reference lines and improves gain matching between devices. The nominal REFT and REFB values are 1.95V and 0.95V, respectively. These values imply that external data has several advantages, such as reducing the number of output pins (saving routing space on the board), reducing power consumption, and reducing the effects of digital noise coupling to the analog circuitry within the ADS5273.

The ADS5273 is powered by two sets of power and ground. Analog power/ground devices are denoted AVDD/AVSS, and digital devices are denoted LVDD/LVSS.

drive analog input

The analog input bias is shown in Figure 35. The input is internally biased with two 600Ω resistors to enable AC coupling. A resistor greater than 20Ω in series with each input pin is recommended.

The input is sampled with a 4pF sampling capacitor. The selection capacitor of the external AC coupler determines the desired operating input frequency with the lowest attenuation. Attenuation The result of using 10nF AC coupling capacitors is that the input –1V corresponds to the zero code of the ADC and the differential input of +1V corresponds to the full scale code (4095 LSB). VCM (common mode voltage for REFT and REFB) is also available externally via a pin, nominally 1.45V.

The ADC uses a pipelined converter structure composed of a combination of multi-bit and single-unit internal stages. Each stage feeds its data into digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The pipeline structure results in a data delay of 6.5 clock cycles.

The output of the ADC is sent to the serializer

12 times the clock generated by the phase-locked loop works. The 12 data bits per channel are serialized and sent LSB first. The serializer generates a 1x clock and a 6x clock in addition to serializing the data. These clocks are generated in the same way that serialized data is generated, so these clocks remain perfectly synchronized with the data. The data and serializer's clock outputs are buffered externally using LVDS buffers. Using LVDS buffers to transfer data has several advantages externally, such as reduced output pin count (saving wiring space on the board), lower power consumption, and the suppression effect of digital noise coupling on the analog signal circuitry inside the ADS5273. The ADS5273 consists of two sets of power supplies and grounds. The analog power/ground set is represented by AVDD/AVSS, while the digital set is represented by LVDD/LVSS.

drive analog input

Analog Input Biasing The input is internally biased using two 600Ω resistors as shown in Figure 35 to enable ac coupling. Resistors greater than 20Ω are recommended in series with each input pin. The input is sampled with a 4pF sampling capacitor. The selection capacitor of the external AC coupler determines the desired operating input frequency with the lowest attenuation. Attenuation using a 10nF AC coupling capacitor results in 0.04%.

If the input is DC coupled, the common-mode voltage of the ADS5273 output driver circuit should be within ±50mV of VCM (as the output pin). It is recommended that the output common mode of the driver circuit be derived from the VCM provided by the device.

Figure 36 shows the sample and hold circuit. The circuit is divided into two working stages. During the sampling phase, the input is sampled with two nominally 4pF capacitors. The sampling circuit consists of a low-pass RC filter to filter out possible differences in noise components coupled on the input pins. The next stage is that the phase of the voltage sample on the pause capacitor is transferred (using an amplifier) to the sub-sequence pipeline ADC stage.

Input overvoltage recovery

by the ADS5273 is nominally 2.03V. The ADS5273 is designed to handle overvoltages where differential peak-to-peak voltages can exceed twice the full-scale range of the ADC. If the input is in common mode with VCM during overload (at 1.45V nominal), an overvoltage pulse input with twice the full-scale pulse amplitude is expected within three clock cycles from when the input switches from overload to zero strength. The sample-and-hold amplifier (SHA) and all amplifiers in the ADC are specifically designed for good recovery from overloaded signals.

In most applications, the ADC input consists of a differential sinusoidal input. While the pulse type signal remains in the peak overload state in its high state, the sinusoidal signal intermittently reaches the peak overload, at its minimum and maximum values. The recovery of this condition on ADC input and ADC output (to 1% of expected code full scale). This typically occurs within the second clock, when the input is driven sinusoidally with an amplitude equal to twice the ADC's differential full-scale range.

Reference circuit design

Digital beamforming algorithms rely on gain matching of all receive channels. For example, a typical system board has 12 octal ADCs. In this case, it is critical to ensure that the gain is matched, which basically requires all ADCs to see the same reference voltage. Matching references within the chip's eight channels is accomplished using an internal reference buffer. The reference voltages on each chip are adjusted during production to ensure that the reference voltages on different chips are well matched.

All bias currents required for the internal operation of the device are set by an external resistor to ground at the ISET pin. Use a 56.2kΩ resistor across ISET to generate an internal reference current of 20µA. This current is mirrored internally to generate the bias current for the internal block. Using a larger external resistor at ISET reduces the reference bias current and therefore reduces the operating power of the device. However, it is recommended that the external resistors be within 10% of the specified value of 56.2kΩ so that the internal bias margin of the various blocks is appropriate.

Buffering the internal bandgap voltage also produces a voltage called VCM which is set to midscale between REFT and REFB and is accessible on the pin. It is used as a reference voltage to derive the common mode when the input is directly coupled. It can also be used to derive the common mode voltage in external reference mode. When using internal reference mode, a 2Ω resistor (REFT and REFB) and decoupling capacitor should be added between the reference pins, as shown in Figure 37. This 2Ω resistor is not mandatory if the device is used in external reference mode.

The device also supports the use of an external voltage reference. This mode includes mandatory REFT as well as external references. In this mode, the internal reference buffer is tri-stated. The current from the eight ADCs since the conversion is coming from the external forced reference performance is slightly lower than the internal use of the reference. It should be noted that mode, VCM and ISET continue from the internal bandgap voltage, as in the internal reference mode. Therefore, ensure that the common mode voltage is externally forced to the reference voltage and within 50mV of VCM. The state PD and INT/EXT of the reference are shown in Table 1.

timing

Eight channels on the chip are input from one ADCLK. To ensure that the aperture delay and jitter are the same for all channels, a clock tree network is used to generate a single sample clock for each channel. All clock path channels are matched from source to track and hold amplifiers. This ensures that all channels have the same show and schedule. Matching using a clock tree introduces an aperture delay, defined as the actual instant between the rising edge of ADCLK and the sampling. All apertures delay channel matching to the best possible extent. However, mismatches of ±20 pS (±3) may exist. Within the same chip between the aperture instants of the eight ADCs. However, the aperture delay for ADCs on two different chips can be several 100 picoseconds apart. Another key specification is aperture jitter, defined as the uncertainty at the instant of sampling. The ingress clock path is designed to provide approximately 1ps.

Ideally, the input ADCLK should have a 50% duty cycle. However, when routing ADCLK to different onboard components, the duty cycle of ADCLK up to the ADS5273 can deviate by 50%. A smaller (or larger) duty cycle reduces the time available for each circuit's sample or hold phase and is therefore not optimal. For this reason an internal PLL is used to generate an internal clock with a duty cycle of 50%. The input sampling instant, however, is driven by an external clock and is not affected by PLL jitter. In addition to generating the 50% duty cycle clock the ADC and PLL also generate a 12x clock serializer for the ADC from the serial data stream. The use of a PLL automatically dictates that the minimum sampling rate is about 20MSPS. Phase-locked loops also require the input clock to be free-running. If the input clock is temporarily stopped (duration less than 300ns), it takes about 10 seconds for the PLL to lock to the input clock frequency.

LVDS buffer

The LVDS buffer has two current sources, as shown in Figure 38. OUTP and OUTN are externally loaded by a resistive load of about 100Ω ideally. Depending on whether the data is a 0 or a 1, the current is directed through the resistor in one direction or the other. The LVDS buffer has four current settings. The default current setting is 3.5mA, which provides a differential voltage drop of approximately ±350mV across a 100Ω resistor.

The single-ended output impedance of LVDS serializes it into a single data stream. For a clock frequency of 70MHz, the data rate output of the serializer is 840Mbps. Data is output LSB first, with register programmability allowing it to be restored to MSB first. The serializer also sends a 1x clock and a 6x clock. 6x clocks (denoted LCLKP/LCLKN) are used to synchronize the capture of LVDS data.

Deskew mode can also be enabled using register settings. This mode gives a data stream of alternating 0s and 1s that can be used to determine the relative delay between the 6x clock and output data for optimal capture. The serializer also generates a 1x clock and transfers through the LVDS buffer. The 1x clock (called ADCLKP/ADCLKN) is used to determine the start of the 12-bit data frame. Synchronous mode (enabled via register setting) gives data 6 1s after 6 0s. Using this mode, the 1x clock can be used to determine the start of the data frame. Besides deskew mode mode and sync mode mode, user can also define custom mode and output from LVDS buffer. LVDS buffers are asserted three times in power-down mode. The LVDS outputs are weakly forced to 1.2V through 10kΩ resistors (from each output pin to 1.2V).

noise coupling problem

High-speed mixed-signal to various noise coupling types. One of its main sources of noise is from serializers and output buffers. Maximize isolation of these noise sources from sensitive analog blocks. As a starting point, there are clear boundaries on the chip in the analog and digital domains. AVDD and AVSS are used to represent analog power sections, while LVDD and LVSS are used to represent digital devices. Take care to ensure minimal interaction between internal supply sets. The degree of noise coupling transferred from the digital part to the analog part depends on:

1. Effective inductive power/ground devices for each.

2. Isolated power/ground device between digital and analog. Less effective inductance of power/ground pins results in better noise rejection. For this reason, use multiple pins to drive each pin power/ground. It must also be ensured that the impedance of the ship's power and ground wires is kept to the minimum possible. Using a ground plane in the board and a decoupling capacitor between the large ground plane power supply and the ground trace is most necessary for the device's signal-to-noise ratio.

It is recommended to maintain isolation using separate power supplies to drive AVDD and LVDD, as well as AVSS and LVSS. Using LVDS buffers reduces injected noise by a considerable amount compared to CMOS buffers. Current in this LVDS buffer versus switching direction. At the same time, the low output swing, as well as the variability of the LVDS buffer, results in low noise coupling.

Power down mode

The ADS5273 has a power-down pin called the police station. Pulling PD high will cause the device to enter shutdown mode. In this mode, the reference and clock circuits and all channels are powered off. Device power consumption drops to less than 100 megawatts in this mode. In power-down mode, the internal buffers driving REFT and REFB are tri-stated and their outputs are forced to a voltage approximately equal to half the voltage on AVDD. The speed of recovery from power-down mode depends on REFT and the reference pin. For capacitors on REFT and REFB less than 1µF, the reference voltages settle to within 1% of their steady state values in less than 500µs. Individual channels can also be selectively powered off by programming registers.

The ADS5273 also has an internal circuit that monitors the status of the stopped clock. If ADCLK is stopped (or if it is running below 3MHz), this monitoring circuit generates a logic signal to put the device in a shutdown state. The power consumption of the device is thus reduced to over 100 mW when ADCLK is stopped. Recovery from such a power outage can be approximately 100 microseconds; as shown in Table 2.

reset

Use separate power supplies to drive AVDD and LVDD, and separate ground planes, after supplies stabilize, AVSS and LVSS are required. Give the device a valid reset pulse. This result is reset to default values in all internal registers. The injected noise value of 0 (inactive) can be reduced using LVDS buffers. Without reset, it is possible to compare this to a CMOS buffer, which is quite impressive. Some registers may be in a non-default state and the current in the LVDS buffer is independent of power-up. This may cause the device to switch orientations. At the same time, the low output swing acts as a fault. When reset is active, device and LVDS buffer disparity, outputs a 0 code on all channels. However, LVDS produces low noise coupling. The output clock is not affected by the reset.

Layout Design of PowerPAD Thermally Enhanced Package Circuit Board

The ADS5273 is housed in an 80-wire power strip in a thermally enhanced package. To take full advantage of the thermally efficient PowerPAD package designed, the printed circuit board (PCB) design must take this technology into account. See the PowerPAD brief SLMA004, Making PowerPAD Simple (downloadable from), which addresses the considerations when integrating a PowerPAD into a PCB design. For more details, including thermal simulation and repair procedures, see Technical Brief SLMA002, PowerPAD Thermal Enhancement Assemblies ().

Interfacing High Speed LVDS Output (SBOA104), an application report discusses the design of a simple deserializer that can deserialize LVDS output up to 840Mbps, available on the TI website (). Connecting High Speed Multichannel ADCs to XILINX FPGAs A separate application report (XAPP774) describing how to connect TI's high speed multichannel ADCs to Xilinx FPGAs via serial LVDS output can be downloaded directly from the Xilinx website.