feature

Four On-C hip Track/Hold Am clamps; simultaneous sampling of 4 C channels; fast 12-bit ADCms conversion time with 8 e/C channels; 29 kHz magnification for all four C channels; hip reference; 610 V Input range; 65V power supply.

application

Sunar; motor controller; adaptive filter; digital signal processing.

General Instructions

The AD7874 is a four-channel simultaneous sampling 12-bit data acquisition system. This section includes a high-speed 12-bit ADC, on-chip reference, on-chip clock, and four track/hold amplifiers. The latter feature allows the four input channels to be sampled simultaneously, thereby preserving the relative phase information of the four input channels, which is not possible if all four channels share a single rail/hold amplifier. This makes the AD7874 ideal for applications such as phased array sonars and AC motor controllers where relative phase information is important.

The aperture delay of the four track/hold amplifiers is small, and minimum and maximum limits are specified. This allows multiple AD7874s to sample multiple input channels simultaneously without introducing phase errors between the signals connected to multiple devices. The reference output/reference input device also allows multiple AD7874s to be driven from the same reference source.

In addition to traditional dc accuracy specifications such as linearity, full scale, and offset error, the AD7874 fully specifies dynamic performance parameters including distortion and signal-to-noise ratio.

The AD7874 is fabricated using the Analog Devices Linear Compatible CMOS (LC2MOS) process, a hybrid process that combines precision bipolar circuitry with low-power CMOS logic. The part is available in a 28-pin, 0.6-inch wide plastic or hermetic dual in-line package (DIP), a 28-terminal lead-free ceramic chip carrier (LCCC), and a 28-pin SOIC.

Product Highlights

1. Simultaneous sampling of four input channels. Four input channels, each with its own track/hold amplifier, allow simultaneous sampling of the input signal. Track/hold capture time is 2 microseconds and conversion time is 8 microseconds per channel, allowing a 29 kHz sample rate for all four channels.

2. Tight aperture delay matching.

The aperture delay of each channel is small, and the aperture delay matching between the four channels is less than 4ns. Additionally, the aperture delay specification has upper and lower bounds that allow multiple AD7874s to sample more than four channels.

3. Fast microprocessor interface.

The high-speed digital interface of the AD7874 allows direct connection to all modern 16-bit microprocessors and digital signal processors.

the term

Acquisition time

Acquisition time is the time it takes for the track/hold amplifier output to reach its final value, within ±1/2 LSB, after the falling edge of INT (the point at which track/holds returns to track mode). This includes switching delay time, spin-up time, and settling time for full-scale voltage changes.

Aperture delay

Aperture delay is defined as the time it takes for the internal switch to disconnect the holding capacitor from the input. This creates an effective delay in sampling timing. It is done by applying the step input and adjusting the CONVST input position until the output code follows the step input change.

Aperture Delay Matching

Aperture delay matching is the maximum deviation of the aperture delay across the four on-chip track/hold amplifiers.

Aperture jitter

Aperture jitter is the uncertainty in aperture delay due to internal noise and switching thresholds that vary with signal level.

rate of decline

The sag rate is the change in hold analog voltage caused by leakage current.

Isolation between channels

Inter-channel isolation is a measure of the level of cross-talk between channels. It is measured by applying a full-scale 1khz signal to the other three inputs. The numbers given are the worst case for all four channels.

SNR, THD, IMD

See the Dynamic Specifications section.

Converter Details

The AD7874 is a complete 12-bit 4-channel data acquisition system. It consists of a 12-bit successive approximation. ADC, four high-speed track/hold circuits, a four-channel analog multiplexer, and a 3-volt Zener reference. The ADC uses successive approximation techniques and is based on fast settlement, voltage switching DACs, high speed comparators, fast CMOS synthetic aperture radar and high speed logic.

Conversions are initiated on the rising edge of CONVST. All four input tracks/holds on this side go from one track to the other. The conversion is first performed on the channel 1 input voltage, then channel 2 is converted and so on. These four results are stored in an on-chip register. When all four conversions are complete, INT goes low to indicate that data can be read from these locations. The conversion sequence takes 78 or 79 rising clock edges depending on the synchronization of CONVST to CLK. Internal delay and reset time bring the total conversion time from high to low to a maximum of 32.5 MHz with an external clock of 2.5 MHz. The AD7874 uses an implicit addressing scheme in which four data words are accessed sequentially to the same memory location. The first read access channel 1 data, the second read access channel 2 data and so on. Individual data registers cannot be accessed independently.

internal reference

The AD7874 has an on-chip temperature compensated buried Zener reference that is factory trimmed to 3 V ±10 mV (see Figure 3). The reference voltage is provided at the REF OUT pin. This reference voltage can be used to provide a reference voltage for the ADC and bipolar bias circuits. This is achieved by connecting REF OUT to REF IN.

The reference can also be used as a reference for other components and is capable of supplying up to 500 microamps of current to external loads. In systems using multiple AD7874s, using the REF OUT of one device to provide REF In for the other ensures good full-scale tracking between all AD7874s. Since the AD7874 REF Ins are buffered, each AD7874 presents high impedance to the reference, so one AD7874 REF OUT can drive multiple AD7874 REF Ins.

Maximum recommended capacitance

Normal operation is 50 pF. If a reference is required for other system use, it should be separated from AGND using a parallel combination of a 200Ω resistor with a 10µF tantalum capacitor and a 0.1µF ceramic capacitor.

xref

In some applications, the user may need a system reference or some other external reference to drive the AD7874 reference input. Figure 4 shows how the AD586 5 V reference can be used to provide the 3 V reference required for the AD7874 reference.

Track Hold Amplifier

Track-and-hold amplifiers on each analog input of the AD7874 allow the ADC to accurately convert an input sine wave of 20 V pp amplitude to 12-bit accuracy. Even when the ADC is operating at its maximum throughput rate, the input bandwidth of the track/hold amplifier is greater than the Nyquist rate of the ADC. The small signal 3db cutoff frequency usually occurs at 500khz.

The four track/hold amplifiers simultaneously sample their respective input channels. The aperture delay of the track/hold circuit is small and, more importantly, well matched between the four tracks/holds on one device, and well matched between each device. This allows relative phase information between different input channels to be accurately preserved. It also allows multiple AD7874s to sample more than four channels simultaneously.

The operation of the track/hold amplifier is largely transparent to the user. Once the conversion is started, the four channels are automatically converted, there is no need to select the channel to be digitized.

analog input

The analog input for channel 1 of the AD7874 is shown in Figure 4. The analog input range is ±10 V, and the input resistance is typically 30 kΩ. The designed transcoding occurs in the middle between consecutive integer LSB values (ie 1/2 LSB, 3/2 LSB, 5/2 LSB). . . FS–3/2 LSB). The output code is 2s complement binary, 1lsb=FS/4096=20v/4096=4.88mv. The ideal input/output transfer function is shown in Figure 5.

Offset and full scale adjustment

In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. With AC coupling, offset errors in the analog domain can be eliminated. The full-scale error effect is linear and should not cause a problem as long as the input signal is within the full dynamic range of the ADC. Some applications always require the input signal to span the entire analog input dynamic range. In this application, the offset and full-scale errors must be adjusted to zero.

Figure 6 shows a circuit that can be used to adjust the offset and full-scale error on the AD7874 (channel 1 is shown for example purposes only). When adjustment is required, the offset error must be adjusted before the full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7874 when the input voltage is below 1/2 LSB of analog ground. The trimming procedure is as follows: Apply a voltage of -2.44 mV (–1/2 LSB) at V1 in Figure 6 and adjust the op amp offset voltage until the ADC output code flashes between 1111 1111 1111 and 0000 0000 0000.

Gain error can be adjusted at the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trimming procedure in both cases is as follows:

Positive full scale adjustment

A voltage of +9.9927 V (FS/2–3/2 LSBs) was applied at V1. Adjust R2 until the ADC output code flashes between 0111111111110 and 0111111111.

Negative full scale adjustment

Apply a voltage of -9.9976 V (–FS+1/2 LSB) at V1 and adjust R2 until the ADC output code flashes between 1000 0000 and 1000 0000 0001.

In systems using an external reference, an alternative to adjusting the full-scale error is to adjust the voltage at the REF in pin until the full-scale error is adjusted for any channel. Good full-scale matching of the channels will ensure small full-scale errors for the other channels.

time and control

Transform input with assertions. This CONVST input is an asynchronous input independent of the ADC clock. This is essential for applications where accurate sampling in time is important. In these applications, the signal samples must be sampled at exactly equal intervals to minimize errors or jitter due to sampling uncertainty. In these cases, the CONVST input is driven by a timer or precise clock source. Once a conversion has started, CONVST should not be asserted again until the conversion on all four channels is complete.

In applications where precise time interval sampling is not critical - cal, the CONVST pulse can be generated by a microprocessor write or read line that is gated with a decoded address (unlike the AD7874 CS address). CONVST should not be derived only from the decoded address, as a very short CONVST pulse (in some microprocessor systems, due to address bus changes at the start of the instruction cycle) can initiate a conversion.

All four channel/hold amplifiers are held from one channel to the other on the rising edge of the CONVST pulse. The four-channel/hold amplifier maintains its hold mode while converting all four channels. The rising edge of CONVST also initiates the conversion of the channel 1 input voltage (VIN1). When a conversion is completed on Channel 1, its result is stored in Data Register 1, which is one of four on-chip registers used to store the conversion result. When the result of the first conversion is stored, the conversion is initiated at the voltage held by Track/Hold 2. When a conversion is complete at the voltage held by Track/Hold 4, the result of which is stored in Data Register 4, INT goes low to indicate that the conversion process is complete.

The sequence in which channel transitions occur is handled automatically by the AD7874. This means that the user does not have to provide address lines to the AD7874 or worry about selecting which channel to digitize.

Reading data from the device consists of four read operations to the same microprocessor address. The addressing of the four on-chip data registers is again by AD 7874. The first read of the AD7874 after a conversion always accesses data from data register 1 (ie, the conversion result is input from VIN1). INT performs RD during the first read operation. The second read always accesses data from data register 2, and so on. The address pointer resets to point to the rising edge of data register 1 const. Attempts to read the AD7874 should not be attempted during conversion. The timing diagram of the AD7874 conversion sequence is shown in Figure 7.

AD7874 Dynamic Specifications

The AD7874 is specified and 100% tested to dynamic performance specifications as well as traditional DC specifications such as integral and differential nonlinearity. These AC specifications are required for signal processing applications such as phased array sonar, adaptive filters, and spectrum analysis. These applications require information about the effect of the ADC on the spectral content of the input signal. Therefore, the parameters specifying the AD7874 include signal-to-noise ratio, harmonic distortion, intermodulation distortion, and peak harmonics. These terms will be discussed in detail in the following sections.

signal to noise ratio

SNR is the signal-to-noise ratio measured at the ADC output. The signal is the rms magnitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals, excluding DC, and has a maximum value of half the sampling frequency (fs/2). The signal-to-noise ratio depends on the number of quantization levels used in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio for a sine wave input is given by:

where N is the number of digits. So for an ideal 12-bit converter, the signal-to-noise ratio is 74 dB.

The output spectrum from the ADC is evaluated by applying a very low distortion sine wave signal to the VIN input sampled at 29 kHz. Generates a Fast Fourier Transform (FFT) plot from which SNR data can be obtained. Figure 8 shows a typical 2048-point FFT plot of the AD7874BN with an input signal of 10 kHz and a sampling frequency of 29 kHz. The signal-to-noise ratio obtained from this figure is 73.2db. Harmonics should be considered when calculating the signal-to-noise ratio.

significant digits

The formula given in Equation 1 relates the signal-to-noise ratio to the number of bits. Rewriting the formula, as in Equation 2, yields a performance metric expressed in effective number of bits (N).

A device's effective number of bits can be calculated directly from its measured signal-to-noise ratio.

Figure 9 shows a typical plot of effective bits versus frequency for the AD7874BN sampled at 29 kHz. The effective number of bits is usually between 11.75 and 11.87, which corresponds to an SNR figure of 72.5db and 73.2db.

Total Harmonic Distortion (THD)

Total Harmonic Distortion (THD) is the ratio of the rms value of the harmonics to the rms value of the fundamental. For the AD7874, THD is defined as:

where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second to sixth harmonics. The THD is also derived from the FFT plot of the ADC output spectrum.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (fa and fb), any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2 , 3. ……Wait. The intermodulation term refers to the intermodulation term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

Using the CCIF standard, where two input frequencies near the top of the input bandwidth are used, the second and third order terms have different importance. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the THD specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dBs. In this case, the input consists of two equal amplitude low distortion sine waves. Figure 10 shows a typical IMD diagram for the AD7874.

Peak harmonics or spurious noise

Harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fs/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification will be determined by the largest harmonic in the spectrum, but for parts of the harmonic buried in the noise floor, the peak will be the noise peak.

AC Linear Graph

When a sine wave of a specified frequency is applied to the VIN input of the AD7874 and millions of samples are collected, a histogram showing the frequency of occurrence of each of the 4096 ADC codes can be generated. From this histogram data, a linear plot of the ac integral as shown in Figure 11 can be generated. This shows the very good integral linearity performance of the AD7874 at an input frequency of 10 kHz. The absence of large peaks in the graph shows good differential linearity. A simplified version of the formula used is outlined below:

where INL(i) is the integral linearity at code i. V(fs) and V(o) are the estimated full-scale and offset transitions, and V(i) is the estimated transition for the ith code.

The estimated transcoding points for V(i) are derived as follows:

where A is the peak signal amplitude and N is the number of histogram samples:

Microprocessor interface

The AD7874 high-speed bus timing allows direct connection to DSP processors as well as modern 16-bit microprocessors. A suitable microprocessor interface is shown in Figures 12 to 16.

AD7874–ADSP-2100 interface

Figure 12 shows the interface between the AD7874 and the ADSP-2100. Conversions are initiated using a timer which allows very precise control of the sampling instant - Neils on all 4 channels. The AD7874 INT line provides an interrupt to the ADSP2100 when a conversion is complete on all four channels. The four conversion results can then be read from the AD7874 using four consecutive reads to the same memory address. The following instruction reads one of the four results (this instruction is repeated four times to read all four results in sequence): MR0 = DM(ADC); where MR0 is the ADSP-2100 MR0 register and ADC is the AD7874 address.

AD7874–ADSP-2101/ADSP-2102 Interface

The interface shown in Figure 12 also forms the basis for the interface between the AD7874 and the ADSP-2101/ADSP-2102. The read line for the ADSP-2101/ADSP-2102 is labeled RD. In this interface, the processor's RD pulse width can be programmed using the data memory wait state control register. The instructions for reading one of the four results are as described for the ADSP-2100.

AD7874–TMS32010 interface

The interface between the AD7874 and the TMS32010 is shown in Figure 13. Conversions are started again using an external timer, and the TMS32010 interrupts when all four conversions are complete. The following instructions are used to read the conversion result from the AD7874: IN D,ADC; where D is the data memory address and ADC is the AD7874 address.

AD7874–TMS320C25 interface

Figure 14 shows the interface between the AD7874 and the TMS320C25. As with the previous two interfaces, conversions are initiated with a timer, and when the conversion sequence is complete, the processor is interrupted. The TMS320C25 does not have a separate RD output to directly drive the AD7874 RD input. This must be coupled with some logic gates by the processor STRB and R/W outputs. The RD signal is strobed with the MSC signal to provide a wait state during the read cycle required for correct interface timing. The conversion result is read from the AD7874 using the following command: IN D,ADC; where D is the data memory address and ADC is the AD7874 address.

Some applications may require that the conversion be initiated by the microprocessor rather than an external timer. One option decodes the AD7874 converter from the address bus so that a write operation starts the conversion. Data is read at the end of the transformation sequence as before. Figure 16 shows an example of initiating a conversion using this method. Note that for all interfaces, read operations should not be attempted during conversion.

AD7874–MC68000 interface

The interface between the AD7874 and the MC68000 is shown in Figure 15. As before, the transition is using an external timer. The AD7874 integer line can be used to interrupt the processor, or a software delay can ensure that the conversion has completed before attempting to read the AD7874. Due to its interrupting nature, the 68000 requires additional logic (not shown in Figure 15) to allow it to be interrupted properly. For more information on 68000 interrupts, see the 68000 User Manual.

The MC68000 AS and R/W outputs are used to generate the RD input signal of the split AD7874. CS is used to drive the 68000 DTACK input to allow the processor to perform normal read operations on the AD7874. Use the following 68000 instruction to read the conversion result: MOVE.W ADC, D0; where D0 is the 68000 D0 register and ADC is the AD7874 address.

AD7874–8086 interface

Figure 16 shows the interface between the AD7874 and the 8086 microprocessor. Unlike the previous interface example, the microprocessor initiates the conversion. This is done by combining the 8086 WR signal with the decoded address output (different from the AD7874 CS address). The AD7874 integer line is used to interrupt the microprocessor when the conversion sequence is complete. Data is read from the AD7874 using the following instruction: MOV AX,ADC; where AX is the 8086 accumulator and ADC is the AD7874 address.

Applied Vector Motor Control

The electric current of the motor can be divided into two parts: one part produces the torque, and the other part produces the magnetic flux. For optimum motor performance, these two components should be controlled independently. In traditional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the fundamental control variables. However, both torque and magnetic flux are functions of current (or voltage) and frequency. This coupling effect can degrade the performance of the motor because, for example, if the torque is increased by increasing the frequency, the magnetic flux tends to decrease.

In addition to controlling the drive and current frequency, the vector control of an AC motor also includes controlling the phase. Controlling the phase of the motor requires feedback from the position of the rotor relative to the rotating magnetic field within the motor. Using this information, the vector controller mathematically converts the three-phase drive currents into individual torque and flux components. The AD7874 has four channels of simultaneous sampling capability, making it ideal for vector motor control applications.

A block diagram of a vector motor control application using the AD7874 is shown in Figure 17. The position of the magnetic field is determined by determining the current in each phase of the motor. Only two phase currents need to be measured, because if two phases are known, a third current can be calculated. Channel 1 and Channel 2 of the AD7874 are used to digitize this information.

Simultaneous sampling is essential to maintain relative phase information between the two channels. Use a current-sensing isolation amplifier, transformer, or Hall-effect sensor between the motor and the AD7874. The rotor information is obtained by measuring the voltages at the two inputs of the motor. Channel 3 and Channel 4 of the AD7874 are used to obtain this information. The relative phase of the two channels is equally important. Use DSP microprocessor to carry out mathematical transformation and control loop calculation to the information fed back by AD7874.

Multiple AD7874

Figure 18 shows a system in which multiple AD7874s can be configured to handle multiple input channels. This type of configuration is common in applications such as sonar, radar, etc. The AD784 specifies maximum and minimum limits for aperture delay. This means that the user knows the maximum difference in sampling instants between all channels. This allows the user to maintain relative phase information between different channels.

The common read signal from the microprocessor drives the RD input of all AD7874s. Each AD7874 is assigned a unique address selected by the address decoder. The reference output of the AD7874, digital 1, is used to drive the reference input of all other AD7874s in the circuit shown in Figure 18. A single reference output pin can drive multiple AD7874 reference input pins. Alternatively, all REF-IN inputs can be driven using external or system references. A common reference ensures good full-scale tracking between all channels.

data acquisition board

Figure 20 shows the AD7874 in a data acquisition circuit. The corresponding printed circuit board (PCB) layout and silkscreen are shown in Figures 21 to 23. A 26-contact IDC connector provides a microprocessor-to-board connection.

A component gate is provided near the analog input on the PCB, which can be used to provide an antialiasing filter for the analog input channel or to provide a signal conditioning circuit. For ease of selection, four shorting headers (labeled LK1 to LK4 on the PCB) are provided on the analog inputs, one for each input. If a channel-specific shorting plug is used, the input signal is connected to a buffer amplifier that drives the ADC's analog input. If the shorting plug is omitted, wire connections can be used to connect the input signal to the PCB component grid.

The microprocessor is connected to the circuit board through the 26-contact IDC connector SKT8, and the pins are shown in Figure 19. This connector contains all data, control, and status signals for the AD7874 (except the CLK input and through SKT5 and SKT7, respectively). It also contains the decoded R/W and STRB inputs, which are required for the TMS32020 interface (also the 68000 interface, although the pin label on the 68000 is dif-ferent). Note that the AD7874 CS input must be decoded before the AD7874 evaluation board.

SKT1, SKT2, SKT3, and SKT4 provide inputs for VIN1, VIN2, VIN3, and VIN4, respectively. Assuming LK1 to LK4 are in place, these input signals are fed to four buffer amplifiers, IC1, before they are applied to the AD7874. The use of an external clock source is optional; there is a shorting header (LK5) on the AD7874 CLK input, which must be connected to –5 V (for the ADC's own internal clock) or SKT5. SKT6 and SKT7 provide reference and CONVST inputs, respectively. Shorting header LK6 provides the option of using an external reference or the ADC's own internal reference.

power connection

The PCB requires two analog power supplies and a 5v digital power supply. The analog power supplies are labeled V+ and V-. The two power supplies range from 12 V to 15 V (see the silkscreen in Figure 23). Connect to 5V digital power supply via SKT8. The +5 V and -5 V supplies required by the AD7874 are generated by voltage regulators (IC3 and IC4) on the V+ and V- supplies.

Shorting Plug Options

There are seven shorting plug options that must be set up before the board can be used. An overview is as follows:

LK1–LK4 connect the analog inputs to the buffer amplifiers. Analog inputs can also be connected to a component grid for signal conditioning.

LK5 selects the AD7874 internal clock or external clock source.

LK6 selects the AD7874 internal reference source or external reference source.

LK7 connects the AD7874 RD input directly to the RD input of the SKT8 or the decoded STRB and R/W inputs. This shorting plug setting depends on the microprocessor, for example, the TMS32020 and 68000 need to decode the RD signal.