feature

Serial digital data link requires few I/O pins; analog input track/hold functionality; 2, 4 or 8 channel input multiplexer options; address logic; 0V to 5V analog input range with single 5V No zero-scale or full-scale adjustment required; TTL/CMOS input/output compatible; on-chip 2.6V bandgap reference; 0.3" standard width 8, 14, or 20-pin dip package; 14-, 20-pin small outline package.

Main Specifications

Resolution: 8 bits; Conversion Time (fC=1MHz): 8µs (max); Power Consumption: 20mW (max); Single Supply: 5VDC (±5%); Total Unadjusted Error: ±1/2 LSB and ±1LSB; no over-temperature missing codes.

application

Digital automotive sensors; process control monitoring; remote sensing in noisy environments; instrumentation; test systems; embedded diagnostics.

General Instructions

The ADC08031 /ADC08032/ADC08034/ADC08038 are 8-bit successive approximation A/D converters with serial I/O configurable input multiplexers for up to 8 channels. This serial I/O is configured to comply with NSC MICROWIRE 8482 ; a serial data exchange standard that facilitates interfacing with COPS™ series controllers and can be easily interfacing with standard shift registers or microprocessors.

The ADC08034 and ADC08038 provide a 2.6V bandgap reference. See ADC08131, ADC08134, and ADC08138 for devices that provide guaranteed over-temperature reference voltage performance. The track/hold function allows the analog voltage to vary during the actual A/D conversion for the positive input. The analog inputs can be configured in various single-ended, differential or pseudo-differential modes. Additionally, the input voltage range can accommodate voltages as small as 1V.

Connection Diagram

Function description

Multiplexer addressing

The design of these converters utilizes a built-in sample-and-hold comparator structure that provides a differential analog input that is converted using a continuous approximation procedure.

The actual converted voltage is always the difference between the specified "+" input terminal and "-" input terminal. The polarity of each pair of input terminals represents the most positive line expected by the converter. If the specified "+" input voltage is less than the "-" input voltage, the converter will respond with an all-zero output code.

A unique input multiplexing scheme has been used to provide multiple analog channels with software configurable single-ended, differential, or pseudo-differential (which will convert the difference between voltages at any analog input and a common terminal) operation. This type of input flexibility is significantly simplified by the analog signal conditioning required in transducer-based data acquisition systems. One converter package can now handle ground-referenced and true differential inputs as well as signals with arbitrary reference voltages.

A specific input configuration is assigned during the MUX addressing sequence before starting a conversion. The MUX address selects the analog input enable, and whether this input is single-ended or differential. Differential inputs are limited to adjacent channel pairs. For example, channel 0 and channel 1 can be selected as a differential pair, but channel 0 or 1 cannot operate differentially with any other channel. In addition to selecting the differential mode, the polarity can also be selected. Channel 0 may be selected as the positive input, channel 1 as the negative input, or vice versa. The best example of this programmability is the various product options for MUX addressing codes shown in the table below.

The MUX address is transferred into the converter via the DI line. Because the ADC08031 contains only one differential input channel with fixed polarity assignment, it does not need to be addressing. The common input line (COM) on the ADC08038 can be used as a pseudo-differential input. In this mode, any other input on this pin is treated as a "-" input channel. This voltage does not have to be analog ground; it can be all inputs. This feature is most useful in single-supply applications where analog circuits may be biased to a potential other than ground and the output signals are all referenced to this potential.

Since the input configuration is software controlled, it can be modified as needed before each conversion. One channel can be treated as a single-ended ground-referenced input for one conversion; it can then be reconfigured to be part of another converted differential channel. Figure 1 illustrates the input flexibility that can be achieved.

The analog input voltage of each channel can go from 50mV below ground to 50mV above VCC (typically 5V) without degrading conversion accuracy.

2.0 digital interface

One of the most important features of these converters is their serial data link to the control processor. Using the serial communication format provides two very important system improvements; it allows many functions to be contained in a small package, and it eliminates the transmission of low-level analog signals by positioning the converter on the analog sensor; Noise immune digital data is transmitted back to the main processor.

To understand the operation of these converters, it is best to refer to the timing and functional block diagrams and follow the complete conversion sequence. For clarity, separate timing diagrams are shown for each device.

1. Start a conversion by pulling the CS (chip select) line low. This line must remain low throughout the conversion process. The converter is now waiting for the start bit and its MUX assignment word.

2. On each rising edge of the clock, the state of the data in the (DI) row is clocked into the MUX address shift register.

The start bit is the first logical "1" that occurs on this line (all leading zeros are ignored). After the start bit, the converter expects the next 2 to 4 bits to be the MUX assignment word.

3. When the start shift is moved to the start position in the MUX register, the input channel has been allocated and the conversion is about to start. The interval 1/2 clock cycle (nothing happens) is automatically inserted to allow the selected MUX channel to be fixed. At this point, the SARS line goes high, indicating that a conversion is in progress, and the DI line is disabled (it no longer accepts data).

4. The Data Out (DO) line is now out of tri-state and provides a leading zero MUX settling time for one clock cycle.

5. During conversion, the output of the SAR comparator indicates whether the analog input is greater (high) or less than (low) a series of continuous voltages (first 5 bits) and a resistive ladder (last 3 bits) generated inside the rated capacitor array. The output of the comparator is sent to the falling edge of CLK after each comparison. This data is the result of the conversion (MSB first) and can be read immediately by the processor.

6. After 8 clock cycles, the conversion is complete. The SARS line returns low to represent 1/2 the clock cycle.

7. The stored data in the successive approximation register is loaded into the internal shift register. If the programmer wants the data to be available in LSB-first format [this makes use of the Shift Enable (SE) control line]. Turn on ADC08038 SE line pinout, if held high LSB value remains valid on DO line. when? SE is forced to turn down the data and is first clocked by LSB. On devices that do not include SE control lines, the LSB takes precedence and the MSB flows first. The DO line then goes low and remains low until CS returns high. The ADC08031 is an exception because its data is only formatted in MSB first.

8. When the CS line is high, all internal registers are cleared to meet the t selection requirements. See "Data Input Timing" under "Timing Diagram". If another transition is required, CS must do a high-to-low transition followed by the address information. The DI and DO lines can be tied together and controlled via a single line of bidirectional processor I/O bits. This is possible because the DI input is only "seeing" when the DO line is still in a high impedance state.

3.0 Reference Factors

The voltage VREFIN applied to the reference input of these converters defines the voltage range of the analog input (the difference between VIN (max) and VIN (min) over which 256 possible output codes apply .This device can be used for both ratiometric measurement applications and systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resistance (as low as 1.3kΩ). This pin is used for successive approximation conversion on top of the resistor divider string and capacitor array.

In a ratiometric measurement system, the analog input voltage is proportional to the a/D reference voltage. This voltage is usually the system power supply, so the VREFIN pin can be tied to VCC (done inside the ADC08032) This technique relaxes the stability requirements of the system reference when the analog input and A/D reference move simultaneously, at a given input condition Keep the same output code below.

For absolute accuracy, the reference pin can be biased with a time and temperature stable voltage source when the analog input varies between very specific voltage limits. For the ADC08034 and ADC08038, a bandgap reference of 2.6V (Note 8) is connected to VREFOUT. This can be tied to VREFIN. A 100µF capacitor is recommended to bypass VREFOUT. The LM385 and LM336 reference diodes are good low current devices to use with these converters.

The maximum reference value is limited to the VCC supply voltage. However, the minimum value can be very small (see Typical Performance Characteristics) to allow direct conversion of the sensor output, providing an output span of less than 5V. Due to the increased sensitivity of the converter (1lsb is equal to VREF/256), special attention must be paid to noise pickup, circuit layout, and system error voltage sources when operating with a reduced span.

4.0 Analog Input

The most important feature of these converters is that they can be located at an analog signal source and communicate with a control processor with a high noise immunity serial bit stream over a few wires. This in itself greatly reduces the circuitry to maintain the accuracy of analog signals that are otherwise most susceptible to noise pickup. However, for analog inputs, if the input is noisy at the beginning, or possibly on a large common-mode voltage, there are several words in sequence.

The differential inputs of these converters actually reduce the effects of common-mode input noise, which is a signal that is common to both the selected "+" and "-" inputs for one converter (60 Hertz is the most typical). The time interval between sampling the "+" input and the "-" input is /2 of the clock period. During this short time interval, changes in the common-mode voltage can cause conversion errors. For a sinusoidal common-mode signal, this error is:

where fCM is the frequency of the common-mode signal, VPEAK is its peak voltage value, and fCLK is the A/D clock frequency.

For a 60Hz common mode signal to produce an LSB error of 4 (5MV), the converter is operating at 250kHz and it must peak at 663V, which would be more than allowed because it exceeds the maximum analog input limit.

The source resistance limit is important for the DC leakage current into the multiplexer. Bypass capacitors should not be used if the supply resistance is greater than 1kΩ. Worst-case leakage current over temperature of ±1µA will result in a 1mV input error with a 1kΩ source resistance. If a high-impedance signal source is required, an op amp RC active low-pass filter can provide impedance buffering and noise filtering.

5.0 Optional Adjustments

5.1 Zero error

The zero point of the A/D does not need to be adjusted. Zero offset is possible if the minimum analog input voltage value VIN(MIN) is not grounded. The converter can be made - by biasing any VIN (-) input to this VIN (minimum) value, enter a 0000 numeric code for this minimum input voltage. This takes advantage of the differential mode operation of the A/D.

The zero error of the A/D converter is related to the position of the first riser of the transfer function and can be measured by grounding the VIN (-) input and applying a small positive voltage to the VIN (VIN) input. Zero error is the difference between the actual DC input voltage, 0000 to 0000 0001 necessary to convert the output digital code from 0000, and the ideal /2 LSB value (9.8mV at /2 LSB = 11VREF = 5.000VDC).

5.2 Full scale

Full-scale adjustment can be done by applying a differential input voltage (1/2lsb lower from the desired analog full-scale voltage range), then adjusting the size of the VREFIN input (or VCC of the ADC08032) for the digital output codes from 1111110 to 1111111.

5.3 Adjust any analog input voltage range

If the analog zero voltage of the A/D is moved away from ground (for example, to accommodate an ungrounded analog input signal), this new zero reference

It should be properly adjusted first. Apply a VIN (+) voltage equal to the desired zero reference voltage plus /2 LSB (where 1 LSB=analog span/256 is used to calculate the LSB of the desired analog span) to the selected "+" input, The zero reference voltage at the corresponding "-" input should then be adjusted to obtain a code transition of 00HEX to 01HEX.

A voltage shall be applied to the VIN (-) input [with the appropriate VIN (-) voltage applied], given by:

Where: VMAX=high end of analog input range and VMIN=low end of analog range (offset zero). (Both are ground referenced.) The VREFIN (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustment process.

application

"Standalone" connection for ADC08038 evaluation

(1) Use one more wire than the load cell itself;

(2) Two miniature DIPs can be installed in the load cell of the digital output sensor;

(3), electronic offset and gain fine-tuning - relax the mechanical specifications of the measurement factor and offset;

(4) The low-level unit output is immediately converted to high noise immunity.

(1) All power supplies are powered by the loop;

(2), 1500V output isolation.

(1), no need for remote power supply;

(2), 1500V isolation.