feature

256 -bit multiple independently programmable channels; AD5204-4-channel; AD5206-6-channel; potentiometer replacement 10 kV, 50 kV, 100 kV; 3-wire SPI compatible serial data input; +2.7 V to + 5.5 V single supply; 62.7 V dual supply; operating; mid-scale preset turned on.

application

Replacement of mechanical potentiometers; instrumentation: gain, offset adjustment; programmable voltage to current conversion; programmable filters, delays, time constants; line impedance matching.

General Instructions

The AD5204/AD5206 provide quad/six-channel, 256-bit digitally controlled variable resistor (VR) devices. These devices perform with potentiometers or variable resistors. Each channel of the AD5204/

The AD5206 contains a fixed resistor with a tapped wiper contact. The fixed resistance value at a point determined by a digital code is loaded into an SPI-compatible serial input register. The resistance between the wiper and the fixed resistor is relative to the transmission to the VR latch. The variable resistor provides a fully programmable resistance value between the A terminal and the wiper or the B terminal and the wiper. The nominal temperature coefficient of a 10 kΩ, 50 kΩ or 100 kΩ resistor at the fixed A to B terminals is 700 ppm/°C.

Each VR has its own VR latch that holds the programmed resistor value. These VR latches are internally updated from a standard loaded serial to parallel shift register three wire serial input digital interface. The 11 data bits form the data word into the serial input register. The first three bits are decoded to determine which VR latch will be strobed when CS returns to logic high. The serial data output pin on the other side of the serial register (AD5204 only) allows simple daisy-chaining of additional external decoding logic in multiple VR applications.

An optional reset (PR) pin forces all AD5204 wipers to the mid-scale position by loading 80 hours into the VR latch. The AD5204/AD5206 are available in two surface mount (SOL-24), TSSOP-24 and 24 lead plastic dipping packages. All components are guaranteed to operate over an extended industrial temperature range of -40°C to +85°C. For additional single, dual, and quad devices, see the AD8400/AD8402/AD8403 products.

Typical performance characteristics

operate

The AD5204/AD5206 provide a quad/six-channel, 256-bit digitally controlled variable resistor (VR) device. Change the programmed VR settings by entering an 11-bit serial data word into the SDI (serial data input) pin. The format of this data word is three address bits, MSB first, followed by eight data bits, MSB first. Table 1 provides the serial register data word format.

The AD5204/AD5206 address assignments are shown in Table 4, the locations of the virtual reality latches (from B7 to B0) used to decode the received serial register data. VR outputs can be randomly changed one at a time. The AD5204 simplifies fault state recovery at power-up by asserting the PR pin preset to midscale. Both parts have a built-in power-up preset that keeps the wipers at a preset mid-scale state when powered up. In addition, the AD5204 includes a power-down SHDN pin that puts the RDAC in a zero-power state with terminals Ax open and wiper Wx connected to Bx, consuming only leakage current in virtual reality configurations. In shutdown mode, the VR latch setting remains unchanged, so when returning from power shutdown to operational mode, the VR setting will return to its previous resistance value.

Variable Resistor Rheostat Operation Programming

The nominal resistance values of the RDAC between terminals A and B are 10 kΩ, 50 kΩ, and 100 kΩ, respectively. The last digits of the part number determine the nominal resistance value, eg 10 kΩ=10; 100 kΩ=100. The nominal resistance (RAB) of the VR has 256 contacts connected through the wiper terminal and the B terminal contact. The 8-bit data word in the RDAC latch is decoded to select one of 256 possible settings. The first connection of the wiper starts from the B terminal of the data 00H. The contact resistance of the wiper connected to the B terminal is 45Ω. The second connection (10 kΩ part) is the first tap point for Data 01H at 84Ω[=RBA(nominal resistance)/256+RW=84Ω+45Ω]. The third connection is the next tap point for data 02H representing 78+45=123Ω. Each LSB data value increase will move the wiper up the resistor ladder until the last tap point reaches 8486 at 10006;. The wiper cannot be directly connected to the A terminal. A simplified diagram of the equivalent RDAC circuit is shown in Figure 16.

The general transfer equation to determine the digitally programmed output resistance between Wx and Bx is:

where Dx is the data contained in the 8-bit RDACx latch and RBA is the nominal end-to-end resistance.

For example, when VB=0V and one terminal is open, the following output resistance values (for a 10K potentiometer) will be set for the following RDAC latch code:

Note that there is a finite wiper resistance of 45Ω under zero-scale conditions. It should be noted that the current between W and B is limited to a maximum of 20 mA in this state to avoid degradation or possible damage to the internal switch contacts.

Like the mechanical potentiometer that the RDAC replaces, it is completely symmetrical. The resistance between wiper W and terminal A produces a digitally controlled resistance RWA. When using these terminals, the B terminal should be tied to the wiper. Setting the resistance value of RWA starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general transport equation for this operation is:

where Dx is the data contained in the 8-bit RDACx latch and is the nominal end-to-end resistance. For example, when VA = 0V and the B terminal is connected to wiper W, the following output resistance values will be set for the following RDAC latch code:

The typical distribution of RBA is within ±1%. However, device-to-device matching is process batch dependent with ±30% variation. RBA has a temperature coefficient of 700 ppm/°C as a function of temperature.

Program Potentiometer Divider Voltage Output Operation

Digital potentiometers tend to generate an output voltage proportional to the input voltage applied to a given terminal. For example, connecting one terminal to +5 V and B terminal to ground produces an output voltage at the wiper, which can be anything from zero volts up to a maximum of 1 LSB less than +5 V. Each LSB voltage is equal to the voltage applied on terminal AB divided by the 256 position resolution of the potentiometer divider. For any given input voltage applied across terminal AB, the general equation defining the output voltage with respect to ground is:

The operation of the digital potentiometer in voltage divider mode allows for more precise operation when the temperature is too high. Here the output voltage depends on the ratio of the internal resistances rather than the absolute value, so the drift increases to 15ppm/°C.

digital interface

The AD5204/AD5206 contain a standard three-wire serial input control interface. The three inputs are Clock (CLK), CS and Serial Data Input (SDI). The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work fine. If a mechanical switch is used for product evaluation, a trigger or other suitable method should be used to remove the shock. Figure 17 shows more details of the internal digital circuitry. When CS is activated, the low clock loads data into the serial register on each positive clock edge, see Table IV. When using positive (VDD) and negative (VSS) supply voltages, the logic levels are still referenced to digital ground (GND).

The Serial Data Out (SDO) pin contains an open-drain N-channel FET. This output requires a pull-up resistor in order to transfer data to the SDI pin of the next package. The pull-up resistor termination voltage may be greater than the VDD supply for the AD5204 SDO output device, for example, the AD5204 can operate at VDD = 3.3 V and the pull-up for the next device interface can be set to +5 V. This allows multiple RDACs to be cascaded from a single processor serial data line. When using a pull-up resistor connected to the SDI pin of the following devices in series, the clock period needs to be increased. The capacitive loading of the daisy-chain nodes SDO-SDI between devices must be considered for successful data transfer. When daisy-chaining is used, CS should be held low until all bits of each packet are clocked into their respective serial registers to ensure that the address and data bits are in the correct decoding positions. If two AD5204 quad RDACs were daisy-chained, this would require a 22-bit address and data in the word format provided in Table I. During shutdown (SHDN), the SDO output pin is forced off (logic high state) to disable power dissipation in the pull-up resistor. The schematic diagram of the equivalent SDO output circuit is shown in Figure 19.

The data settings and data retention times in the specification table determine the data validity time requirements. When CS returns high, the last 11 bits of the data word entered into the serial register remain unchanged. At the same time, CS goes high, which will enable the address decoder to enable one of the four or six positive edge-triggered RDAC latches, see Figure 18 for details.

The target RDAC latch is loaded with the last 8 bits of the serial data word, completing a DAC update. Four separate 8-bit data words must be entered to change all four VR settings.

All digital pins are protected with series input resistors and parallel Zener ESD structures, as shown in Figure 20. Applicable to digital pins CS, SDI, SDO, PR, SHDN, CLK.