DRAM makers are entering the next phase of expansion, but they face some challenges as memory technology approaches its physical limits.

DRAM is used for the main memory in the system, and today's most advanced devices are based on processes around 18nm to 15nm. The physical limit of DRAM is about 10nm. R&D is working to expand the technology and eventually replace it with new storage types.

However, so far, there is no direct alternative. Vendors will continue to scale DRAM and squeeze more performance until new solutions are adopted, despite the incremental steps of the current 1xnm node regime. And at future nodes, some, but not all, DRAM manufacturers will make a major transition from traditional lithography to extreme ultraviolet (EUV) lithography.

With or without EUV, DRAM suppliers face higher costs and other challenges. However, DRAM is a critical part of the storage/storage hierarchy in the system. In the first level of the hierarchy, SRAM is integrated into the processor for fast data access. The next layer of DRAM is used for main memory.

The DRAM industry is a huge and tough market. DRAM suppliers are in a slump due to market price pressures. However, OEMs still want faster DRAM with greater bandwidth to keep up with the onslaught of new data-intensive applications such as 5G and machine learning.

In response, DRAM suppliers are moving towards new and faster bandwidth specifications. But vendors are no longer scaling up or down DRAM at the traditional pace, which is roughly 30 percent DRAM at each node. In fact, DRAM scaling is slowing down, which affects area density and cost. In DRAM, nodes are designated by the active or bulk half-pitch of the memory cells.

Today, suppliers are delivering three advanced DRAM products in the 1xnm node mechanism. These three generations of DRAM did not specify a digital node. The industry refers to them simply as 1xnm, 1ynm and 1znm.

Then, in R&D, the supplier has expanded the roadmap for three more generations of DRAM, all of which are 1xnm nodes. These are called 1anm, 1bnm and 1cnm. 1anm DRAM is scheduled to launch in 2021 or earlier.

All in all, DRAM has seen only modest gains in scaling and is stuck at the 1xnm node. But contrary to popular belief, DRAM is not losing momentum. "We're not done, we don't think the roadmap is completely over," said Debra Bell, senior director of DRAM product engineering at Micron Technology. "We have a clear line of sight for a few years, and we have other ideas. We are discussing and evaluating that."

Nonetheless, the industry faces several challenges in scaling this memory. It is unclear whether DRAM can scale beyond 10nm. Still, there is plenty of frenetic activity on this stage:

DRAM suppliers from China will enter the market this year.
Vendors are shipping DDR5 DRAM with the next interface specification, called DDR5, which can speed up data transfer rates in devices.
At future DRAM nodes, Samsung and SK Hynix plan to use EUV for DRAM production. However, Micron plans to scale today's advanced lithography technology on advanced DRAM nodes.
In R&D, manufacturers are working on technologies to extend DRAM beyond 10nm. In addition, DRAM vendors are developing several new memories that can replace DRAM and flash memory.

DRAM Outlook With the prolonged downturn in the IC market, global DRAM sales are expected to reach $ 62 billion in 2019, down from $ 99.4 billion in 2018. According to VLSI Research, the overall IC market is expected to decline by 12.9% in 2019.

But now the foundry business is heating up, showing signs of recovery. "On the DRAM side, we're going to recover very quickly next year," said Handel Jones, chief executive of IBS. "What's happening is prices are stabilizing."

Additionally, DRAM continues to grow in systems such as servers and smartphones. Micron said the average DRAM content in a smartphone will increase from 3GB in 2018 to 4GB in 2019. This growth is fueled by the explosion of AI, data and video that requires more memory to help store and transmit information in systems.

Meanwhile, in the DRAM market, Samsung led with a 45.5% share in the second quarter of 2019, followed by SK Hynix (28.7%) and Micron (20.5%), according to TrendForce. Several Taiwanese DRAM suppliers have a small share.

In 2019, Chinese DRAM suppliers will enter the market, but will not be a factor for some time. Mainland Chinese supplier Changxin Storage Technology Co., Ltd. will mass-produce DRAM by the end of the year. Another company, Tsinghua Unigroup, is also actively developing the DRAM business.

However, DRAM is a critical device in the system. DRAM is fast and cheap, but it also has some drawbacks. DRAM and SRAM are volatile storage technologies, which means they lose data when system power is turned off. Flash memory, by contrast, is non-volatile, which means it retains data when the system is shut down.

DRAM itself is based on a one transistor, one capacitor (1T1C) memory cell architecture. Data is stored as electric charge in a capacitor, which is designated as a "0" or "1". Transistors control access to data.

The tiny capacitance design of DRAM makes it ideal for packing numerous memory cells into a small area for high density and high storage capacity. In fact, billions of DRAM cells can be packed onto a single memory chip," explained Alex Yoon, senior technical director at Lam Research.

DRAM cells are organized in a fixed manner. These cells are arranged in rows and have bit line structures that connect to memory addresses called word lines. The address provides a way to identify where data is stored, and a word line forms an electrical path that enables all memory cells on that row to be activated simultaneously for storage (write) or retrieval (read). "

Figure 1: Individual memory cells and arrays.

However, over time, when the transistor is turned off, the capacitor will leak or discharge. Therefore, the data stored in the capacitor must be refreshed every 64 milliseconds, which consumes system power.

It is also becoming increasingly difficult to scale or shrink DRAM cells on each node. "With DRAM, geometric lateral scaling continues, but it is slowing down and, like 3D NAND, further material innovation is required," Gill Lee, managing director of memory technology at Applied Materials, said in a blog post.

Scaling of capacitors is an obstacle, and aspect ratio is a challenge. Another key scaling challenge for DRAM is charge sharing from capacitors to digit lines. It's a combination of your timing specs, how much time you need to move the charge onto the number line, and then how long you can make the number line. All of these factors affect scale, and the challenges it brings.

DRAM is based on a stacked capacitor architecture in which capacitors are connected and reside on recessed channel array transistor structures.

Capacitors are vertical cylindrical structures. Inside the cylinder, the capacitor incorporates a metal-insulator-metal (MIM) material stack. The insulator is based on a zirconium dioxide high-k material, allowing the structure to maintain its capacitance at low leakage.

In the DRAM manufacturing process, transistors are fabricated first, followed by capacitors. At each node, the goal is to maintain or increase the volume inside the cylindrical capacitor. But at each node, the capacitor shrinks, which can lead to a reduction in volume inside the structure. This equates to a smaller cell capacitance in the storage capacitor.

Under the 20nm process, the industry has encountered obstacles in scaling capacitors. In response, Samsung developed a new 20nm cellular capacitor cell layout technology.

Traditionally, tiny circular capacitor cells are placed side by side on the surface of the structure. In contrast, Samsung staggered the capacitive cells on the surface, similar to a honeycomb layout. This allows the use of taller capacitors with larger diameters. Using the same dielectric material, the cell capacitance of the honeycomb structure is 21% larger than the previous version.

To fabricate these structures in the factory, Samsung used a 193nm immersion lithography and self-aligned double patterning (SADP) process. The holes are patterned on the surface and then etched. Repeat the process. Metals are deposited and then high-k materials are deposited using atomic layer deposition (ALD).
Extended DRAM

Using these and other technologies in the fab, Samsung, Micron, and SK Hynix scaled DRAM and moved beyond 20nm.

It's not easy. For example, lining up capacitor holes is a challenge. Etching capacitors at high aspect ratios is also difficult. "ALD and dry etching are difficult," said TechInsights analyst Jeongdong Choe. "But very thin and uniform high-k dielectric deposition is becoming increasingly important on scaled-down DRAM cell arrays."

Starting in 2016, suppliers started adopting the 1xnm node system, where suppliers have three DRAM products (1xnm, 1ynm and 1znm) on the roadmap. Originally, the 1xnm node was defined as having 17nm to 19nm DRAM, 1ynm was 14nm to 16nm, and 1znm was 11nm to 13nm.

Today, some vendors have relaxed their extension specifications, causing some confusion in the market. Some DRAMs meet these specifications, while others do not. On top of that, the DRAM cell size is slightly different, around 6F2. The cell size is equal to the size of the feature (F) times the square of 4.

In general, vendors are moving down the 1xnm node system incrementally, sometimes nanometer by nanometer. Even so, suppliers can still reduce die size to some extent.

In 2016, Samsung released the industry's first 1xnm DRAM, or 18nm device. 8Gbit devices are 30% faster than 2xnm devices and consume less power. It also contains the DDR4 interface standard. Double Data Rate (DDR) technology transfers data twice per clock cycle of the device. DDR4 runs at a maximum speed of 3200Mbps.

Today, at the same time, DRAM suppliers are scaling equipment to the next node, 1ynm. 1nm DRAMs, typically based on 15nm and above processes, will account for the majority of shipments this year.

SK Hynix recently introduced 16Gbit 1ynm DRAM, which is twice the density of the previous 8Gbit version. The device also features the new DDR5 interface standard.

Initially, DDR5 supports 5200Mbps, which is 60% faster than DDR4. DDR5 can support up to 6,400Mbps.

Other companies are also shipping DDR5 DRAM. The mobile version is called LPDDR5. DDR4 is still the mainstream technology, although DDR5/LPDDR5 is needed for a number of reasons.

Over the years, processor vendors have turned to multi-core CPU architectures. However, the per-cell memory bandwidth has barely kept up.

OEMs want faster data transfer rates from DRAM. That's where DDR5 fits in. "Here, you get bandwidth and capacity. We want to be able to scale with CPU cores. Think about CPU core count. It's gone up about 8x over the past decade. Obviously, memory has to keep up with the trends. overall computing performance,” Jim Elliott, Samsung’s senior vice president of sales and marketing, said in a recent presentation.

Meanwhile, the next battleground takes place at the next node - 1znm. Micron was the first supplier to ship 1znm DRAM, followed by Samsung and SK Hynix. These devices are based on the DDR4 or DDR5 specification.

Every vendor claims leadership at 1znm. But not all parts are the same, and scaling specs vary.

In addition to 1znm, vendors have more than three layers of DRAM (1anm, 1bnm, and 1cnm) on the roadmap. The details of these parts, which are still in the 1xnm node state, have not been disclosed by the supplier.

Vendors have taken different paths at nodes from 1anm and beyond. At those nodes, features are smaller and have more mask layers. To simplify the process, the DRAM industry is bringing EUV into production for the first time.

For example, SK Hynix plans to use EUV at 1anm, which will be available in 2021. "Samsung completed EUV testing of DRAM at 1z. However, they won't use EUV for 1z volume production. Instead, they may be able to use it for 1a or 1b volume products," TechInsights' Choe said.

EUV lithography machines use the 13.5nm wavelength, and EUV is a complex technology that takes longer than it takes to go into production.

More recently, though, Samsung and TSMC have invested in EUV production at the 7nm logic node, while R&D is at 5nm. DRAM is the next product of EUV. "With EUV, you get better fidelity. The more you stack up these mask layers, the blurrier you get," said Dan Hutcheson, CEO of VLSI Research.

However, not everyone is turning to EUV. On advanced DRAM nodes, Micron plans to expand 193nm immersion lithography and SADP to 1bnm.

It's not a big surprise. Micron is known for extending a given lithography technology as long as possible. "They've learned how to use tools extremely sparingly, and how to get more life out of them," said VLSI's Hutcheson. "They push themselves harder than anyone else."

Scaling DRAM will require more than EUV. Today's 1T1C DRAMs may stretch out for a few more years, but may run out in the 12nm to 10nm range.

Therefore, the industry is looking for ways to scale DRAM beyond 10nm with a 4F2 cell size. "Vertical gates as well as capacitorless 1T DRAM cells are candidates for 4F2," said TechInsights' Choe.

There are some challenges here, especially for vertical gate channel transistors like 3D structures. "The problem is wordline-to-wordline coupling and bitline-to-bitline coupling," Samsung chief engineer Dongsoo Woo said in a recent presentation.
Alternatives to DRAM

Meanwhile, over the years, the industry has been developing several next-generation memory types that can replace DRAM and flash.

Today, vendors are shipping phase-change memory (PCM), ReRAM, and STT-MRAM. Other memory technologies are also in development.

Next-generation memory is fast, non-volatile and has unlimited endurance. But these new memories also rely on exotic materials and complex switching mechanisms, so they will take longer to develop. Also, the new memory types are more expensive.

Each new memory type is different. PCM stores information in amorphous and crystalline phases. STT-MRAM exploits the magnetism of electron spins. ReRAM works by changing the resistance of the material.

Today, PCM and STT-MRAM devices are used in some parts of SSDs. In some but not all parts of the system, they replace DRAM. So it's safe to say that they haven't completely replaced DRAM.

"Right now, we don't see any next-generation memory that can directly replace DRAM," said David Hideo Uriu, director of product marketing at UMC. "We do see replacement of SRAM by using MRAM. But for the goal of lasting replacement of DRAM, we can only see to a "hybrid cache" DRAM/MRAM component."

STT-MRAM itself is making progress. “MRAM technology will continue to improve and move closer to the goal of persistent memory. MRAM is the technology that comes closest to DRAM in speed and performance.” Given that the speed at which data is read is close to that of DRAM, some applications may be able to use it as a alternatives. Again, in "hybrid" form, DRAM would be used to cache MRAM storage areas and improve performance, replacing DRAM in some applications.