feature

Low power, smallest pin compatible, dual nano DAC; AD5627R /AD5647R/AD5667R; 12-/14-/16-bit on-chip 1.25 V/2.5 V, 5 ppm/°C reference; AD5627/AD5667; 12-/16-bit; External reference only; 3 mm x 3 mm LFCSP and 10-lead MSOP; 2.7 V to 5.5 V supply; monotonic by design; power-on reset to zero-scale power-down per channel; hardware LDAC and CLR functions; I2C-compatible serial interface supports standards ( 100 kHz), Fast ( 400 kHz) and High Speed (3.4 MHz) modes.

application

Process Control; Data Acquisition Systems; Portable Battery-Powered Instruments; Digital Gain and Offset Adjustment; Programmable Voltage and Current Sources; Programmable Attenuators.

General Instructions

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 of the nanoDAC family are low power, dual-, 12-, 14-, and 16-bit buffered voltage output digital-to-analog converters (DACs) with or without an on-chip reference. All devices operate from a single 2.7V to 5.5V supply, are guaranteed monotonic by design, and feature an IC-compatible serial interface.

The AD5627R/AD5647R/AD5667R have an on-chip reference.

The AD5627RBCPZ, AD5647RBCPZ, and AD5667RBCPZ have a 1.25 V, 5 ppm/°C reference, giving a 2.5 V full-scale output range; the AD5627RBRMZ and AD5667RBRMZ have a 2.5 V, 5 ppm/°C reference, giving a 5 V full-scale output range. The chip reference is turned off at power-up, allowing the use of an external reference. Internal references are enabled by software writing. The AD5667 and AD5627 require an external reference voltage to set the output range of the DAC.

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 include a power-on reset circuit that ensures that the DAC output powers up to 0v and remains there until a valid write occurs.

The device includes a per-channel power-down feature that reduces the device's current consumption to 480Na at 5V and provides a software-selectable output load in power-down mode. The device has low power consumption during normal operation, making it ideal for portable battery-operated devices. On-chip precision output amplifiers achieve rail-to-rail output swing.

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 use a 2-wire IC-compatible serial interface and operate in standard (100 kHz), fast (400 kHz), and high-speed (3.4 MHz) modes.

the term

Relative Accuracy or Integral Nonlinearity For a DAC, the relative accuracy or integral nonlinearity is the maximum deviation measured in the LSBs from a straight line through the endpoints of the DAC transfer function.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. The specified differential nonlinearity ±1 LSB maximum guarantees monotonicity. The monotonicity of the DAC is guaranteed by design.

Zero code error

A zero code error is a measure of the output error when the zero scale (0x0000) is loaded into the DAC register. Ideally, the output should be 0V. Due to the combination of offset errors in the DAC and output amplifier, the output of the DAC cannot go below 0V, so the zero code error is always positive in the AD5667R. Zero-code errors are expressed in millivolts.

full scale error

Full-scale error is a measure of the output error when the full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V-1 LSB. Full-scale error is expressed as a percentage of full-scale range (FSR).

gain error

Gain error is a measure of DAC span error. It is the deviation of the slope of the DAC transfer characteristic from the ideal, expressed in FSR%.

Zero code error drift

Zero code error drift is a measure of the change in zero code error with temperature expressed in microvolts per degree Celsius.

Gain temperature coefficient

Gain temperature coefficient is a measure of gain error as a function of temperature. Expressed in parts per million FSR/°C.

offset error

Offset error is a measure of the difference between V (actual) and V (ideal) expressed in mV in the linear region of the transfer function. The offset error is measured on the AD5667R and the DAC register is loaded with code 512 . It can be negative or positive.

DC Power Supply Rejection Ratio (PSRR) DC-PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. The unit is decibel. VREF remains at 2v and VDD varies by ±10%.

Output voltage settling time

Output voltage settling time is the time required for the DAC output to settle to a specified level with a 1/4 to 3/4 full-scale input change, measured from the rising edge of the stop condition.

Digital-to-analog fault pulse

A digital-to-analog fault pulse is a pulse injected into the analog output when the input code in the DAC register changes state. It is usually designated as a fault region in nV-s, measured when the digital input code is changed by 1lsb at the major carry transition (0x7FFF to 0x8000).

digital feedthrough

Digital feedthrough is a measurement of the pulses injected into the DAC's analog output from the DAC's digital input, but when the DAC output is not being updated. It is specified in nV-s and is measured by a full-scale code change on the data bus, i.e. from 0 to 1 and vice versa.

reference feedthrough

Reference feedthrough is the ratio of the signal amplitude at the DAC output to the reference input when the DAC output is not being updated. Expressed in decibels.

Output Noise Spectral Density

The output noise spectral density is the random noise generated inside the measurement. Random noise is characterized by its spectral density. It is measured by loading the DAC to midscale and measuring the noise at the output. The unit of measurement is nV/√Hz.

DC crosstalk

DC crosstalk is the DC change in the output level of one DAC as the output of another DAC changes. It is measured by the full-scale output change of one DAC (or soft power off and on) while monitoring the other DAC held at mid-scale. Expressed in μV.

DC crosstalk caused by load current changes is a way to measure the effect of a change in load current on one DAC on another DAC held at midscale. Expressed in microvolts/mA.

digital crosstalk

Digital crosstalk is a glitch pulse transmitted by the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s, and vice versa) in the input register of another DAC digital-to-analog converter. It is measured in standalone mode and expressed in nV-s.

Analog crosstalk

Analog crosstalk is a glitch pulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading an input register and making a full-scale code change (from 0 to 1 and vice versa), then executing a software LDAC and monitoring the output of the DAC whose digital code has not changed. The fault area is denoted by nV-s.

DAC-to-DAC crosstalk

DAC-to-DAC crosstalk is a glitch pulse transferred to the output of one DAC due to another DAC's digital code change and subsequent analog output change. It is measured by loading the attack channel with LDAC low and making a full range of code changes (from 0 to 1 and vice versa), while monitoring the output of the attack channel at mesoscale. The fault energy is expressed in nV-s.

Double the bandwidth

The multiplying bandwidth is a measure of the limited bandwidth of the amplifier within the DAC. A sine wave on the reference appears in the output (loading the full-scale code to the DAC). The octave bandwidth is the frequency at which the output amplitude drops 3db below the input.

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and a decaying sine wave using a DAC. The sine wave is used as a reference for the DAC, and THD is a measure of the harmonics of the DAC's output. The unit is decibel.

theory of operation

Section D/A

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 DACs are fabricated using a CMOS process. The structure consists of a string DAC and an output buffer amplifier. Figure 52 shows a block diagram of the DAC architecture.

Because the input encoding of the DAC is straight binary, the ideal output voltage when using an external reference is given by:

The ideal output voltage when using the internal reference is given by:

where: D is 0 to 4095 (12 bits) loaded into the DAC register: AD5627R/AD5627. AD5647R is 0 to 16383 (14 bits). 0 to 65535 (16 bits) for AD5667R/AD5667. N is the DAC resolution.

resistor string

The resistor string is shown in Figure 53. It's just a string of resistors, each with a value of R. The code loaded into the DAC register determines at which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

output amplifier

The output buffer amplifier can generate rail-to-rail voltages at the output, allowing the output to range from 0v to VDD. It can drive a 2 kΩ load in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier are shown in Figure 33 and Figure 34. The slew rate was 1.8 V/µs and the full settling time was 7 µs.

internal reference

The AD5627R/AD5647R/AD5667R have an on-chip reference. Versions without the R suffix require external references. The on-chip reference is turned off at power-up and enabled by writing to the control register. See the Internal Reference Settings section for details. The version packaged in the 10-lead LFCSP package has a 1.25 V reference and provides a full-scale output of 2.5 V. These devices can operate from a V supply ranging from 2.7 V to 5.5 V. The version packaged in the 10-lead MSOP package has a 2.5 V reference and provides a full-scale output of 5 V. These devices can operate from a VDD supply of 4.5 V to 5.5 V, but with a VDD supply voltage less than 5V, the output is fixed at VDD. See the ordering guide for a complete list of models. The internal reference associated with each device is available on the VREFOUT pin.

A buffer is required if the reference output drives an external load. When using the internal reference, it is recommended to place a 100 nF capacitor between the reference output and GND to maintain reference stability.

xref

The AD5627/AD5667 require an external reference, which is applied to the VREFIN pin. The VREFIN pin on the AD5627R/AD5647R/AD5667R allows an external reference to be used if required by the application. The default condition for the on-chip reference is to turn off at power-up. All devices can be operated from a 2.7V to 5.5V power supply.

serial interface

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 feature a 2-wire IC-compatible serial interface (see 22C-Bus Specification, Rev. 2.1, January 2000, Philips Semiconductors). Under the control of the master device, the AD5627R/AD5647R/AD5667R, AD5627/AD5667 can be connected to the IC bus as a slave device. A timing diagram for a typical write sequence is shown in Figure 3.

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 support standard (100 kHz), fast (400 kHz), and high-speed (3.4 MHz) data transfer modes. High-speed operation is only available on select models. See the ordering guide for a complete list of models. 10-bit addressing and general call addressing are not supported.

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 each have a 7-bit slave address. The five msbs are 00011, and the two lsbs (A1, A0) are set by the state of the ADDR address pins. As shown in Table 7, the ability to hardwire changes to ADDR allows users to combine up to three such devices on a single bus.

The 2-wire serial bus protocol operates as follows:

1. When a high-to-low transition occurs on the SDA line when SCL is high, the host initiates data transfer by establishing a start condition. The following bytes are the address bytes, consisting of a 7-bit slave address. The slave address corresponding to the transmit address responds by pulling SDA low during 9 clock pulses (this is called the acknowledge bit). During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from the shift register. the first

2. Data is transferred over the serial bus in a sequence of 9 clock pulses (8 data bits followed by an acknowledgment bit). The transition of the SDA line must occur during the low period of SCL and remain stable during the high period of SCL.

3. A stop condition is established when all data bits have been read or written. In write mode, the master pulls the SDA line high during 10 clock pulses to establish a stop condition. In read mode, the master issues no acknowledgement for 9 clock pulses (ie, the SDA line is held high). The master then pulls the SDA line low before the 10 clock pulses and then high during the 10 clock pulses to establish a stop condition. the first

write operation

When writing to the AD5627R/AD5647R/AD5667R, AD5627/AD5667, the user must begin the start command followed by an address byte (R/W=0), after which the DAC confirms that it is ready to receive data by pulling SDA low. The AD5627R/AD5647R/AD5667R, AD5627/AD5667 require two bytes of data from the DAC and command bytes to control various DAC functions. Therefore, three bytes of data must be written to the DAC, with the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 54. All of these data bytes are acknowledged by the AD5627R/AD5647R/AD5667R, AD5627/AD5667. A stop condition then occurs.

read operation

When reading data from the AD5627R/AD5647R/AD5667R, AD5627/AD5667, the user begins with a start command followed by an address byte (R/W = 1), after which the DAC confirms that it is ready to transmit data by pulling SDA low. Three bytes of data are then read from the DAC, acknowledged by the master, as shown in Figure 55. A stop condition then occurs.

high speed mode

The AD5627RBRMZ and AD5667RBRMZ provide high-speed serial communication with a 3.4MHz clock frequency. See the ordering guide for details.

Overdrive communication begins after the master addresses all devices connected to the bus with master code 00001XXX to indicate that overdrive transfers are about to begin (see Figure 56). Devices connected to the bus are not allowed to acknowledge the high-speed master code. Therefore, the code behind is a non-recognition. The host must then issue a repeated start followed by the device address. Then, the selected device confirms the address.

All devices continue to operate in high-speed mode until a stop condition is issued by the host. When a stop condition is issued, the device returns to standard/fast mode. When the device is in high-speed mode, the device also returns to standard/fast mode when the CLR is activated.

input shift register

The input shift register is 24 bits wide. Data is loaded into the device as a 24-bit word under the control of the serial clock input SCL. The timing diagram for this operation is shown in Figure 3. 8 msb make up the command byte. DB23 is reserved and should always be set to 0 when writing to the device. DB22(S) Select Multibyte Operation The next three bits are command bits (C2, C1, C0) that control the mode of operation of the device. See Table 8 for details. The last 3 bits of the first byte are the address bits (A2, A1, A0). See Table 9 for details. The remaining bits are 16, 14, 12 bit data words. The data word consists of a 16-bit, 14-bit, and 12-bit input code followed by 2 or 4 bits, respectively, of the don't care AD5647R and AD5627R/AD5627 (see Figure 59 to Figure 61).

multibyte operations

AD5627R/AD5647R/AD5667R, AD5627/AD5667 support multi-byte operation. 2-byte operation is useful for applications that require fast DAC updates and do not require changing command bytes. For 2-byte operation mode, the S bit (DB22) in the command register can be set to 1 (see Figure 57). For standard 3-byte and 4-byte operations, the S bit (DB22) in the command byte should be set to 0 (see Figure 58).

broadcast mode

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 support broadcast addressing. Broadcast addressing enables simultaneous update or shutdown of multiple AD5627R/AD5647R/AD5667R, AD5627/AD5667 devices. With a broadcast address, the AD5627R/AD5647R/AD5667R, AD5627/AD5667 respond regardless of the state of the address pins. Broadcasting is only supported in write mode. AD5627R/AD5647R/AD5667R, AD5627/AD5667 broadcast address is 00010000.

LDAC function

The DACs of the AD5627R/AD5647R/AD5667R, AD5627/AD5667 have a double-buffered interface consisting of two sets of registers, an input register, and a DAC register. The input registers are connected directly to the input shift registers, and the digital code is transferred to the associated input register upon completion of a valid write sequence. The DAC register contains the digital code used by the resistor string.

Access to the DAC registers is controlled by the LDAC pin.

When the LDAC pin is high, the DAC registers are locked and the input registers can change state without affecting the contents of the DAC register. However, when LDAC is lowered, the DAC registers become transparent and the contents of the input registers are transferred to them. The double-buffered interface is useful if the user needs to update all DAC outputs simultaneously. The user can individually write to one of the input registers, then, when writing to the other DAC input register, by lowering LDAC, all outputs are updated simultaneously. These devices all contain an additional feature that the DAC registers are not updated unless the input registers have been updated since the last time LDAC was low. Normally, when LDAC is low, the DAC register is filled with the contents of the input register. In the case of the AD5627R/AD5647R/AD5667R, AD5627/AD5667, the DAC register is updated only if the input register has changed since the last time the DAC register was updated, thereby eliminating unwanted digital crosstalk.

The outputs of all DACs can be updated simultaneously, using the hardware LDAC pins.

Synchronous LDAC

The DAC registers are updated after new data is read in. LDAC can be permanently low or pulsed.

Asynchronous LDAC

The output does not update the register at the same time as the input is written. When LDAC goes low, the DAC register is updated with the contents of the input register.

The LDAC register provides the user with complete flexibility and control over the hardware LDAC pins. This register allows the user to select the LDAC pins in hardware implementation. Setting the LDAC bit register for a DAC channel to 0 means that the channel is controlled by the LDAC pin. If this bit is set to 1, the channel will be updated synchronously, that is, regardless of the LDAC pin. It effectively pulls the LDAC pin low. The LDAC register operating modes are shown in Table 10. This flexibility is useful in applications where the user wants to update selected channels at the same time while the other channels are updated synchronously.

Write to the DAC using Command 110 to load the 2-bit LDAC registers[DB1:DB0]. The default value for each channel is 0, i.e., the LDAC pin is functioning properly. Setting the bit to 1 means that the DAC register is updated regardless of the state of the LDAC pin. See Figure 63 for the contents of the input shift register during the LDAC register set command.

Power down mode

Command 100 is reserved for power up/down functions. Power up/down modes are programmed by setting Bit DB5 and Bit DB4. This defines the output state of the DAC amplifier, as shown in Table 11. Bits db1 and DB0 determine which DAC or DAC the power-up/power-down command is applied to. Setting one of these bits to 1 applies the power-up/power-down state defined by DB5 and DB4 to the corresponding DAC. If the bit is 0, the state of the DAC is unchanged. Figure 65 shows the contents of the input shift register for power up/down commands.

When Bit DB5 and Bit DB4 are set to 0, the device operates normally at 5V and the normal power consumption is 400µA. However, for the three power-down modes, the supply current drops to 480Na at 5V. Not only does the supply current drop, but the output stage is also internally switched from the amplifier's output to a resistor network of known value. This allows the output impedance of the device to be known when the device is in power down mode. The output can be internally connected to GND through a 1kΩ or 100kΩ resistor, or left open (tri-stated) as shown in Figure 62.

When the power-down mode is activated, the bias generator, output amplifier, resistor string and other associated linear circuits are turned off. However, when powered down, the contents of the DAC registers are not affected. The outlet power drop time is usually 4μs, V=5V.

Power-on reset and software reset

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 contain a power-on reset circuit that controls the output voltage during power-up. The device is powered up to 0 V and the output remains powered up at this level until a valid write sequence to the DAC. This is useful in applications where it is important to know the state of the DAC's output during power-up. During power-on reset, any events on the LDAC or CLR are ignored.

There is also a software reset function. Command 101 is a software reset command. The software reset command contains two reset modes, which are software programmable by setting bit DB0 in the input shift register.

Table 12 shows how the state of the bits corresponds to the software reset mode of operation of the device. Figure 64 shows the contents of the input shift register during the software reset mode of operation.

After a full software reset (Db0=1), there must be a short delay, about 5 seconds, to complete the reset. During reset, a low pulse can be observed on the CLR line. If the next IC transaction begins before the CLR line returns high, the IC transaction is ignored.

Clear pin (CLR)

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 have asynchronous clear inputs. The CLR input is falling edge sensitive.

When CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded into all input and DAC registers. This clears the output to 0 V. The device exits clear code mode on the falling edge of the ninth clock pulse of the last byte validly written. If the CLR is activated during the write sequence, the write is aborted. If the CLR is activated in overdrive mode, the device exits overdrive mode to standard/express mode.

Internal reference setup (R version)

By default, the on-chip reference is turned off at power-up. It can be turned on by sending a reference set command (111) and setting DB0 in the input shift register. Table 13 shows how the state of the bits corresponds to the operating mode. During an internal reference set command, the contents of the input shift register are shown in Figure 66.

application information

Using the reference as AD5627R/AD5647R/AD5667R, AD5627/AD5667 Since the supply current required by the AD5627R/AD5647R/AD5667R, AD5627/AD5667 is extremely low, another option is to use a voltage reference to supply the required voltage to the device (see Figure 67) . This is especially useful if the power supply is noisy, or if the system supply voltage is not 5V or 3V, such as 15V. The voltage reference outputs the regulated supply voltage for the AD5627R/AD5647R/AD5667R, AD5627/AD5667. If a low dropout REF195 is used, it must supply 450 µA to the AD5627R/AD5647R/AD5667R, AD5627/AD5667 with no load on the output of the DAC. When the DAC output is loaded, the REF195 must also supply current to the load. The total current required (with a 5 kΩ load on the DAC output) is: 450 μA + (5 V/5 kΩ) = 1.45 mA; the load regulation of the REF195 is typically 2ppm/mA, resulting in 2.9ppm of the 1.45ma current ( 14.5µV) error. This corresponds to a 0.191 LSB error.

Bipolar Operation Using AD5627R/AD5647R/AD5667R, AD5627/AD5667

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 have been designed for single-supply operation, but a bipolar output range can also be achieved using the circuit in Figure 68. The output voltage range of this circuit is ±5v. At the amplifier output, an AD820 or OP295 is used as the output amplifier for rail-to-rail operation.

The output voltage of any input code can be calculated as follows:

where D represents the input code in decimal (0 to 65535). VDD=5V, R1=R2=10kΩ,

This is an output voltage range of ±5 V, 0x0000 corresponds to -5 V output and 0xFFFF corresponds to +5 V output.

Power Bypass and Ground

When accuracy is important in a circuit, it is helpful to carefully consider the power and ground return layout on the board. A printed circuit board containing the AD5627R/AD5647R/AD5667R, AD5627/AD5667 should have separate analog and digital sections, each with its own board area. If the AD5627R/AD5647R/AD5667R, AD5627/AD5667 are in a system where other devices require an AGND to DGND connection, the connection should only be made at one point. This ground point should be as close as possible to the AD5627R/AD5647R/AD5667R, AD5627/AD5667.

The power supplies to the AD5627R/AD5647R/AD5667R, AD5627/AD5667 should be bypassed with 10µF and 0.1µF capacitors. Capacitors should be placed as close to the device as possible, ideally a 0.1µF capacitor should be placed close to the device. The 10µF capacitor should be of the tantalum bead type. It is important that the 0.1µF capacitors have low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic type capacitors. This 0.1µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents generated by internal logic switches. The power cord itself should have as large a trace as possible to provide a low impedance path and reduce the impact of faults on the power cord. Clocks and other fast switching digital signals should be shielded from other devices on the board through digital ground. Avoid crossover of digital and analog signals as much as possible. When the traces cross on opposite sides of the board, make sure they run at right angles to each other to reduce the effect of feedthrough through the board. The best board layout technique is microstrip, where the component side of the board is used only for the ground plane, and the signal traces are placed on the solder side. However, this is not always possible with two-layer boards.

Dimensions