Features and Benefits

Powered by 1 Li+ or 2 alkaline/NiMH/NiCAD batteries; adjustable output voltage; >75% efficiency; three-level switch current limit: 1.0, 1.2, 1.4A; fast charge time; charge completion indicator; with trigger Integrated IGBT driver; no primary-side Schottky diodes ▪Low profile package.

illustrate

The A8436 is a highly integrated integrated circuit that charges the flash capacitors of digital and film cameras. It also features an integrated IGBT driver that facilitates flash discharge functionality and saves board space.

To charge the flash capacitor, the A8436 integrates a 40V DMOS switch that drives the transformer in a flyback topology, allowing an optimized design for tight coupling and high efficiency. A proprietary control scheme optimizes capacitor charging time. Low quiescent current and low shutdown current further improve system efficiency and extend battery life.

Three levels of switch current limit are available: 1.0, 1.2, and 1.4 A. This level is determined by configuring the ILIM pin to be grounded, floating, or pulled high to the IC supply voltage, respectively.

The charge pin activates the A8436 and begins charging the output capacitor. When the specified output voltage is reached, the A8436 stops charging until the charging pin is toggled again. Pull the charging pin low to stop charging. The D''O''N''E'' pin is an open-drain indicator when the specified output voltage is reached.

The A8436 can be used with two Alkaline/NiMH/NiCAD or a single-cell Li-Ion battery connected to the primary side of the transformer. Connect the VIN pin to a 3.0 to 5.5 volt power source, which can be the system rail or battery positive if used.

The A8436 is available in a very low profile (0.75mm) 10-terminal 3mm x 3mm MLP/TDFN package, making it ideal for space-constrained applications, as well as MSOPs. They are lead free, 100 % matte tin leadframe.

typical application

Applications include: digital camera flash; film camera flash; mobile phone flash; emergency flash.

Running Timing Diagram

Event description:

A. In the case that the vehicle identification number is higher than the VUVLO level, start charging by pulling the charging to high.

B. When the voltage reaches the target voltage, charging stops. "D" "O" "N" "E" goes low, indicating that the charging process is complete.

C. Start a new charging process with a low-to-high transition at the charge pin.

D. Pull charge low to put the controller in low power standby mode.

E. The charging does not start because the VIN is below the VUVLO level when the charging is too high.

F. After the VIN is above VUVLO, another low-to-high transition at the charge pin is required to start charging.

Performance characteristics

Tests using the application circuit shown in Figure 6 (unless otherwise stated)

Function description

Overview

The A8436 is a flash capacitor charger control IC with adjustable input current limit. It also integrates an IGBT driver for flash tube flash operation, saving significant board space compared to discrete flash operation solutions. The control logic is shown in the functional block diagram.

The charging operation of the A8436 is initiated by a low-to-high signal on the charge pin, provided that the VIN is above the VUVLO level. If the charge is already high before the VIN reaches VUVLO, another low-to-high transition on the charge pin is required to start charging. When the charge cycle begins, the transformer primary current I rises substantially linearly at a rate determined by the combined effects of the battery voltage,

Primary side inductance. When the IPrimary reaches the current limit ISWLIM, by configuring the ILIM pin setting, the internal MOSFET turns off immediately, allowing energy from the secondary winding to be pushed into the flash capacitor COUT. The secondary side current decreases linearly with the increase of charge.

When the internal MOSFET switch is turned off, the output voltage VOUT is sensed by the resistor string R1 to R3 connected between the anode D1 of the output diode and ground. This resistor string forms a voltage divider that is fed back to the FB pin. The resistors must be sized to achieve the desired output voltage level based on a typical value of 1.205 V at the FB pin. Once VOUT reaches the desired value, the charging process is terminated. The user can toggle the charge pin to refresh the flash capacitor.

Switching time control

The A8436 implements adaptive on/off time control. (See the control logic block in the simplified functional block diagram on page 2 for circuit details.) The duration, tON, is determined by the input voltage, VIN, transformer primary inductance, LPrimary, and the set current limit ISWLIM. The off-time duration tOFF depends on the operating conditions during the off-time. The A8436 applies its two charging modes according to these conditions: fast charging mode and timer mode.

Quick Charge and Timer Mode

When the flash capacitor COUT is only partially discharged, the IC operates in fast charge mode. In fast charge mode, the converter operates near the discontinuity boundary and the sensing circuit tracks the flyback voltage at the SW node. Once the voltage drops below 1.2v, the internal MOSFET switch is turned on again to start the next charge cycle.

When starting to output a fully discharged flash capacitor, the IC operates in timer mode, which is a fixed 18µs off-time control typically when the output voltage VUT is less than about 10 to 20 V. An advantage of the A8436 watchdog timer control scheme is that it limits the initial current surge, which acts as a "soft start". As shown in Figure 3, the timer mode lasts only a fraction of the time (usually <100ms). It has a lower initial input charge current due to its low duty cycle. When the output voltage rises above 10 to 20 volts, the adaptive fast charge mode takes over control, increasing the average input current level.

Charge cycle for fully discharged flash capacitor

Figure 4A. Initial two cycles of charging a fully discharged flash capacitor. During these two cycles, the rest time (VSW low) is controlled by an internal 18µs timer (timer mode). Note that in the first cycle, the i main cycle starts around 0a, but in the second cycle, it starts from a higher level. This indicates that the transformer core did not reset during the first cycle.

Figure 4B. During the intermediate cycle, the output voltage VOUT increases. The second is discontinuous, causing ringing of the VSW. However, the ringing is not large enough to pull VSW below 1.2V, so the A8436 is still in timer mode.

Figure 4C shows the last cycle in timer mode, followed by a series of cycles in fast charge mode. Due to the increase in VOUT, VSW is able to drop below 1.2V each cycle, triggering the turn-on of the main MOSFET switch.

To understand the timer mode, it is important to note that secondary currents such as secondary winding charging current decrease linearly at the following rate:

where: secondary current is the secondary side current, primary side inductance, and N is the transformer turns ratio (N times/N times).

As the three panels in Figure 4 show, when the A8436 charges a fully discharged flash capacitor, ISecondary decreases very slowly due to the low initial VOUT. When the SW node voltage is greater than 1.2 V, the A8436 internal timer (timer mode) sets a maximum time frame of 18 μs. When the off-time exceeds 18µs, the internal MOSFET switch turns on, initiating the next charge cycle.

input current limit

By configuring the ILIM pin, the peak input current ISWLIM can be set to three levels:

The lower input current offers the advantage of extending battery life. However, for faster charging times, use the highest current limit.

ISWLIM can be adjusted during charging. Figure 5 shows the ISWLIM waveform being adjusted during charging. The ISWLIM is reduced from 1.4 A to 1.2 A, and the charging speed is slightly slower at lower current levels.

application information

Transformer Design

turns ratio. The minimum transformer turns ratio N (secondary:primary) should be chosen according to the following formula:

where: VOUT(V) is the desired output voltage level, VD_Drop(V) is the forward voltage drop of the output diode, VBATT(V) is the transformer battery supply, and 40(V) is the rated voltage of the internal MOSFET switch, Indicates the maximum allowable reflected voltage output to the switch pin.

For example, if VBATT is 3.5 V, the VD_ drop is 1.7 V (which may be the case when two high voltage diodes are in series), and the desired VOUT is 320 V, the turns ratio should be at least 8.9.

In the worst case, N will be higher when VBATT is at its highest and VDYLUP and VOUT are at their maximum tolerance limits. Taking VBATT=5.5v, VD_Drop=2v, VOUT=320v×102%=326.4v is the worst case, and N is 9.5.

In practice, be sure to choose a turns ratio higher than the calculated value to give some safety margin. In the worst case, a minimum turns ratio of N=10 is recommended.

Primary Inductance. The A8436 has a minimum off-time tOFF(min) of 300 ns to ensure proper SW node voltage sensing. When choosing the primary inductance LPrimary (μH), use the following formula as a loose guide:

Ideally, the charging time is not affected by the primary inductance of the transformer. However, in practical applications, it is recommended that the primary inductance be selected between 10μH and 20μH. When the primary inductance is much less than 10μH, the operating frequency of the converter is high, and the switching loss increases proportionally. This results in lower efficiency and longer charging times. When LPrimary is greater than 20μH, the power rating of the transformer must be increased substantially to handle the required power density, and the series resistance is usually higher. An optimized design to achieve a small scale solution would have a 12 to 14µH primary, minimal leakage inductance and secondary capacitance, and minimize primary and secondary series resistance. See the table "Recommended Components" for details.

leakage inductance and secondary capacitance. The transformer should be designed to minimize leakage inductance to ensure that the peak turn-off voltage at the switch node does not exceed the 40V limit. However, for this application, the minimum achievable leakage inductance is often affected by the increase in parasitic capacitance. In addition, the transformer secondary capacitance should be minimized. Any secondary capacitance will be multiplied by N2 when reflected to the primary capacitance, resulting in a high initial current swing when the switch is turned on, and reducing efficiency.

Adjust the output voltage

The A8436 senses the output voltage during shutdown. This allows the voltage divider network R1 to R3 (see Figure 6) to be connected to the anode of the high voltage output diode D1, thereby eliminating the power loss due to the feedback network when charging is complete. The output voltage can be adjusted by choosing an appropriate voltage divider resistor value. Calculate the value of Rx(Ω) using the following formula:

R1 and R2 together need to have a breakdown voltage of at least 300 V. A typical 1206 surface mount resistor has a breakdown voltage rating of 150 V. It is recommended that R1 and R2 have similar values to ensure uniform voltage stress between them. The recommended values are: R1=R2=150kΩ (1206); R3=1.2kΩ (0603), both of which together generate a stop voltage of 303v.

Using higher resistor values for R1, R2, and R3 does not significantly improve efficiency because power loss in the feedback network occurs primarily during shutdown time, which is only a small fraction of each charge cycle.

Output diode selection

Select the rectifier diode D1, with small parasitic capacitance (short reverse recovery time), and meet the requirements of reverse voltage and forward current at the same time.

The peak reverse voltage VD_peak of the diode occurs when the internal MOSFET switch is closed and the primary side current starts to rise. can be calculated as:

The peak current ID_peak of the rectifier diode is calculated as:

Input Capacitor Selection

It is recommended to use a ceramic capacitor with X5R or X7R dielectric for the input capacitor C2. It should be rated at least 4.7µF/6.3v to disconnect the battery input VBATT on the primary side of the transformer. When using a separate bias, connect at least a 0.1µF/6.3 V bypass capacitor to the VIN pin for the A8436 VIN supply.

Layout Guidelines

The key to a good flash capacitor charger circuit layout is to minimize parasitics on the power switch loop (transformer primary side) and the rectifier loop (secondary side). Use short, thick lines to connect to the transformer primary and switch pins.

Output voltage sensing circuit components must be kept away from switching nodes, such as the SW pin. Make sure there are no ground planes under R1 and R2, as parasitic capacitance to ground can affect sensing accuracy. It is important that the "D" "O" "N" "E" signal traces should be kept away from transformers and other switch traces to minimize noise pickup. In addition, high-voltage isolation rules must be strictly followed to avoid board breakdown failures.