feature

Excellent clamping characteristics; 3 mV clamping error; 1.5 ns overspeed recovery; minimal nonlinear clamping region; 240 MHz clamp input bandwidth; 63.9 V clamp input range; wideband AD8036 AD8037; small signal 240 MHz 270 MHz; large Signal (4v pp) 195mhz 190mhz; good DC characteristics; 2 mV offset; 10 mV/8C drift; ultra-low distortion, low noise; –72 dBc typical @20 MHz; 4.5nv/Hz input voltage noise; high speed; Conversion rate 1500 V/MS; sedimentation 10ns to 0.1%, 16ns to 0.01%; 63 V to 65 V power supply operation.

application

ADC buffers; IF/RF signal processing; high-quality imaging; broadcast video systems; video amplifiers; full-wave rectifiers.

Product Description

The AD8036 and AD8037 are wideband, low distortion clamping amplifiers. The AD8036 is unity gain stable. The AD8037 is stable at gains of two or more. These devices allow designers to specify high (VCH) and low (VCL) output clamp voltages. The output signal will be clamped at these specified levels. The AD8036 and AD8037 utilize a unique patent-pending CLAMPIN 8482 ; input clamp structure that improves clamping performance by a factor of 10 compared to conventional output clamp arrangements. In particular, the clamp error is typically less than or equal to 3mv, and the distortion in the clamp region is minimized. This product can be used as a classic op amp or clamp amplifier where high and low output voltages are specified.

The AD8036 and AD8037 employ a voltage feedback structure that meets the requirements of many applications that previously relied on current feedback amplifiers. The AD8036 and AD8037 exhibit an exceptionally fast and accurate impulse response (16 ns to 0.01%), and the extremely wide small signal clamp is a trademark of Analog Devices.

As well as large signal bandwidth and ultra-low distortion. The AD8036 achieves -66 dBc at 20 MHz, 240 MHz small signal and 195 MHz large signal bandwidth. The AD8036 and AD8037 recover from 2× clamp overdrive in 1.5ns. These features make the AD8036/AD8037 ideal for driving, buffered flash, and high-resolution ADCs.

In addition to traditional output clamp amplifier applications, the input clamp structure also supports clamp levels as additional inputs to the amplifier. Therefore, signals with speeds up to 240MHz can be applied to the clamp pins in addition to the static dc clamp levels. The clamp value can also be set to any value within the output voltage range if VH is greater than VL. Because of these clamping properties, the AD8036 and AD8037 can be used in non-traditional applications such as full-wave rectifiers, pulse generators, or amplitude modulators. These new applications are just a few examples of different applications that can be designed with input clamps.

The AD8036 is available in chip, industrial (–40°C to +85°C) and military (–55°C to +125°C) package temperature ranges, as well as the industrial AD8037. Industrial versions are available in plastic dipping and SOIC; MIL versions are available in cerdip packages.

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage swing × bandwidth product . . . . . . . . . 350 V-MHz;

|VH – Vehicle Identification Number|. . .. . . . . . . . . . . ≤ 6.3 V;

|VL – Vehicle Identification Number|. . . . . . . . . . . . . . . . . . ≤ 6.3 V;

Internal power consumption

Plastic dipping package (N) . . . . . . . . . . . . . . . . . . .3 watts;

Small Outline Package (SO) . . . . . . . . . . . . . . 0.9 watts;

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . ±VS;

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . ±1.2 V;

Output short circuit duration. . . . . . . . . . . . . . . . . . . . . . . Observe the power derating curve;

Storage temperature range N, R. . . . . . . –65°C to +125°C;

Operating Temperature Range (Class A) . . . . . .. –40°C to +85°C;

Lead temperature range (soldering for 10 seconds) . . . . . . .+300 degrees Celsius.

notes

1. Stresses listed above absolute maximum ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the above conditions or any other section of this specification is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

2. The specification applies to devices in free air: 8-lead plastic impregnation: θJA=90°C/W; 8-lead SOIC: θJA=155°C/W; 8-lead Cerdip: θJA=110°C/W .

Maximum power consumption

The maximum power that these devices can safely dissipate is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic packaged devices is determined by the glass transition temperature. In plastics around 150°C, temporarily exceeding this limit may result in a shift in parametric performance. Variation in the stress applied to the mold by the package. Junction temperatures exceeding +175°C for extended periods of time can cause device failure. Although the AD8036 and AD8037 are internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (±150°C) will not be exceeded under all conditions. condition. To ensure correct operation, it is necessary to observe the maximum power derating curve.

general theory of operation

The AD8036 and AD8037 are wideband voltage feedback clamp amplifiers. Since their open-loop frequency response follows the traditional 6db/octave attenuation, their gain-bandwidth product is essentially unchanged. Increasing their closed-loop gain results in a corresponding reduction in small-signal bandwidth. This can be observed by noting the bandwidth specification between the AD8036 (gain 1) and the AD8037 (gain 2). The AD8036/AD8037 typically maintain a phase margin of 65 degrees. This high margin minimizes the effects of signal and noise peaks.

While the AD8036 and AD8037 can be used in inverting or non-inverting configurations, the clamp function will only work in non-inverting mode. Therefore, this section only shows connections in non-transformed configurations. Applications that require a reversed configuration are discussed in the Applications section. In applications that do not require clamping, pins 5 and 8 (VL and VH, respectively) can be left floating. See also the Input Clamp Amplifier Operation and Applications chapter.

Feedback Resistor Selection

The value of the feedback resistor is critical for optimal performance of the AD8036 (gain +1), while the value of the feedback resistor is less critical as the gain increases. Therefore, this section is dedicated to the year 8036 AD.

At the minimum stable gain (+1), the AD8036 provides the best dynamic performance, RF=140Ω. This resistor acts only as a parasitic suppressor, preventing decaying RF oscillations due to lead (input, feedback) inductance and parasitic capacitance. This RF value provides the best combination of wideband, low parasitic peaking, and fast settling time.

In fact, 100–130Ω resistors should be placed in series with the positive input of other AD8036 non-vertical configurations for the same reason. The correct connections are shown in Figure 69.

For general voltage gain applications, the amplifier bandwidth can be approximately estimated as:

This estimate loses accuracy at gains of +2/-1 or lower due to the damping factor of the amplifier. For these "low gain" cases, the bandwidth will actually exceed the calculated value (see closed loop BW plots, Figures 15 and 27).

impulse response

Unlike traditional voltage feedback amplifiers, the AD8036 and AD8037 provide “on-demand” current that increases proportionally to the input “step” signal amplitude, while the conversion speed of traditional voltage feedback amplifiers is determined by their front-end DC quiescent current and gain bandwidth. Cumulative decision. This results in a slew rate (1200 V/μs) comparable to a wideband current feedback design. This, combined with the relatively low input noise current (2.1pa/√), gives the AD8036 and AD8037 the best characteristics of voltage and current feedback amplifiers.

Large signal performance

The outstanding large-signal operation of the AD8036 and AD8037 is due to a unique proprietary design architecture.

To maintain this level of performance, a maximum 350 MHz product must be observed (eg, @100 MHz, VO less than 3.5 VPP).

Supply and Input Clamp Bypass

Proper power supply bypassing is critical when optimizing the performance of high frequency circuits. The inductance in the power line can form a resonant circuit, which can create peaks in the amplifier's response. Additionally, if large current transients must be supplied to the load, bypass capacitors (typically greater than 1µF) are required to provide the best settling time and lowest distortion. A parallel combination of at least 4.7µF and between 0.1µF and 0.01µF is recommended. Some brands of electrolytic capacitors require a small series damping resistor ≈ 4.7Ω for best results.

When the AD8036 and AD8037 are used in clamp mode and a dc voltage is connected to the clamp inputs VH and VL, 0.1µF bypass capacitors are required between each input pin and ground for stability.

Driving capacitive loads

The AD8036 and AD8037 are primarily used to drive inactive loads. If a drive load with capacitive elements is required, the best frequency response is obtained by adding a small series resistor, as shown in Figure 70. The accompanying chart shows the optimum value of RSERIES for capacitive loads. It is worth noting that when driving bulk capacitive loads, the frequency response of the circuit will be controlled by the passive roll-off of RSERIES and CL. RSERIES is not required for capacitive loads of 6pf or less.

Input Clamp Amplifier Operation

The key to the fast, accurate clamping and amplifier performance of the AD8036 and AD8037 is their unique patent-pending clamp-input clamp structure. This new design reduces clamping error by more than 10 times over previous output-clamp-based circuits, while greatly increasing the bandwidth, accuracy, and versatility of the clamped input.

Figure 72 is an ideal block diagram of the AD8036 connected as a unity gain voltage follower. The main signal path consists of A1 (1200 V/µs, 240 MHz high voltage gain, differential to single-ended amplifier) and A2 (G=+1 high current gain output buffer). The only difference between the AD8037 and the AD8036 is that A1 is optimized for two or more closed-loop gains.

The clamping part consists of comparators CH and CL, which drive switch S1 through the decoder. A unity-gain buffer in series with the +VIN, VH, and VL inputs isolates the input pins from the comparator and S1 without compromising bandwidth or accuracy.

These two comparators have about the same bandwidth as A1 (240mhz), so they can keep up with the signal within the effective bandwidth of the AD8036. To illustrate the operation of the clamp circuit, consider the case where VH is referenced to +1v, VL is open, and the AD8036 is set to gain +1 by connecting its output back to its inverting input through the recommended 140Ω feedback resistor. Note that the main signal path always runs closed loop because the clamp circuit only affects the non-rotating input of A1.

If a voltage ramp of 0 V to +2 V is applied to +VIN of the AD8036 for the connection just described, VOUT should fully track +VIN to +1 V and then should be limited to +1 V exactly as +VIN continues to +2 V.

In fact, the AD8036 is close to this ideal performance. When the +VIN input voltage changes from zero to 1V, the output of the high limit comparator CH starts in the off state, and the output of CL also starts in the off state. When +VIN just exceeds VIN (ideally, by say 1µV, actually about 18mV), CH changes state, switching S1 from "A" to "B" reference level. Since the + input of A1 is now connected to VH, further increases in +VIN have no effect on the output voltage of the AD8036. In short, the AD8036 now operates as a unity gain buffer at the VH input, since any change in VH, for VH > 1v, will be faithfully reproduced at VOUT.

The AD8036 operates similarly to the negative input voltage on VL and the negative clamp level, with S1 controlled by the comparator CL. Since the comparators see the voltage on the +VIN pin as their common reference level, the voltages VH and VL are defined as "high" or "low" relative to +VIN. For example, if VIN is set to zero volts, VH is on, and VL is +1v, the comparator CL will switch S1 to "C", so the AD8036 will buffer the voltage on VL and ignore +VIN.

The performance of the AD8036 and AD8037 is very close to the ideal just described. The threshold of the comparator extends from 60 mV within the clamping window defined by the voltages on VL and VH to 60 mV beyond the edge of the window. Switch S1 is implemented by current control, and the A1+ input transitions continuously from eg VIN to VH when the input voltage crosses the input threshold of the comparator from 0.9v to VH=1.0v.

The net effect of these non-idealities is to soften the transition from amplification mode to clamp mode without affecting the absolute clamp limit set by the clamp circuit. Figure 73 is a plot of VOUT versus VIN for the AD8036 and a typical output clamp amplifier. Both amplifiers are set to G=+1 and VH=+1 V.

The worst-case error between VOUT (ideal clamped) and VOUT (actual) is typically 18mv times the amplifier's closed loop gain. This happens when VIN equals VH (or VL). When the VIN is above and/or below this limit, the output voltage will settle to within 5 mV of the ideal value.

In contrast, the transfer curve of an output clamp amplifier will typically show some compression at the onset of the 0.8v input, and the output voltage can exceed the clamp limit by as much as 200mv. In addition, since the effective output clamping causes the amplifier to operate open-loop in clamp mode, the output impedance of the amplifier will increase, potentially leading to additional errors.

The clamped input clamp structure of the AD8036 and AD8037 is only suitable for non-converting or follower applications, since it operates on the input, the clamped voltage levels VH and VL and the input error limit will be multiplied by the closed loop gain at the output of the amplifier. For example, to set an output limit of ±1v for the AD8037 operating at a gain of 3.0, VH and VL need to be set to +0.333 V and -0.333 V, respectively.

The only limitation to using the +VIN, VL, VH pins of the AD8036 and AD8037 as inputs is that the maximum voltage difference between +VIN and VH or VL should not exceed 6.3 V, and that all three voltages are within the supply voltage range. For example, if VL is set to –3 V, the VIN should not exceed +3.3 V.

AD8036/AD8037 Applications

The AD8036 and AD8037 use a unique input clamp circuit to perform the clamping function. As a result, they provide better clamping functionality than traditional output clamping devices and provide additional flexibility to perform other unique applications.

However, there are some restrictions on the circuit configuration; since the clamping is performed at the input stage, some calculations are required to determine the clamp level.

A major limitation of the clamping feature of the AD8036/AD8037 is that clamping only occurs when the amplifier is used in non-converting mode. To clamp the inverter circuit, an additional inverter gain stage is required. Another limitation is that VH is greater than VL, and each is within the output voltage range of the amplifier (±3.9v). VH can be below ground and VL can be above ground as long as VH is kept above VL.

unity gain clamp

The simplest circuit to calculate the clamp level is the unity-gain follower shown in Figure 74. In this case, the AD8036 should be used because it is compensated for the irreversible unity gain.

This circuit will clamp at the higher voltage set by VH (the voltage applied to pin 8) and the lower voltage set by VL (the voltage applied to pin 5).

gain clamp

Figure 75 shows the AD8037 configured with two non-vertical gains. The AD8037 is used in this circuit because it compensates for two or more gains and provides greater bandwidth. In this case, the high clamp level at the output will occur at 2×VH and the low clamp level at the output will be 2×VL. In a circuit configured to not change the gain, the equation governing the output clamp level is as follows:

Among them: VCH is the high output clamp level;

VCL is the low output clamp level;

G is the gain of the amplifier configuration;

VH is the high input clamp level (pin 8);

VL is the low input clamping level (pin 5);

*Amplifier offset is assumed to be zero.

Offset clamping

Some op amp circuits need to work at bias voltages. These are usually configured in inverter mode, where the bias voltages can be summed as one input. Since the AD8036/AD8037 clamp does not function in inversion mode, it cannot be clamped with this configuration.

Figure 76 shows the non-rotating configuration of the AD8037, which provides clamping and has an offset. 9251 ; This circuit shows the AD8037 as a driver for the AD9002, 8-bit, 125 Msps a/D converter and illustrates some considerations for using the AD8037 with offset and clamp.

The analog input range of the AD9002 is ground to -2V. The voltage outside the input range should not exceed 0.5V to prevent interruption of the internal operation of the A/D and to avoid excessive current flow These requirements make the AD8037 the first choice for signal conditioning.

When an offset is added to a non-vertical op amp circuit, it is input to the inverting input through a resistor. The result is that the op amp must now operate at greater than unity closed loop gain. For this circuit, two gains were chosen to allow the AD8037 to be used. The feedback resistor, R2, is set to 301Ω for optimal performance of the AD8037 at a gain of 2.

There is an interaction between offset and gain, so some calculations have to be done to get the correct values for R1 and R3. For both gains, the parallel combination of resistors R1 and R3 must equal feedback resistor R2. Therefore R1×R3/R1+R3=R2=301Ω, the reference used to provide the offset is the AD780 whose output is 2.5v. It has to be split down to give the desired 1v offset. So 2.5 V × R1/(R1 + R3) = 1 V, when both equations are solved simultaneously, we get R1 = 499 Ω and R3 = 750 Ω (using the nearest 1% resistor value in all cases). A positive 1V offset at the input translates to a -1V offset at the output.

The usable input signal swing of the AD9002 is 2V pp. This is centered at a -1V offset, allowing usable signals to range from 0V to -2V. It is best to clamp the input signal so that it does not exceed this range by more than 100mV in both directions. Therefore, the high clamp level should be set to +0.1V and the low clamp level should be set to -2.1V as shown at the input of the AD9002 (the output of the AD8037).

Because the clamping is done at the input stage of the AD8037, the clamp level seen at the output is not only affected by the gain of the circuit described earlier, but also by the offset. Therefore, to obtain the desired clamp level, VH must be biased at +0.55v and VL must be biased at -0.55v.

The clamping level at the output can be calculated by:

VCH= VOFF + G × VH

VCL= VOFF + G × VL

where: VOFF is the offset voltage appearing at the output.

The resistors used to generate the VH and VL voltages should be kept to a minimum to reduce errors due to clamp bias currents. This current depends on VH and VL (see Figure 61) and will create a voltage drop across any resistors in series with each clamp input. This additional error voltage, multiplied by the amplifier's closed-loop gain, can be substantial, especially in high closed-loop gain configurations. A 0.1µF bypass capacitor should be placed between the input clips VH and VL and ground to ensure stable operation.

The 1N5712 Schottky diode is used to protect the substrate diode in the AD9002 from forward bias during power-up transients.

Programmable pulse generator

The clamp output of the AD8036/AD8037 is accurately set and level controlled. This, combined with the wide frequency band and high slew rate, makes them ideal for programmable level pulse generators.

Figure 77 is a schematic diagram of a pulse generator that can directly receive a TTL-generated timing signal as its input and generate pulses at outputs up to 24v pp at a slew rate of 2500v/µs. The output level can be programmed anywhere from -12 V to +12 V.

This circuit uses the AD8037 to work with the AD811 at a gain of 2 to boost the output to a range of ±12 V. The AD811 was chosen because of its ability to operate from ±15V supplies and its high slew rate.

R1 and R2 act as level shifters to make the TTL signal levels approximately symmetrical between ground and ground. This ensures that both high and low logic levels will be clamped by the AD8037. For well-controlled signal levels in the output pulse, the high and low outputs should be generated by the clamping action of the AD8037, not by high or low logic through the linear amplifier. To get good rise and fall times at the output pulses, a logic family with high-speed edges should be used.

High logic levels are clamped to twice the VH voltage, while low logic levels are clamped to twice the VL voltage. The output of the AD8037 is amplified by the AD811 operating at a gain of 5 for a total gain of 10 resulting in a high output level that is 10 times the VH voltage and a low output level that is 10 times the VL voltage.

High-speed full-wave rectifier

The clamp input is an additional input to the input stage of the op amp. As such, they have an input bandwidth comparable to the amplifier input, and when they are driven dynamically, they have some unique capabilities.

Figure 78 is a schematic diagram of a full wave rectifier, sometimes referred to as an absolute value generator. It operates up to 20 MHz and can work at higher frequencies, but with a drop in performance. Distortion performance is significantly better than diode-based full-wave rectifiers, especially at high frequencies.

The circuit is configured as an inverting amplifier with a gain of 1. This input drives the inverting amplifier and also directly drives VL, the low-level clamp input. The high-level clamp input VH remains floating and has no effect in this circuit.

When the input is negative, the amplifier acts as a conventional unit inverting amplifier, outputting a positive signal with the same amplitude as the opposite polarity of the input. VL is driven negatively by the input, so it does not perform a clamping action because a positive output signal always drives VL above the negative level.

When the input is positive, the output result is the sum of the two independent effects. First, due to the unity-gain inversion configuration, the inverting amplifier multiplies the input by –1. This effectively produces an offset as described above, but with a dynamic level equal to –1 times the input.

Second, while the positive input is grounded (through 100Ω), the output is clamped at twice the voltage applied to VL (the positive dynamic voltage in this case). The factor of two is because the noise gain of the amplifier is two.

The sum of these two actions produces an output equal to the unit of the input signal of the positive input signal multiplied by the input signal, see Figure 79. A photo of the input/output range with an input signal of 20 MHz and an amplitude of ±1 V is shown in Figure 80.

Therefore, for a positive or negative input signal, the output is the unit multiplied by the absolute value of the input signal. By applying the input to VH instead of VL, the circuit can easily be configured to produce a negative absolute value of the input.

When the input crosses zero, the circuit can be within about 40 mV of ground. This voltage is fixed over a wide frequency range and is the result of switching between the traditional op amp input and the clamp input. But since there is no diode to quickly switch from forward to reverse bias, its performance far exceeds that of a diode-based full-wave rectifier.

The mentioned 40mV offset can be eliminated by adding an offset to the circuit. The gain from the 27.4 kΩ input resistor to the inverting input is 0.01, while the gain of the circuit changes by only 1%. The positive and negative 4V DC levels of this resistor (depending on the polarity of the rectifier) will compensate for the offset.

Full-wave rectifiers are widely used in AM signal detection, high-frequency AC voltmeters and various operations.

AM

In addition to being able to be configured as an amplitude demodulator (AM detector), the AD8037 can also be configured as an amplitude modulator as shown in Figure 81.

The positive input of the AD8037 is driven by a square wave of sufficient amplitude to generate a high and low clamp action. This is a high frequency carrier signal.

The modulated signal is applied to both the input of the unity-gain inverting amplifier and the lower clamped input VL. VH is biased at +0.5v dc.

To understand circuit operation, it is helpful to first consider a simple circuit. If both VL and VH are biased at -0.5v DC, and the carrier and modulation inputs are driven as described above, the output will be a 2v pp square wave at the carrier frequency, on the waveform at the modulation frequency. Inverting the input (modulated signal) produces a different offset at the output than a 2v pp square wave. Because the noise gain of the circuit is 2, both the high and low levels are twice the clamped input level.

A more complicated situation arises when VL is driven by a modulating signal rather than held at a dc level. The resulting waveform consists of an upper envelope and a lower envelope, with the carrier square wave between the upper and lower envelopes. In a typical AM waveform, the upper and lower envelope waveforms are 180° out of phase.

The upper envelope is generated by the upper clamp level, which is offset by the waveform applied to the inverting input. Due to the reverse configuration, this offset is opposite to the polarity of the input waveform.

The lower envelope is created by the sum of the two effects. First, it is offset by the waveform applied to the inverting input, as in the case of the simplified circuit above. The polarity of this offset is the same as the direction of the upper envelope. Second, the output is driven in the opposite direction of the offset at twice the offset voltage by the modulation signal applied to VL. This is because the noise gain is equal to 2, and since there is no inversion in this connection, it is the opposite of the offset.

The result of the lower envelope output is the sum of these two effects, which produce the lower envelope of the AM waveform. See Figure 82.

This circuit changes the modulation depth by changing the amplitude of the modulation signal. This changes the amplitude of the upper and lower envelope waveforms.

The modulation depth can also be changed by changing the DC bias applied to VH. In this case, the amplitudes of the upper and lower envelope waveforms remain the same, but the spacing between them changes. This changes the ratio of the envelope amplitude to the overall waveform amplitude.

Layout Considerations

The specified high-speed performance of the AD8036 and AD8037 requires careful attention to board layout and component selection. Proper RF design techniques and selection of low-pass parasitic components are mandatory.

The PCB should have a ground plane covering all unused sections on the component side of the board to provide a low impedance path. The ground plane should be kept away from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for power and input clamp bypassing (see Figure 83). One end should be connected to the ground plane and the other end should be within 1/8" of each power supply and clamping pin. Another large (0.47µF–10µF) tantalum electrolytic capacitor should be paralleled, although not necessarily so close, to provide current at the output for fast, large signal changes.

The feedback resistor should be placed close to the inverting input pin to keep stray capacitance at this node to a minimum. At the inverter input, a capacitance change of less than 1pf will significantly affect high-speed performance.

Long signal paths (greater than 1 inch) should use stripline design techniques. They should be designed with a characteristic impedance of 50Ω or 75Ω and properly terminated at each end.

Evaluation Committee

Evaluation boards for the AD8036 and AD8037 are available that have been carefully laid out and tested to achieve the specified high-speed performance of the device. See the ordering guide for ordering information.

The evaluation board layout can be used as shown or as a guideline for the evaluation board layout.