feature

7.6MHz 5th-order Y,C filter with composite summer 14dB notch filter at 4.425MHz to 4.6MHz capable of handling stereo 27MHz with 50dB stopband attenuation on Y,C, and CV output on Y,C, flat Better than 0.5dB to 4.2MHz, and CV output to drive EQ and notch filter group delay for RF modulators - 180ns with no external frequency selection components or <5ns group delay on clock Y, C and CV outputs AC Coupled input AC or DC coupled output PAL frequency continuous time low pass filter available for Y, C, CV <1.4% differential gain, 0.7° differential phase Low slope on Y, C and CV channels Integrated DC restoration circuit

application

cable set-top box

satellite set top box

DVD player

illustrate

The FMS6406 is a dual Y/C fifth-order Butterworth low-pass video filter group delay optimized for minimal overshoot and flatness. The device also contains a summing circuit to generate filtered composite video, audio trapping and group delay compensation circuits. Audio traps remove subsequent RF audio carriers at spectral locations of video information. The group delay circuit predistortion compensates for the signal group delay distortion inherent in the receiver IF filter. In a typical application, the Y and C input signals from the dac are AC coupled to the filter. Both channels have DC restoration circuitry, in video sync. Use separate feedback clips for the Y and C channels. The clamp pulse is from the Y channel. All outputs are capable of driving 2Vpp, AC or DC coupled, one or two video loads. A single video load consists of a 75W series impedance matching resistor connected to a terminated 75W line, which represents 150 watts loaded onto the part. The double load is at the same time and will move towards the part. At 1Vpp, the Y, C, and CV signals have a gain of 6dB input level. All video channels are clamped during synchronization to establish proper output voltage reference levels.

Absolute Maximum Ratings "Absolute Maximum Ratings" are values for which the safety of the device is not guaranteed. This device should not operate within these limitations. Parameter values defined in the Electrical Characteristics table are not guaranteed absolute maximum ratings. The Recommended Operating Conditions table defines the conditions

Typical Performance Characteristics Tc=25°C, Vi=1Vpp, VCC=5V, HD/N_SD=0, RSOURCE=37.5Ω, all inputs AC-coupled 0.1µF, all outputs AC-coupled 220µF to 150Ω, referenced to 400kHz; unless otherwise noted

Typical Performance Characteristics Tc=25°C, Vi=1Vpp, VCC=5V, HD/N_SD=0, RSOURCE=37.5Ω, all inputs AC-coupled 0.1µF, all outputs AC-coupled 220µF to 150Ω, referenced to 400kHz; unless otherwise noted .

Typical Performance Characteristics Tc=25°C, Vi=1Vpp, VCC=5V, HD/N_SD=0, RSOURCE=37.5Ω, all inputs AC-coupled 0.1µF, all outputs AC-coupled 220µF to 150Ω, referenced to 400kHz; unless otherwise noted .

Description of the function: This product is a two-channel single-chip continuous-time reconstruction of luminance and chrominance signals from S-Video D/A sources. The composite video output is generated by summing the Y and C outputs. The chip is designed to be AC coupled in and will couple out equally well as AC or DC operation. The reconstruction filter provides a 5th order Butterworth group delay equalization response. This provides delay and amplitude for a maximum flat response. Each of the four outputs is capable of driving 2Vpp into a 75Ω load. During the sync interval, all channels are clamped to set the appropriate minimum output DC level. The effective input time constant of this action is greatly reduced allowing the use of small low-cost coupling capacitors. The net effect is that the input will settle to 10mV within 5ms for any DC shift present in the input video signal. In most applications, the input coupling capacitor is 0.1µF. The Y and C inputs typically sink 1µA during active video, and typically slope the horizontal line to 2mV at the Y output. During synchronization, the clamp recovers by generating an average leakage current above 20 μA over the clamp interval. Any changes in the coupling capacitance will affect the amount of slope of each line. Any decreasing tilt will increase with the settling time. Luminance (Y) I/O The typical luma input is driven by a low impedance 1Vpp supply or the output of a 75Ω terminated line is driven by the output of a current DAC.

In either case the inputs must be capacitively coupled to allow the synchronization detection and DC recovery circuits to function properly. All outputs are capable of driving 2Vpp, AC or DC coupled, one or two video loads. A single video load consists of a series of 75Ω impedance matching resistors connected to a terminated 75Ω line, which represents a 150Ω load on the part. The double load is where these parallel circuits will go to parts. At 1Vpp, the Y, C, and CV signals have a gain of 6dB input level. Even having two loads will produce a full 2Vpp signal on its output pins. Chroma (C) I/O The chroma input can be driven in the same way as the luma input, but is typically only a 0.7Vpp signal. Because the chrominance signal does not contain any DC content, the output signal can use capacitors as small as 0.1µF if DC coupling is not required. Composite video (CV) output The composite video output driver is the same as another output. When driving dual loads if the other output is connected carelessly short if those loads are AC coupled. Equalizer/Notch (EQ_Notch) Output This output is designed to drive a 600Ω load to 2Vpp, which would serve its primary purpose of driving a modulator load. Layout Considerations General layout and power supply bypass performance and thermal characteristics at high frequency. The FMS6406DEMO is a full power four-layer board and ground. Following this layout configuration will provide the best performance and thermal characteristics. For best results, follow these steps High Frequency Layout Basis: Include 1µF and 0.1µF Ceramic Bypass Capacitors Place 1µF Capacitors on Power Pins Place 0.1µF Capacitors on Power Pins For multilayer boards, use a large ground plane to help Heat dissipation For two-layer boards, use a ground plane that extends at least 0.5" beyond the device Minimize all trace lengths to reduce series inductance